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authorAnton Blanchard <anton@samba.org>2013-05-01 16:06:33 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-05-05 19:25:35 -0400
commit73d2fb758e678c93bc76d40876c2359f0729b0ef (patch)
treed4831170cd6c5373f0daab7589e70a4821c9099d /arch/powerpc/kernel
parent01227a889ed56ae53aeebb9f93be9d54dd8b2de8 (diff)
powerpc: Emulate non privileged DSCR read and write
POWER8 allows read and write of the DSCR in userspace. We added kernel emulation so applications could always use the instructions regardless of the CPU type. Unfortunately there are two SPRs for the DSCR and we only added emulation for the privileged one. Add code to match the non privileged one. A simple test was created to verify the fix: http://ozlabs.org/~anton/junkcode/user_dscr_test.c Without the patch we get a SIGILL and it passes with the patch. Signed-off-by: Anton Blanchard <anton@samba.org> Cc: <stable@kernel.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/traps.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 37cc40ef5043..83efa2f7d926 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -970,7 +970,10 @@ static int emulate_instruction(struct pt_regs *regs)
970 970
971#ifdef CONFIG_PPC64 971#ifdef CONFIG_PPC64
972 /* Emulate the mfspr rD, DSCR. */ 972 /* Emulate the mfspr rD, DSCR. */
973 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && 973 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
974 PPC_INST_MFSPR_DSCR_USER) ||
975 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
976 PPC_INST_MFSPR_DSCR)) &&
974 cpu_has_feature(CPU_FTR_DSCR)) { 977 cpu_has_feature(CPU_FTR_DSCR)) {
975 PPC_WARN_EMULATED(mfdscr, regs); 978 PPC_WARN_EMULATED(mfdscr, regs);
976 rd = (instword >> 21) & 0x1f; 979 rd = (instword >> 21) & 0x1f;
@@ -978,7 +981,10 @@ static int emulate_instruction(struct pt_regs *regs)
978 return 0; 981 return 0;
979 } 982 }
980 /* Emulate the mtspr DSCR, rD. */ 983 /* Emulate the mtspr DSCR, rD. */
981 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && 984 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
985 PPC_INST_MTSPR_DSCR_USER) ||
986 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
987 PPC_INST_MTSPR_DSCR)) &&
982 cpu_has_feature(CPU_FTR_DSCR)) { 988 cpu_has_feature(CPU_FTR_DSCR)) {
983 PPC_WARN_EMULATED(mtdscr, regs); 989 PPC_WARN_EMULATED(mtdscr, regs);
984 rd = (instword >> 21) & 0x1f; 990 rd = (instword >> 21) & 0x1f;