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authorLEROY Christophe <christophe.leroy@c-s.fr>2014-09-19 04:36:09 -0400
committerScott Wood <scottwood@freescale.com>2014-11-07 19:10:43 -0500
commit4094f28f90adab007eca9babf28f606a40a83032 (patch)
tree4a9d47ec744360da9391ad705693ad8f5993c664 /arch/powerpc/kernel
parentd3e40262e7d05236bf4c2c4fdf007589ba8af97a (diff)
powerpc/8xx: set PTE bit 22 off TLBmiss
No need to re-set this bit at each TLB miss. Let's set it in the PTE. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/head_8xx.S10
1 files changed, 2 insertions, 8 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 6e9124177f19..8d6e6830a675 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -447,14 +447,8 @@ DataStoreTLBMiss:
447 and r11, r11, r10 447 and r11, r11, r10
448 rlwimi r10, r11, 0, _PAGE_PRESENT 448 rlwimi r10, r11, 0, _PAGE_PRESENT
449#endif 449#endif
450 /* Honour kernel RO, User NA */ 450 /* invert RW */
451 /* 0x200 == Extended encoding, bit 22 */ 451 xori r10, r10, _PAGE_RW
452 rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */
453 /* r11 = (r10 & _PAGE_RW) >> 1 */
454 rlwinm r11, r10, 32-1, 0x200
455 or r10, r11, r10
456 /* invert RW and 0x200 bits */
457 xori r10, r10, _PAGE_RW | 0x200
458 452
459 /* The Linux PTE won't go exactly into the MMU TLB. 453 /* The Linux PTE won't go exactly into the MMU TLB.
460 * Software indicator bits 22 and 28 must be clear. 454 * Software indicator bits 22 and 28 must be clear.