Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (23 commits)
  [POWERPC] Add arch/powerpc support for the Motorola PrPMC2800
  [POWERPC] Add bootwrapper support for Motorola PrPMC2800 platform
  [POWERPC] Add DTS file for the Motorola PrPMC2800 platform
  [POWERPC] Check cache coherency of kernel vs firmware
  [POWERPC] Add Marvell mv64x60 PCI bridge support
  [POWERPC] Create Marvell mv64x60 I2C platform_data
  [POWERPC] Create Marvell mv64x60 ethernet platform_data
  [POWERPC] Create Marvell mv64x60 MPSC (serial) platform_data
  [POWERPC] Add interrupt support for Marvell mv64x60 chips
  [POWERPC] Add bootwrapper support for Marvell/mv64x60 I2C
  [POWERPC] Add bootwrapper support for Marvell MPSC
  [POWERPC] Add bootwrapper support for Marvell/mv64x60 hostbridge
  [POWERPC] Add Makefile rules to wrap dts file in zImage
  [POWERPC] Spelling fixes: arch/ppc/
  [POWERPC] U-boot passes the initrd as start/end, not start/size.
  [POWERPC] PS3: Update ps3_defconfig
  [POWERPC] PS3: Fix request_irq warning
  [POWERPC] Don't complain if size-cells == 0 in prom_parse()
  [POWERPC] Simplify smp_space_timers
  [POWERPC] Trivial ps3 warning fixes
  ...

3 files changed, 44 insertions, 18 deletions

diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index b5c96af955c6..3786dcc8a7b6 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -24,7 +24,7 @@
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS       4
 #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
-                        (ns) > 0)
+                        (ns) >= 0)
 
 static struct of_bus *of_match_bus(struct device_node *np);
 static int __of_address_to_resource(struct device_node *dev,
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 370803722e47..ed07a198f8d6 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -530,3 +530,44 @@ void __init setup_panic(void)
 {
         atomic_notifier_chain_register(&panic_notifier_list, &ppc_panic_block);
 }
+
+#ifdef CONFIG_CHECK_CACHE_COHERENCY
+/*
+ * For platforms that have configurable cache-coherency.  This function
+ * checks that the cache coherency setting of the kernel matches the setting
+ * left by the firmware, as indicated in the device tree.  Since a mismatch
+ * will eventually result in DMA failures, we print * and error and call
+ * BUG() in that case.
+ */
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define KERNEL_COHERENCY        0
+#else
+#define KERNEL_COHERENCY        1
+#endif
+
+static int __init check_cache_coherency(void)
+{
+        struct device_node *np;
+        const void *prop;
+        int devtree_coherency;
+
+        np = of_find_node_by_path("/");
+        prop = of_get_property(np, "coherency-off", NULL);
+        of_node_put(np);
+
+        devtree_coherency = prop ? 0 : 1;
+
+        if (devtree_coherency != KERNEL_COHERENCY) {
+                printk(KERN_ERR
+                        "kernel coherency:%s != device tree_coherency:%s\n",
+                        KERNEL_COHERENCY ? "on" : "off",
+                        devtree_coherency ? "on" : "off");
+                BUG();
+        }
+
+        return 0;
+}
+
+late_initcall(check_cache_coherency);
+#endif /* CONFIG_CHECK_CACHE_COHERENCY */
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 7cedef8f5f70..2c8564d54e4d 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -711,30 +711,15 @@ void wakeup_decrementer(void)
 void __init smp_space_timers(unsigned int max_cpus)
 {
         int i;
-        unsigned long half = tb_ticks_per_jiffy / 2;
-        unsigned long offset = tb_ticks_per_jiffy / max_cpus;
         u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
 
         /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
         previous_tb -= tb_ticks_per_jiffy;
-        /*
-         * The stolen time calculation for POWER5 shared-processor LPAR
-         * systems works better if the two threads' timebase interrupts
-         * are staggered by half a jiffy with respect to each other.
-         */
+
         for_each_possible_cpu(i) {
                 if (i == boot_cpuid)
                         continue;
-                if (i == (boot_cpuid ^ 1))
-                        per_cpu(last_jiffy, i) =
-                                per_cpu(last_jiffy, boot_cpuid) - half;
-                else if (i & 1)
-                        per_cpu(last_jiffy, i) =
-                                per_cpu(last_jiffy, i ^ 1) + half;
-                else {
-                        previous_tb += offset;
-                        per_cpu(last_jiffy, i) = previous_tb;
-                }
+                per_cpu(last_jiffy, i) = previous_tb;
         }
 }
 #endif