From e147ec8f18082efb700763bed4fe24f73ca50a2c Mon Sep 17 00:00:00 2001 From: will schmidt Date: Fri, 11 May 2007 23:34:16 +1000 Subject: [POWERPC] Simplify smp_space_timers Greatly simplify the function smp_space_timers. The stolen time calculation (per comment within the code) doesn't need the half-jiffy stagger any more. There isn't an issue with bouncing off global locks, so we really shouldn't need any sort of staggering at all. However, the last_jiffy value still needs to be set. This removes the extra stagger logic, and just sets the values. This change should benefit applications that rely on barrier synchronization, and will help cut down OS jitter. Boot tested across the board (G5,power3,power4,power5,970mp blade). Signed-off-by: Will Schmidt Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/time.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) (limited to 'arch/powerpc/kernel') diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 7cedef8f5f70..2c8564d54e4d 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -711,30 +711,15 @@ void wakeup_decrementer(void) void __init smp_space_timers(unsigned int max_cpus) { int i; - unsigned long half = tb_ticks_per_jiffy / 2; - unsigned long offset = tb_ticks_per_jiffy / max_cpus; u64 previous_tb = per_cpu(last_jiffy, boot_cpuid); /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */ previous_tb -= tb_ticks_per_jiffy; - /* - * The stolen time calculation for POWER5 shared-processor LPAR - * systems works better if the two threads' timebase interrupts - * are staggered by half a jiffy with respect to each other. - */ + for_each_possible_cpu(i) { if (i == boot_cpuid) continue; - if (i == (boot_cpuid ^ 1)) - per_cpu(last_jiffy, i) = - per_cpu(last_jiffy, boot_cpuid) - half; - else if (i & 1) - per_cpu(last_jiffy, i) = - per_cpu(last_jiffy, i ^ 1) + half; - else { - previous_tb += offset; - per_cpu(last_jiffy, i) = previous_tb; - } + per_cpu(last_jiffy, i) = previous_tb; } } #endif -- cgit v1.2.2 From fd6e9d3945ee122eb513ada8b17296d243c1ce5e Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Sat, 12 May 2007 03:19:38 +1000 Subject: [POWERPC] Don't complain if size-cells == 0 in prom_parse() An mdio bus scan was added with ucc_geth phylib migration patches, now machines complain on boot, saying: prom_parse: Bad cell count for /qe@e0100000/mdio@2120/ethernet-phy@00 prom_parse: Bad cell count for /qe@e0100000/mdio@2120/ethernet-phy@01 since size-cells can indeed be 0, this patch fixes the check. Signed-off-by: Kim Phillips Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/prom_parse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/kernel') diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c index b5c96af955c6..3786dcc8a7b6 100644 --- a/arch/powerpc/kernel/prom_parse.c +++ b/arch/powerpc/kernel/prom_parse.c @@ -24,7 +24,7 @@ /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) + (ns) >= 0) static struct of_bus *of_match_bus(struct device_node *np); static int __of_address_to_resource(struct device_node *dev, -- cgit v1.2.2 From 06cce43cf0980d0ed3581458fd23522ca2d24e42 Mon Sep 17 00:00:00 2001 From: Dale Farnsworth Date: Sat, 12 May 2007 10:57:35 +1000 Subject: [POWERPC] Check cache coherency of kernel vs firmware check_cache_coherency() verifies that the cache coherency setting of the kernel (CONFIG_NOT_COHERENT_CACHE) matches that left by the firmware, as indicated by coherency-off device tree property. Signed-off-by: Dale Farnsworth Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/setup-common.c | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/powerpc/kernel') diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 370803722e47..ed07a198f8d6 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -530,3 +530,44 @@ void __init setup_panic(void) { atomic_notifier_chain_register(&panic_notifier_list, &ppc_panic_block); } + +#ifdef CONFIG_CHECK_CACHE_COHERENCY +/* + * For platforms that have configurable cache-coherency. This function + * checks that the cache coherency setting of the kernel matches the setting + * left by the firmware, as indicated in the device tree. Since a mismatch + * will eventually result in DMA failures, we print * and error and call + * BUG() in that case. + */ + +#ifdef CONFIG_NOT_COHERENT_CACHE +#define KERNEL_COHERENCY 0 +#else +#define KERNEL_COHERENCY 1 +#endif + +static int __init check_cache_coherency(void) +{ + struct device_node *np; + const void *prop; + int devtree_coherency; + + np = of_find_node_by_path("/"); + prop = of_get_property(np, "coherency-off", NULL); + of_node_put(np); + + devtree_coherency = prop ? 0 : 1; + + if (devtree_coherency != KERNEL_COHERENCY) { + printk(KERN_ERR + "kernel coherency:%s != device tree_coherency:%s\n", + KERNEL_COHERENCY ? "on" : "off", + devtree_coherency ? "on" : "off"); + BUG(); + } + + return 0; +} + +late_initcall(check_cache_coherency); +#endif /* CONFIG_CHECK_CACHE_COHERENCY */ -- cgit v1.2.2