powerpc/85xx: add DOZE/NAP support for e500 core

The e500 core enter DOZE/NAP power-saving modes when the core go to
cpu_idle routine.

The power management default running mode is DOZE, If the user

echo 1 > /proc/sys/kernel/powersave-nap

the system will change to NAP running mode.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 47 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 7c2b65380658..c4268500e856 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -39,6 +39,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/cache.h>
 #include "head_booke.h"
 
 /* As with the other PowerPC ports, it is expected that when code
@@ -1071,6 +1072,52 @@ _GLOBAL(set_context)
         isync                   /* Force context change */
         blr
 
+_GLOBAL(flush_dcache_L1)
+        mfspr   r3,SPRN_L1CFG0
+
+        rlwinm  r5,r3,9,3       /* Extract cache block size */
+        twlgti  r5,1            /* Only 32 and 64 byte cache blocks
+                                 * are currently defined.
+                                 */
+        li      r4,32
+        subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
+                                 *      log2(number of ways)
+                                 */
+        slw     r5,r4,r5        /* r5 = cache block size */
+
+        rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
+        mulli   r7,r7,13        /* An 8-way cache will require 13
+                                 * loads per set.
+                                 */
+        slw     r7,r7,r6
+
+        /* save off HID0 and set DCFA */
+        mfspr   r8,SPRN_HID0
+        ori     r9,r8,HID0_DCFA@l
+        mtspr   SPRN_HID0,r9
+        isync
+
+        lis     r4,KERNELBASE@h
+        mtctr   r7
+
+1:      lwz     r3,0(r4)        /* Load... */
+        add     r4,r4,r5
+        bdnz    1b
+
+        msync
+        lis     r4,KERNELBASE@h
+        mtctr   r7
+
+1:      dcbf    0,r4            /* ...and flush. */
+        add     r4,r4,r5
+        bdnz    1b
+        
+        /* restore HID0 */
+        mtspr   SPRN_HID0,r8
+        isync
+
+        blr
+
 /*
  * We put a few things here that have to be page-aligned. This stuff
  * goes at the beginning of the data segment, which is page-aligned.