[POWERPC] 8xx: Work around CPU15 erratum.

The CPU15 erratum on MPC8xx chips can cause incorrect code execution
under certain circumstances, where there is a conditional or indirect
branch in the last word of a page, with a target in the last cache line
of the next page.  This patch implements one of the suggested
workarounds, by forcing a TLB miss whenever execution crosses a page
boundary.  This is done by invalidating the pages before and after the
one being loaded into the TLB in the ITLB miss handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9c30938aad52..f7458396cd7c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -298,6 +298,12 @@ InstructionTLBMiss:
         stw     r10, 0(r0)
         stw     r11, 4(r0)
         mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
+#ifdef CONFIG_8xx_CPU15
+        addi    r11, r10, 0x1000
+        tlbie   r11
+        addi    r11, r10, -0x1000
+        tlbie   r11
+#endif
         DO_8xx_CPU6(0x3780, r3)
         mtspr   SPRN_MD_EPN, r10        /* Have to use MD_EPN for walk, MI_EPN can't */
         mfspr   r10, SPRN_M_TWB /* Get level 1 table entry address */