powerpc: Base support for exceptions using HSRR0/1

Pass the register type to the prolog, also provides alternate "HV"
version of hardware interrupt (0x500) and adjust LPES accordingly

We tag those interrupts by setting bit 0x2 in the trap number

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S
index f2b317817c4e..e801ef15d6d0 100644
--- a/arch/powerpc/kernel/cpu_setup_power7.S
+++ b/arch/powerpc/kernel/cpu_setup_power7.S
@@ -52,13 +52,14 @@ __init_hvmode_206:
 __init_LPCR:
         /* Setup a sane LPCR:
          *
-         *   LPES = 0b11 (SRR0/1 used for 0x500)
+         *   LPES = 0b01 (HSRR0/1 used for 0x500)
          *   PECE = 0b111
          *
          * Other bits untouched for now
          */
         mfspr   r3,SPRN_LPCR
         ori     r3,r3,(LPCR_LPES0|LPCR_LPES1)
+        xori    r3,r3, LPCR_LPES0
         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
         mtspr   SPRN_LPCR,r3
         isync