Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Ben Herrenschmidt:
 "So here's my next branch for powerpc.  A bit late as I was on vacation
  last week.  It's mostly the same stuff that was in next already, I
  just added two patches today which are the wiring up of lockref for
  powerpc, which for some reason fell through the cracks last time and
  is trivial.

  The highlights are, in addition to a bunch of bug fixes:

   - Reworked Machine Check handling on kernels running without a
     hypervisor (or acting as a hypervisor).  Provides hooks to handle
     some errors in real mode such as TLB errors, handle SLB errors,
     etc...

   - Support for retrieving memory error information from the service
     processor on IBM servers running without a hypervisor and routing
     them to the memory poison infrastructure.

   - _PAGE_NUMA support on server processors

   - 32-bit BookE relocatable kernel support

   - FSL e6500 hardware tablewalk support

   - A bunch of new/revived board support

   - FSL e6500 deeper idle states and altivec powerdown support

  You'll notice a generic mm change here, it has been acked by the
  relevant authorities and is a pre-req for our _PAGE_NUMA support"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (121 commits)
  powerpc: Implement arch_spin_is_locked() using arch_spin_value_unlocked()
  powerpc: Add support for the optimised lockref implementation
  powerpc/powernv: Call OPAL sync before kexec'ing
  powerpc/eeh: Escalate error on non-existing PE
  powerpc/eeh: Handle multiple EEH errors
  powerpc: Fix transactional FP/VMX/VSX unavailable handlers
  powerpc: Don't corrupt transactional state when using FP/VMX in kernel
  powerpc: Reclaim two unused thread_info flag bits
  powerpc: Fix races with irq_work
  Move precessing of MCE queued event out from syscall exit path.
  pseries/cpuidle: Remove redundant call to ppc64_runlatch_off() in cpu idle routines
  powerpc: Make add_system_ram_resources() __init
  powerpc: add SATA_MV to ppc64_defconfig
  powerpc/powernv: Increase candidate fw image size
  powerpc: Add debug checks to catch invalid cpu-to-node mappings
  powerpc: Fix the setup of CPU-to-Node mappings during CPU online
  powerpc/iommu: Don't detach device without IOMMU group
  powerpc/eeh: Hotplug improvement
  powerpc/eeh: Call opal_pci_reinit() on powernv for restoring config space
  powerpc/eeh: Add restore_config operation
  ...

1 files changed, 54 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7290b7..cc2d8962e090 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,57 @@ _GLOBAL(__e500_dcache_setup)
         isync
         blr
 
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT              50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+        mfspr   r3, SPRN_PWRMGTCR0
+
+        /* Set PW20_WAIT bit, enable pw20 state*/
+        ori     r3, r3, PWRMGTCR0_PW20_WAIT
+        li      r11, PW20_WAIT_IDLE_BIT
+
+        /* Set Automatic PW20 Core Idle Count */
+        rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+        mtspr   SPRN_PWRMGTCR0, r3
+
+        blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT                50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+        mfspr   r3, SPRN_PWRMGTCR0
+
+        /* Enable Altivec Idle */
+        oris    r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+        li      r11, AV_WAIT_IDLE_BIT
+
+        /* Set Automatic AltiVec Idle Count */
+        rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+        mtspr   SPRN_PWRMGTCR0, r3
+
+        blr
+
 _GLOBAL(__setup_cpu_e6500)
         mflr    r6
 #ifdef CONFIG_PPC64
         bl      .setup_altivec_ivors
+        /* Touch IVOR42 only if the CPU supports E.HV category */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
+        bl      .setup_lrat_ivor
+1:
 #endif
+        bl      setup_pw20_idle
+        bl      setup_altivec_idle
         bl      __setup_cpu_e5500
         mtlr    r6
         blr
@@ -119,6 +165,14 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
         mflr    r5
         bl      .setup_altivec_ivors
+        /* Touch IVOR42 only if the CPU supports E.HV category */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
+        bl      .setup_lrat_ivor
+1:
+        bl      .setup_pw20_idle
+        bl      .setup_altivec_idle
         bl      __restore_cpu_e5500
         mtlr    r5
         blr