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authorGavin Shan <shangw@linux.vnet.ibm.com>2013-04-25 15:20:59 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-04-26 02:09:59 -0400
commit137436c9a6ee385c883db09e41af763888ee7642 (patch)
tree251fb4b23142e8dc05a5824359ba73e383b0434d /arch/powerpc/include
parenta486bdb0e9da8d876d6ff4efc3138d35e141c0b5 (diff)
powerpc/powernv: Patch MSI EOI handler on P8
The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional steps to handle the P/Q bits in IVE before EOIing the corresponding interrupt. The patch changes the EOI handler to cover that. we have individual IRQ chip in each PHB instance. During the MSI IRQ setup time, the IRQ chip is copied over from the original one for that IRQ, and the EOI handler is patched with the one that will handle the P/Q bits (As Ben suggested). Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/opal.h2
-rw-r--r--arch/powerpc/include/asm/xics.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index a4b28f165b6c..b6c8b58b1d76 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -117,6 +117,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
117#define OPAL_SET_SLOT_LED_STATUS 55 117#define OPAL_SET_SLOT_LED_STATUS 55
118#define OPAL_GET_EPOW_STATUS 56 118#define OPAL_GET_EPOW_STATUS 56
119#define OPAL_SET_SYSTEM_ATTENTION_LED 57 119#define OPAL_SET_SYSTEM_ATTENTION_LED 57
120#define OPAL_PCI_MSI_EOI 63
120 121
121#ifndef __ASSEMBLY__ 122#ifndef __ASSEMBLY__
122 123
@@ -506,6 +507,7 @@ int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
506 uint8_t *p_bit, uint8_t *q_bit); 507 uint8_t *p_bit, uint8_t *q_bit);
507int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 508int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
508 uint8_t p_bit, uint8_t q_bit); 509 uint8_t p_bit, uint8_t q_bit);
510int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
509int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 511int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
510 uint32_t xive_num); 512 uint32_t xive_num);
511int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 513int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
index 4ae9a09c3b89..282d43a0c855 100644
--- a/arch/powerpc/include/asm/xics.h
+++ b/arch/powerpc/include/asm/xics.h
@@ -150,6 +150,7 @@ extern void xics_register_ics(struct ics *ics);
150extern void xics_teardown_cpu(void); 150extern void xics_teardown_cpu(void);
151extern void xics_kexec_teardown_cpu(int secondary); 151extern void xics_kexec_teardown_cpu(int secondary);
152extern void xics_migrate_irqs_away(void); 152extern void xics_migrate_irqs_away(void);
153extern void icp_native_eoi(struct irq_data *d);
153#ifdef CONFIG_SMP 154#ifdef CONFIG_SMP
154extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, 155extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
155 unsigned int strict_check); 156 unsigned int strict_check);