Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

103 files changed, 2251 insertions, 856 deletions

diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
index 4b0e15206006..bdf0563ba423 100644
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -93,7 +93,7 @@ typedef struct	mem_ctlr {
 } memctl8xx_t;
 
 /*-----------------------------------------------------------------------
- * BR - Memory Controler: Base Register                                 16-9
+ * BR - Memory Controller: Base Register                                        16-9
  */
 #define BR_BA_MSK       0xffff8000      /* Base Address Mask                    */
 #define BR_AT_MSK       0x00007000      /* Address Type Mask                    */
@@ -110,7 +110,7 @@ typedef struct	mem_ctlr {
 #define BR_V            0x00000001      /* Bank Valid                           */
 
 /*-----------------------------------------------------------------------
- * OR - Memory Controler: Option Register                               16-11
+ * OR - Memory Controller: Option Register                              16-11
  */
 #define OR_AM_MSK       0xffff8000      /* Address Mask Mask                    */
 #define OR_ATM_MSK      0x00007000      /* Address Type Mask Mask               */
@@ -393,8 +393,8 @@ typedef struct fec {
         uint    fec_addr_low;           /* lower 32 bits of station address     */
         ushort  fec_addr_high;          /* upper 16 bits of station address     */
         ushort  res1;                   /* reserved                             */
-        uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
-        uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
+        uint    fec_grp_hash_table_high;        /* upper 32-bits of hash table          */
+        uint    fec_grp_hash_table_low; /* lower 32-bits of hash table          */
         uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
         uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
         uint    fec_r_buff_size;        /* Rx buffer size                       */
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 30964ae2d096..f18c6d9b9510 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -209,8 +209,8 @@ static __inline__ unsigned long ffz(unsigned long x)
                 return BITS_PER_LONG;
 
         /*
-         * Calculate the bit position of the least signficant '1' bit in x
-         * (since x has been changed this will actually be the least signficant
+         * Calculate the bit position of the least significant '1' bit in x
+         * (since x has been changed this will actually be the least significant
          * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
          * is the least significant * (RIGHT-most) 1-bit of the value in x.
          */
@@ -267,73 +267,70 @@ static __inline__ int fls64(__u64 x)
 #include <asm-generic/bitops/fls64.h>
 #endif /* __powerpc64__ */
 
+#ifdef CONFIG_PPC64
+unsigned int __arch_hweight8(unsigned int w);
+unsigned int __arch_hweight16(unsigned int w);
+unsigned int __arch_hweight32(unsigned int w);
+unsigned long __arch_hweight64(__u64 w);
+#include <asm-generic/bitops/const_hweight.h>
+#else
 #include <asm-generic/bitops/hweight.h>
+#endif
+
 #include <asm-generic/bitops/find.h>
 
 /* Little-endian versions */
 
-static __inline__ int test_le_bit(unsigned long nr,
-                                  __const__ unsigned long *addr)
+static __inline__ int test_bit_le(unsigned long nr,
+                                  __const__ void *addr)
 {
         __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
         return (tmp[nr >> 3] >> (nr & 7)) & 1;
 }
 
-#define __set_le_bit(nr, addr) \
-        __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
-#define __clear_le_bit(nr, addr) \
-        __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+static inline void __set_bit_le(int nr, void *addr)
+{
+        __set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
 
-#define test_and_set_le_bit(nr, addr) \
-        test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
-#define test_and_clear_le_bit(nr, addr) \
-        test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+static inline void __clear_bit_le(int nr, void *addr)
+{
+        __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
 
-#define __test_and_set_le_bit(nr, addr) \
-        __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
-#define __test_and_clear_le_bit(nr, addr) \
-        __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+static inline int test_and_set_bit_le(int nr, void *addr)
+{
+        return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
 
-#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
-unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
+static inline int test_and_clear_bit_le(int nr, void *addr)
+{
+        return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
+
+static inline int __test_and_set_bit_le(int nr, void *addr)
+{
+        return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
+
+static inline int __test_and_clear_bit_le(int nr, void *addr)
+{
+        return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
+}
+
+#define find_first_zero_bit_le(addr, size) \
+        find_next_zero_bit_le((addr), (size), 0)
+unsigned long find_next_zero_bit_le(const void *addr,
                                     unsigned long size, unsigned long offset);
 
-unsigned long generic_find_next_le_bit(const unsigned long *addr,
+unsigned long find_next_bit_le(const void *addr,
                                     unsigned long size, unsigned long offset);
 /* Bitmap functions for the ext2 filesystem */
 
-#define ext2_set_bit(nr,addr) \
-        __test_and_set_le_bit((nr), (unsigned long*)addr)
-#define ext2_clear_bit(nr, addr) \
-        __test_and_clear_le_bit((nr), (unsigned long*)addr)
-
 #define ext2_set_bit_atomic(lock, nr, addr) \
-        test_and_set_le_bit((nr), (unsigned long*)addr)
+        test_and_set_bit_le((nr), (unsigned long*)addr)
 #define ext2_clear_bit_atomic(lock, nr, addr) \
-        test_and_clear_le_bit((nr), (unsigned long*)addr)
-
-#define ext2_test_bit(nr, addr)      test_le_bit((nr),(unsigned long*)addr)
-
-#define ext2_find_first_zero_bit(addr, size) \
-        find_first_zero_le_bit((unsigned long*)addr, size)
-#define ext2_find_next_zero_bit(addr, size, off) \
-        generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
-
-#define ext2_find_next_bit(addr, size, off) \
-        generic_find_next_le_bit((unsigned long *)addr, size, off)
-/* Bitmap functions for the minix filesystem.  */
-
-#define minix_test_and_set_bit(nr,addr) \
-        __test_and_set_le_bit(nr, (unsigned long *)addr)
-#define minix_set_bit(nr,addr) \
-        __set_le_bit(nr, (unsigned long *)addr)
-#define minix_test_and_clear_bit(nr,addr) \
-        __test_and_clear_le_bit(nr, (unsigned long *)addr)
-#define minix_test_bit(nr,addr) \
-        test_le_bit(nr, (unsigned long *)addr)
-
-#define minix_find_first_zero_bit(addr,size) \
-        find_first_zero_le_bit((unsigned long *)addr, size)
+        test_and_clear_bit_le((nr), (unsigned long*)addr)
 
 #include <asm-generic/bitops/sched.h>
 
diff --git a/arch/powerpc/include/asm/checksum.h b/arch/powerpc/include/asm/checksum.h
index 7cdf358337cf..ce0c28495f9a 100644
--- a/arch/powerpc/include/asm/checksum.h
+++ b/arch/powerpc/include/asm/checksum.h
@@ -52,12 +52,22 @@ extern __wsum csum_partial(const void *buff, int len, __wsum sum);
 extern __wsum csum_partial_copy_generic(const void *src, void *dst,
                                               int len, __wsum sum,
                                               int *src_err, int *dst_err);
+
+#ifdef __powerpc64__
+#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
+extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
+                                      int len, __wsum sum, int *err_ptr);
+#define HAVE_CSUM_COPY_USER
+extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
+                                    int len, __wsum sum, int *err_ptr);
+#else
 /*
  * the same as csum_partial, but copies from src to dst while it
  * checksums.
  */
 #define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
         csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
+#endif
 
 #define csum_partial_copy_nocheck(src, dst, len, sum)   \
         csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index a11d4eac4f97..91010e8f8479 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -140,10 +140,10 @@ static inline void __user *arch_compat_alloc_user_space(long len)
         unsigned long usp = regs->gpr[1];
 
         /*
-         * We cant access below the stack pointer in the 32bit ABI and
+         * We can't access below the stack pointer in the 32bit ABI and
          * can access 288 bytes in the 64bit ABI
          */
-        if (!(test_thread_flag(TIF_32BIT)))
+        if (!is_32bit_task())
                 usp -= 288;
 
         return (void __user *) (usp - len);
@@ -213,7 +213,7 @@ struct compat_shmid64_ds {
 
 static inline int is_compat_task(void)
 {
-        return test_thread_flag(TIF_32BIT);
+        return is_32bit_task();
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
index e50323fe941f..4398a6cdcf53 100644
--- a/arch/powerpc/include/asm/cpm.h
+++ b/arch/powerpc/include/asm/cpm.h
@@ -98,7 +98,7 @@ typedef struct cpm_buf_desc {
 #define BD_SC_INTRPT    (0x1000)        /* Interrupt on change */
 #define BD_SC_LAST      (0x0800)        /* Last buffer in frame */
 #define BD_SC_TC        (0x0400)        /* Transmit CRC */
-#define BD_SC_CM        (0x0200)        /* Continous mode */
+#define BD_SC_CM        (0x0200)        /* Continuous mode */
 #define BD_SC_ID        (0x0100)        /* Rec'd too many idles */
 #define BD_SC_P         (0x0100)        /* xmt preamble */
 #define BD_SC_BR        (0x0020)        /* Break received */
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
index bd07650dca56..8ee4211ca0c6 100644
--- a/arch/powerpc/include/asm/cpm1.h
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -4,7 +4,7 @@
  *
  * This file contains structures and information for the communication
  * processor channels.  Some CPM control and status is available
- * throught the MPC8xx internal memory map.  See immap.h for details.
+ * through the MPC8xx internal memory map.  See immap.h for details.
  * This file only contains what I need for the moment, not the total
  * CPM capabilities.  I (or someone else) will add definitions as they
  * are needed.  -- Dan
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 3a40a992e594..c0d842cfd012 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -154,8 +154,10 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
+#define CPU_FTR_476_DD2                 ASM_CONST(0x0000000000010000)
 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
+#define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x0000000000080000)
 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
@@ -177,33 +179,34 @@ extern const char *powerpc_base_platform;
 #define LONG_ASM_CONST(x)               0
 #endif
 
-#define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
+
+#define CPU_FTR_HVMODE_206              LONG_ASM_CONST(0x0000000800000000)
+#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0000001000000000)
 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
-#define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
 #define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
 #define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 #define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0040000000000000)
 #define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0080000000000000)
 #define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0100000000000000)
+#define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0200000000000000)
+#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0400000000000000)
+#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0800000000000000)
+#define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x1000000000000000)
 
 #ifndef __ASSEMBLY__
 
-#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
-                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
+#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
+                                 MMU_FTR_16M_PAGE)
 
 /* We only set the altivec features if the kernel was compiled with altivec
  * support
@@ -378,10 +381,13 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
             CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
             CPU_FTR_DBELL)
+#define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+            CPU_FTR_DEBUG_LVL_EXC)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
@@ -392,46 +398,55 @@ extern const char *powerpc_base_platform;
             CPU_FTR_MMCRA | CPU_FTR_CTRL)
 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
-            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
+            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
+            CPU_FTR_STCX_CHECKS_ADDRESS)
 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
-            CPU_FTR_CP_USE_DCBTZ)
+            CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS)
 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
-            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_PURR)
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
-            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
+            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
-            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT)
+            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+            CPU_FTR_ICSWX | CPU_FTR_CFAR)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
-            CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
-            CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
+            CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
             CPU_FTR_UNALIGNED_LD_STD)
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-            CPU_FTR_PPCAS_ARCH_V2 | \
-            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
-            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
+            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_PURR | CPU_FTR_REAL_LE)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
+#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
 #ifdef __powerpc64__
+#ifdef CONFIG_PPC_BOOK3E
+#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E5500 | CPU_FTRS_A2)
+#else
 #define CPU_FTRS_POSSIBLE       \
             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
             CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
-            CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
+            CPU_FTR_VSX)
+#endif
 #else
 enum {
         CPU_FTRS_POSSIBLE =
@@ -458,23 +473,28 @@ enum {
             CPU_FTRS_44X | CPU_FTRS_440x6 |
 #endif
 #ifdef CONFIG_PPC_47x
-            CPU_FTRS_47X |
+            CPU_FTRS_47X | CPU_FTR_476_DD2 |
 #endif
 #ifdef CONFIG_E200
             CPU_FTRS_E200 |
 #endif
 #ifdef CONFIG_E500
             CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
+            CPU_FTRS_E5500 |
 #endif
             0,
 };
 #endif /* __powerpc64__ */
 
 #ifdef __powerpc64__
+#ifdef CONFIG_PPC_BOOK3E
+#define CPU_FTRS_ALWAYS         (CPU_FTRS_E5500 & CPU_FTRS_A2)
+#else
 #define CPU_FTRS_ALWAYS         \
             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
             CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
+#endif
 #else
 enum {
         CPU_FTRS_ALWAYS =
@@ -505,6 +525,7 @@ enum {
 #endif
 #ifdef CONFIG_E500
             CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
+            CPU_FTRS_E5500 &
 #endif
             CPU_FTRS_POSSIBLE,
 };
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index a8e18447c62b..ce516e5eb0d3 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -37,16 +37,16 @@ extern cpumask_t threads_core_mask;
  * This can typically be used for things like IPI for tlb invalidations
  * since those need to be done only once per core/TLB
  */
-static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
+static inline cpumask_t cpu_thread_mask_to_cores(const struct cpumask *threads)
 {
         cpumask_t       tmp, res;
         int             i;
 
-        res = CPU_MASK_NONE;
+        cpumask_clear(&res);
         for (i = 0; i < NR_CPUS; i += threads_per_core) {
-                cpus_shift_left(tmp, threads_core_mask, i);
-                if (cpus_intersects(threads, tmp))
-                        cpu_set(i, res);
+                cpumask_shift_left(&tmp, &threads_core_mask, i);
+                if (cpumask_intersects(threads, &tmp))
+                        cpumask_set_cpu(i, &res);
         }
         return res;
 }
@@ -58,25 +58,28 @@ static inline int cpu_nr_cores(void)
 
 static inline cpumask_t cpu_online_cores_map(void)
 {
-        return cpu_thread_mask_to_cores(cpu_online_map);
+        return cpu_thread_mask_to_cores(cpu_online_mask);
 }
 
-static inline int cpu_thread_to_core(int cpu)
-{
-        return cpu >> threads_shift;
-}
+#ifdef CONFIG_SMP
+int cpu_core_index_of_thread(int cpu);
+int cpu_first_thread_of_core(int core);
+#else
+static inline int cpu_core_index_of_thread(int cpu) { return cpu; }
+static inline int cpu_first_thread_of_core(int core) { return core; }
+#endif
 
 static inline int cpu_thread_in_core(int cpu)
 {
         return cpu & (threads_per_core - 1);
 }
 
-static inline int cpu_first_thread_in_core(int cpu)
+static inline int cpu_first_thread_sibling(int cpu)
 {
         return cpu & ~(threads_per_core - 1);
 }
 
-static inline int cpu_last_thread_in_core(int cpu)
+static inline int cpu_last_thread_sibling(int cpu)
 {
         return cpu | (threads_per_core - 1);
 }
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 8bdc6a9e5773..1cf20bdfbeca 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -124,23 +124,23 @@ static inline u64 cputime64_to_jiffies64(const cputime_t ct)
 }
 
 /*
- * Convert cputime <-> milliseconds
+ * Convert cputime <-> microseconds
  */
 extern u64 __cputime_msec_factor;
 
-static inline unsigned long cputime_to_msecs(const cputime_t ct)
+static inline unsigned long cputime_to_usecs(const cputime_t ct)
 {
-        return mulhdu(ct, __cputime_msec_factor);
+        return mulhdu(ct, __cputime_msec_factor) * USEC_PER_MSEC;
 }
 
-static inline cputime_t msecs_to_cputime(const unsigned long ms)
+static inline cputime_t usecs_to_cputime(const unsigned long us)
 {
         cputime_t ct;
         unsigned long sec;
 
         /* have to be a little careful about overflow */
-        ct = ms % 1000;
-        sec = ms / 1000;
+        ct = us % 1000000;
+        sec = us / 1000000;
         if (ct) {
                 ct *= tb_ticks_per_sec;
                 do_div(ct, 1000);
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 0893ab9343a6..9c70d0ca96d4 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -27,9 +27,8 @@ enum ppc_dbell {
         PPC_G_DBELL_MC = 4,     /* guest mcheck doorbell */
 };
 
-extern void doorbell_message_pass(int target, int msg);
+extern void doorbell_cause_ipi(int cpu, unsigned long data);
 extern void doorbell_exception(struct pt_regs *regs);
-extern void doorbell_check_self(void);
 extern void doorbell_setup_this_cpu(void);
 
 static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index a3954e4fcbe2..16d25c0974be 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -9,6 +9,12 @@
 struct dma_map_ops;
 struct device_node;
 
+/*
+ * Arch extensions to struct device.
+ *
+ * When adding fields, consider macio_add_one_device in
+ * drivers/macintosh/macio_asic.c
+ */
 struct dev_archdata {
         /* DMA operations on that device */
         struct dma_map_ops      *dma_ops;
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 8c9c6ad2004e..dd70fac57ec8 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -42,6 +42,7 @@ extern void __dma_free_coherent(size_t size, void *vaddr);
 extern void __dma_sync(void *vaddr, size_t size, int direction);
 extern void __dma_sync_page(struct page *page, unsigned long offset,
                                  size_t size, int direction);
+extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr);
 
 #else /* ! CONFIG_NOT_COHERENT_CACHE */
 /*
@@ -127,19 +128,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
         return dma_ops->dma_supported(dev, mask);
 }
 
-static inline int dma_set_mask(struct device *dev, u64 dma_mask)
-{
-        struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
-        if (unlikely(dma_ops == NULL))
-                return -EIO;
-        if (dma_ops->set_dma_mask != NULL)
-                return dma_ops->set_dma_mask(dev, dma_mask);
-        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
-                return -EIO;
-        *dev->dma_mask = dma_mask;
-        return 0;
-}
+extern int dma_set_mask(struct device *dev, u64 dma_mask);
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
                                        dma_addr_t *dma_handle, gfp_t flag)
@@ -210,6 +199,11 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 
+extern int dma_mmap_coherent(struct device *, struct vm_area_struct *,
+                             void *, dma_addr_t, size_t);
+#define ARCH_HAS_DMA_MMAP_COHERENT
+
+
 static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                 enum dma_data_direction direction)
 {
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index c376eda15313..2b917c69ed15 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -250,7 +250,7 @@ do {								\
  * the 64bit ABI has never had these issues dont enable the workaround
  * even if we have an executable stack.
  */
-# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
+# define elf_read_implies_exec(ex, exec_stk) (is_32bit_task() ? \
                 (exec_stk == EXSTACK_DEFAULT) : 0)
 #else 
 # define SET_PERSONALITY(ex) \
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
index f0fb4fc1f6e6..45921672b97a 100644
--- a/arch/powerpc/include/asm/emulated_ops.h
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -52,6 +52,10 @@ extern struct ppc_emulated {
 #ifdef CONFIG_VSX
         struct ppc_emulated_entry vsx;
 #endif
+#ifdef CONFIG_PPC64
+        struct ppc_emulated_entry mfdscr;
+        struct ppc_emulated_entry mtdscr;
+#endif
 } ppc_emulated;
 
 extern u32 ppc_warn_emulated;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 57c400071995..f5dfe3411f64 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -46,6 +46,7 @@
 #define EX_CCR          60
 #define EX_R3           64
 #define EX_LR           72
+#define EX_CFAR         80
 
 /*
  * We're short on space and time in the exception prolog, so we can't
@@ -56,30 +57,40 @@
 #define LOAD_HANDLER(reg, label)                                        \
         addi    reg,reg,(label)-_stext; /* virt addr of handler ... */
 
-#define EXCEPTION_PROLOG_1(area)                                \
-        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
+/* Exception register prefixes */
+#define EXC_HV  H
+#define EXC_STD
+
+#define EXCEPTION_PROLOG_1(area)                                        \
+        GET_PACA(r13);                                                  \
         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
         std     r10,area+EX_R10(r13);                                   \
         std     r11,area+EX_R11(r13);                                   \
         std     r12,area+EX_R12(r13);                                   \
-        mfspr   r9,SPRN_SPRG_SCRATCH0;                                  \
+        BEGIN_FTR_SECTION_NESTED(66);                                   \
+        mfspr   r10,SPRN_CFAR;                                          \
+        std     r10,area+EX_CFAR(r13);                                  \
+        END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);         \
+        GET_SCRATCH0(r9);                                               \
         std     r9,area+EX_R13(r13);                                    \
         mfcr    r9
 
-#define EXCEPTION_PROLOG_PSERIES_1(label)                               \
+#define __EXCEPTION_PROLOG_PSERIES_1(label, h)                          \
         ld      r12,PACAKBASE(r13);     /* get high part of &label */   \
         ld      r10,PACAKMSR(r13);      /* get MSR value for kernel */  \
-        mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
+        mfspr   r11,SPRN_##h##SRR0;     /* save SRR0 */                 \
         LOAD_HANDLER(r12,label)                                         \
-        mtspr   SPRN_SRR0,r12;                                          \
-        mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
-        mtspr   SPRN_SRR1,r10;                                          \
-        rfid;                                                           \
+        mtspr   SPRN_##h##SRR0,r12;                                     \
+        mfspr   r12,SPRN_##h##SRR1;     /* and SRR1 */                  \
+        mtspr   SPRN_##h##SRR1,r10;                                     \
+        h##rfid;                                                        \
         b       .       /* prevent speculative execution */
+#define EXCEPTION_PROLOG_PSERIES_1(label, h) \
+        __EXCEPTION_PROLOG_PSERIES_1(label, h)
 
-#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
+#define EXCEPTION_PROLOG_PSERIES(area, label, h)                        \
         EXCEPTION_PROLOG_1(area);                                       \
-        EXCEPTION_PROLOG_PSERIES_1(label);
+        EXCEPTION_PROLOG_PSERIES_1(label, h);
 
 /*
  * The common exception prolog is used for all except a few exceptions
@@ -98,10 +109,11 @@
         beq-    1f;                                                        \
         ld      r1,PACAKSAVE(r13);      /* kernel stack to use          */ \
 1:      cmpdi   cr1,r1,0;               /* check if r1 is in userspace  */ \
-        bge-    cr1,2f;                 /* abort if it is               */ \
-        b       3f;                                                        \
-2:      li      r1,(n);                 /* will be reloaded later       */ \
+        blt+    cr1,3f;                 /* abort if it is               */ \
+        li      r1,(n);                 /* will be reloaded later       */ \
         sth     r1,PACA_TRAP_SAVE(r13);                                    \
+        std     r3,area+EX_R3(r13);                                        \
+        addi    r3,r13,area;            /* r3 -> where regs are saved*/    \
         b       bad_stack;                                                 \
 3:      std     r9,_CCR(r1);            /* save CR in stackframe        */ \
         std     r11,_NIP(r1);           /* save SRR0 in stackframe      */ \
@@ -123,6 +135,10 @@
         std     r9,GPR11(r1);                                              \
         std     r10,GPR12(r1);                                             \
         std     r11,GPR13(r1);                                             \
+        BEGIN_FTR_SECTION_NESTED(66);                                      \
+        ld      r10,area+EX_CFAR(r13);                                     \
+        std     r10,ORIG_GPR3(r1);                                         \
+        END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);            \
         ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
         mflr    r9;                     /* save LR in stackframe        */ \
         std     r9,_LINK(r1);                                              \
@@ -137,62 +153,68 @@
         li      r10,0;                                                     \
         ld      r11,exception_marker@toc(r2);                              \
         std     r10,RESULT(r1);         /* clear regs->result           */ \
-        std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
+        std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */ \
+        ACCOUNT_STOLEN_TIME
 
 /*
  * Exception vectors.
  */
-#define STD_EXCEPTION_PSERIES(n, label)                 \
-        . = n;                                          \
+#define STD_EXCEPTION_PSERIES(loc, vec, label)          \
+        . = loc;                                        \
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
-        DO_KVM  n;                                      \
-        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
-        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
+        DO_KVM  vec;                                    \
+        SET_SCRATCH0(r13);              /* save r13 */          \
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_STD)
 
-#define HSTD_EXCEPTION_PSERIES(n, label)                \
-        . = n;                                          \
-        .globl label##_pSeries;                         \
-label##_pSeries:                                        \
+#define STD_EXCEPTION_HV(loc, vec, label)               \
+        . = loc;                                        \
+        .globl label##_hv;                              \
+label##_hv:                                             \
         HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG_SCRATCH0,r20; /* save r20 */  \
-        mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
-        mtspr   SPRN_SRR0,r20;                          \
-        mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
-        mtspr   SPRN_SRR1,r20;                          \
-        mfspr   r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
-        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
-        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
+        DO_KVM  vec;                                    \
+        SET_SCRATCH0(r13);      /* save r13 */          \
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_HV)
 
-
-#define MASKABLE_EXCEPTION_PSERIES(n, label)                            \
-        . = n;                                                          \
-        .globl label##_pSeries;                                         \
-label##_pSeries:                                                        \
+#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h)                     \
         HMT_MEDIUM;                                                     \
-        DO_KVM  n;                                                      \
-        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
-        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
+        DO_KVM  vec;                                                    \
+        SET_SCRATCH0(r13);    /* save r13 */                            \
+        GET_PACA(r13);                                                  \
         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
         std     r10,PACA_EXGEN+EX_R10(r13);                             \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         mfcr    r9;                                                     \
         cmpwi   r10,0;                                                  \
-        beq     masked_interrupt;                                       \
-        mfspr   r10,SPRN_SPRG_SCRATCH0;                                 \
+        beq     masked_##h##interrupt;                                  \
+        GET_SCRATCH0(r10);                                              \
         std     r10,PACA_EXGEN+EX_R13(r13);                             \
         std     r11,PACA_EXGEN+EX_R11(r13);                             \
         std     r12,PACA_EXGEN+EX_R12(r13);                             \
         ld      r12,PACAKBASE(r13);     /* get high part of &label */   \
         ld      r10,PACAKMSR(r13);      /* get MSR value for kernel */  \
-        mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
+        mfspr   r11,SPRN_##h##SRR0;     /* save SRR0 */                 \
         LOAD_HANDLER(r12,label##_common)                                \
-        mtspr   SPRN_SRR0,r12;                                          \
-        mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
-        mtspr   SPRN_SRR1,r10;                                          \
-        rfid;                                                           \
+        mtspr   SPRN_##h##SRR0,r12;                                     \
+        mfspr   r12,SPRN_##h##SRR1;     /* and SRR1 */                  \
+        mtspr   SPRN_##h##SRR1,r10;                                     \
+        h##rfid;                                                        \
         b       .       /* prevent speculative execution */
+#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h)                      \
+        __MASKABLE_EXCEPTION_PSERIES(vec, label, h)
+
+#define MASKABLE_EXCEPTION_PSERIES(loc, vec, label)                     \
+        . = loc;                                                        \
+        .globl label##_pSeries;                                         \
+label##_pSeries:                                                        \
+        _MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_STD)
+
+#define MASKABLE_EXCEPTION_HV(loc, vec, label)                          \
+        . = loc;                                                        \
+        .globl label##_hv;                                              \
+label##_hv:                                                             \
+        _MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_HV)
 
 #ifdef CONFIG_PPC_ISERIES
 #define DISABLE_INTS                            \
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
index 96a7d067fbb2..9a67a38bf7b9 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -37,18 +37,21 @@ label##2:						\
         .align 2;                                       \
 label##3:
 
-#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
-label##4:                                               \
-        .popsection;                                    \
-        .pushsection sect,"a";                          \
-        .align 3;                                       \
-label##5:                                               \
-        FTR_ENTRY_LONG msk;                             \
-        FTR_ENTRY_LONG val;                             \
-        FTR_ENTRY_OFFSET label##1b-label##5b;           \
-        FTR_ENTRY_OFFSET label##2b-label##5b;           \
-        FTR_ENTRY_OFFSET label##3b-label##5b;           \
-        FTR_ENTRY_OFFSET label##4b-label##5b;           \
+#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)           \
+label##4:                                                       \
+        .popsection;                                            \
+        .pushsection sect,"a";                                  \
+        .align 3;                                               \
+label##5:                                                       \
+        FTR_ENTRY_LONG msk;                                     \
+        FTR_ENTRY_LONG val;                                     \
+        FTR_ENTRY_OFFSET label##1b-label##5b;                   \
+        FTR_ENTRY_OFFSET label##2b-label##5b;                   \
+        FTR_ENTRY_OFFSET label##3b-label##5b;                   \
+        FTR_ENTRY_OFFSET label##4b-label##5b;                   \
+        .ifgt (label##4b- label##3b)-(label##2b- label##1b);    \
+        .error "Feature section else case larger than body";    \
+        .endif;                                                 \
         .popsection;
 
 
@@ -143,6 +146,19 @@ label##5:					       	\
 
 #ifndef __ASSEMBLY__
 
+#define ASM_FTR_IF(section_if, section_else, msk, val)  \
+        stringify_in_c(BEGIN_FTR_SECTION)                       \
+        section_if "; "                                         \
+        stringify_in_c(FTR_SECTION_ELSE)                        \
+        section_else "; "                                       \
+        stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
+
+#define ASM_FTR_IFSET(section_if, section_else, msk)    \
+        ASM_FTR_IF(section_if, section_else, (msk), (msk))
+
+#define ASM_FTR_IFCLR(section_if, section_else, msk)    \
+        ASM_FTR_IF(section_if, section_else, (msk), 0)
+
 #define ASM_MMU_FTR_IF(section_if, section_else, msk, val)      \
         stringify_in_c(BEGIN_MMU_FTR_SECTION)                   \
         section_if "; "                                         \
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 20778a405d7a..3a6c586c4e40 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -46,6 +46,8 @@
 #define FW_FEATURE_PS3_LV1      ASM_CONST(0x0000000000800000)
 #define FW_FEATURE_BEAT         ASM_CONST(0x0000000001000000)
 #define FW_FEATURE_CMO          ASM_CONST(0x0000000002000000)
+#define FW_FEATURE_VPHN         ASM_CONST(0x0000000004000000)
+#define FW_FEATURE_XCMO         ASM_CONST(0x0000000008000000)
 
 #ifndef __ASSEMBLY__
 
@@ -59,7 +61,7 @@ enum {
                 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
                 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
                 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
-                FW_FEATURE_CMO,
+                FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
         FW_FEATURE_PSERIES_ALWAYS = 0,
         FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
         FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 000000000000..2af2bdc37b2e
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Cache SRAM handling for QorIQ platform
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+
+#include <asm/rheap.h>
+#include <linux/spinlock.h>
+
+/*
+ * Cache-SRAM
+ */
+
+struct mpc85xx_cache_sram {
+        phys_addr_t base_phys;
+        void *base_virt;
+        unsigned int size;
+        rh_info_t *rh;
+        spinlock_t lock;
+};
+
+extern void mpc85xx_cache_sram_free(void *ptr);
+extern void *mpc85xx_cache_sram_alloc(unsigned int size,
+                                  phys_addr_t *phys, unsigned int align);
+
+#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/fsl_guts.h
index 0f165e59c326..bebd12463ec9 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -1,5 +1,5 @@
 /**
- * MPC86xx Internal Memory Map
+ * Freecale 85xx and 86xx Global Utilties register set
  *
  * Authors: Jeff Brown
  *          Timur Tabi <timur@freescale.com>
@@ -10,73 +10,112 @@
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
- *
- * This header file defines structures for various 86xx SOC devices that are
- * used by multiple source files.
  */
 
-#ifndef __ASM_POWERPC_IMMAP_86XX_H__
-#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifndef __ASM_POWERPC_FSL_GUTS_H__
+#define __ASM_POWERPC_FSL_GUTS_H__
 #ifdef __KERNEL__
 
-/* Global Utility Registers */
-struct ccsr_guts {
+/*
+ * These #ifdefs are safe because it's not possible to build a kernel that
+ * runs on e500 and e600 cores.
+ */
+
+#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
+#error Only 85xx and 86xx SOCs are supported
+#endif
+
+/**
+ * Global Utility Registers.
+ *
+ * Not all registers defined in this structure are available on all chips, so
+ * you are expected to know whether a given register actually exists on your
+ * chip before you access it.
+ *
+ * Also, some registers are similar on different chips but have slightly
+ * different names.  In these cases, one name is chosen to avoid extraneous
+ * #ifdefs.
+ */
+#ifdef CONFIG_PPC_85xx
+struct ccsr_guts_85xx {
+#else
+struct ccsr_guts_86xx {
+#endif
         __be32  porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
         __be32  porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
         __be32  porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
         __be32  pordevsr;       /* 0x.000c - POR I/O Device Status Register */
         __be32  pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
-        u8      res1[0x20 - 0x14];
+        __be32  pordevsr2;      /* 0x.0014 - POR device status register 2 */
+        u8      res018[0x20 - 0x18];
         __be32  porcir;         /* 0x.0020 - POR Configuration Information Register */
-        u8      res2[0x30 - 0x24];
+        u8      res024[0x30 - 0x24];
         __be32  gpiocr;         /* 0x.0030 - GPIO Control Register */
-        u8      res3[0x40 - 0x34];
+        u8      res034[0x40 - 0x34];
         __be32  gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
-        u8      res4[0x50 - 0x44];
+        u8      res044[0x50 - 0x44];
         __be32  gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
-        u8      res5[0x60 - 0x54];
+        u8      res054[0x60 - 0x54];
         __be32  pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
-        u8      res6[0x70 - 0x64];
+        __be32  pmuxcr2;        /* 0x.0064 - Alternate function signal multiplex control 2 */
+        __be32  dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
+        u8      res06c[0x70 - 0x6c];
         __be32  devdisr;        /* 0x.0070 - Device Disable Control */
         __be32  devdisr2;       /* 0x.0074 - Device Disable Control 2 */
-        u8      res7[0x80 - 0x78];
+        u8      res078[0x7c - 0x78];
+        __be32  pmjcr;          /* 0x.007c - 4 Power Management Jog Control Register */
         __be32  powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
-        u8      res8[0x90 - 0x84];
+        __be32  pmrccr;         /* 0x.0084 - Power Management Reset Counter Configuration Register */
+        __be32  pmpdccr;        /* 0x.0088 - Power Management Power Down Counter Configuration Register */
+        __be32  pmcdr;          /* 0x.008c - 4Power management clock disable register */
         __be32  mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
         __be32  rstrscr;        /* 0x.0094 - Reset Request Status and Control Register */
-        u8      res9[0xA0 - 0x98];
+        __be32  ectrstcr;       /* 0x.0098 - Exception reset control register */
+        __be32  autorstsr;      /* 0x.009c - Automatic reset status register */
         __be32  pvr;            /* 0x.00a0 - Processor Version Register */
         __be32  svr;            /* 0x.00a4 - System Version Register */
-        u8      res10[0xB0 - 0xA8];
+        u8      res0a8[0xb0 - 0xa8];
         __be32  rstcr;          /* 0x.00b0 - Reset Control Register */
-        u8      res11[0xC0 - 0xB4];
+        u8      res0b4[0xc0 - 0xb4];
+#ifdef CONFIG_PPC_85xx
+        __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register */
+#else
         __be32  elbcvselcr;     /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
-        u8      res12[0x800 - 0xC4];
+#endif
+        u8      res0c4[0x224 - 0xc4];
+        __be32  iodelay1;       /* 0x.0224 - IO delay control register 1 */
+        __be32  iodelay2;       /* 0x.0228 - IO delay control register 2 */
+        u8      res22c[0x800 - 0x22c];
         __be32  clkdvdr;        /* 0x.0800 - Clock Divide Register */
-        u8      res13[0x900 - 0x804];
+        u8      res804[0x900 - 0x804];
         __be32  ircr;           /* 0x.0900 - Infrared Control Register */
-        u8      res14[0x908 - 0x904];
+        u8      res904[0x908 - 0x904];
         __be32  dmacr;          /* 0x.0908 - DMA Control Register */
-        u8      res15[0x914 - 0x90C];
+        u8      res90c[0x914 - 0x90c];
         __be32  elbccr;         /* 0x.0914 - eLBC Control Register */
-        u8      res16[0xB20 - 0x918];
+        u8      res918[0xb20 - 0x918];
         __be32  ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
         __be32  ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
         __be32  ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
-        u8      res17[0xE00 - 0xB2C];
+        u8      resb2c[0xe00 - 0xb2c];
         __be32  clkocr;         /* 0x.0e00 - Clock Out Select Register */
-        u8      res18[0xE10 - 0xE04];
+        u8      rese04[0xe10 - 0xe04];
         __be32  ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
-        u8      res19[0xE20 - 0xE14];
+        u8      rese14[0xe20 - 0xe14];
         __be32  lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
-        u8      res20[0xF04 - 0xE24];
+        __be32  cpfor;          /* 0x.0e24 - L2 charge pump fuse override register */
+        u8      rese28[0xf04 - 0xe28];
         __be32  srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
         __be32  srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
-        u8      res21[0xF40 - 0xF0C];
-        __be32  srds2cr0;       /* 0x.0f40 - SerDes1 Control Register 0 */
-        __be32  srds2cr1;       /* 0x.0f44 - SerDes1 Control Register 0 */
+        u8      resf0c[0xf2c - 0xf0c];
+        __be32  itcr;           /* 0x.0f2c - Internal transaction control register */
+        u8      resf30[0xf40 - 0xf30];
+        __be32  srds2cr0;       /* 0x.0f40 - SerDes2 Control Register 0 */
+        __be32  srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
 } __attribute__ ((packed));
 
+#ifdef CONFIG_PPC_86xx
+
 #define CCSR_GUTS_DMACR_DEV_SSI 0       /* DMA controller/channel set to SSI */
 #define CCSR_GUTS_DMACR_DEV_IR  1       /* DMA controller/channel set to IR */
 
@@ -93,7 +132,7 @@ struct ccsr_guts {
  * ch: The channel on the DMA controller (0, 1, 2, or 3)
  * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
  */
-static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
+static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
         unsigned int co, unsigned int ch, unsigned int device)
 {
         unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
@@ -129,7 +168,7 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
  * ch: The channel on the DMA controller (0, 1, 2, or 3)
  * value: the new value for the bit (0 or 1)
  */
-static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
+static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts,
         unsigned int co, unsigned int ch, unsigned int value)
 {
         if ((ch == 0) || (ch == 3)) {
@@ -152,5 +191,7 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK   0x000000FF
 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
 
-#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
-#endif /* __KERNEL__ */
+#endif
+
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a21041f9b..8a0b5ece8f76 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
 /* Freescale Local Bus Controller
  *
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010 Freescale Semiconductor
  *
  * Authors: Nick Spence <nick.spence@freescale.com>,
  *          Scott Wood <scottwood@freescale.com>
+ *          Jack Lan <jack.lan@freescale.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +27,8 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/io.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
 
 struct fsl_lbc_bank {
         __be32 br;             /**< Base Register  */
@@ -125,13 +128,23 @@ struct fsl_lbc_regs {
 #define LTESR_ATMW 0x00800000
 #define LTESR_ATMR 0x00400000
 #define LTESR_CS   0x00080000
+#define LTESR_UPM  0x00000002
 #define LTESR_CC   0x00000001
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+                         | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+                         | LTESR_CC)
+#define LTESR_CLEAR     0xFFFFFFFF
+#define LTECCR_CLEAR    0xFFFFFFFF
+#define LTESR_STATUS    LTESR_MASK
+#define LTEIR_ENABLE    LTESR_MASK
+#define LTEDR_ENABLE    0x00000000
         __be32 ltedr;           /**< Transfer Error Disable Register */
         __be32 lteir;           /**< Transfer Error Interrupt Register */
         __be32 lteatr;          /**< Transfer Error Attributes Register */
         __be32 ltear;           /**< Transfer Error Address Register */
-        u8 res6[0xC];
+        __be32 lteccr;          /**< Transfer Error ECC Register */
+        u8 res6[0x8];
         __be32 lbcr;            /**< Configuration Register */
 #define LBCR_LDIS  0x80000000
 #define LBCR_LDIS_SHIFT    31
@@ -144,6 +157,8 @@ struct fsl_lbc_regs {
 #define LBCR_EPAR_SHIFT    16
 #define LBCR_BMT   0x0000FF00
 #define LBCR_BMT_SHIFT      8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT    0
 #define LBCR_INIT  0x00040000
         __be32 lcrr;            /**< Clock Ratio Register */
 #define LCRR_DBYP    0x80000000
@@ -235,6 +250,7 @@ struct fsl_upm {
         int width;
 };
 
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
 extern int fsl_lbc_find(phys_addr_t addr_base);
 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
 
@@ -265,7 +281,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
                 cpu_relax();
 }
 
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+        /* device info */
+        struct device                   *dev;
+        struct fsl_lbc_regs __iomem     *regs;
+        int                             irq;
+        wait_queue_head_t               irq_wait;
+        spinlock_t                      lock;
+        void                            *nand;
+
+        /* status read from LTESR by irq handler */
+        unsigned int                    irq_status;
+};
+
 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
                                u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
 
 #endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/fsldma.h b/arch/powerpc/include/asm/fsldma.h
deleted file mode 100644
index debc5ed96d6e..000000000000
--- a/arch/powerpc/include/asm/fsldma.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Freescale MPC83XX / MPC85XX DMA Controller
- *
- * Copyright (c) 2009 Ira W. Snyder <iws@ovro.caltech.edu>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__
-#define __ARCH_POWERPC_ASM_FSLDMA_H__
-
-#include <linux/slab.h>
-#include <linux/dmaengine.h>
-
-/*
- * Definitions for the Freescale DMA controller's DMA_SLAVE implemention
- *
- * The Freescale DMA_SLAVE implementation was designed to handle many-to-many
- * transfers. An example usage would be an accelerated copy between two
- * scatterlists. Another example use would be an accelerated copy from
- * multiple non-contiguous device buffers into a single scatterlist.
- *
- * A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This
- * structure contains a list of hardware addresses that should be copied
- * to/from the scatterlist passed into device_prep_slave_sg(). The structure
- * also has some fields to enable hardware-specific features.
- */
-
-/**
- * struct fsl_dma_hw_addr
- * @entry: linked list entry
- * @address: the hardware address
- * @length: length to transfer
- *
- * Holds a single physical hardware address / length pair for use
- * with the DMAEngine DMA_SLAVE API.
- */
-struct fsl_dma_hw_addr {
-        struct list_head entry;
-
-        dma_addr_t address;
-        size_t length;
-};
-
-/**
- * struct fsl_dma_slave
- * @addresses: a linked list of struct fsl_dma_hw_addr structures
- * @request_count: value for DMA request count
- * @src_loop_size: setup and enable constant source-address DMA transfers
- * @dst_loop_size: setup and enable constant destination address DMA transfers
- * @external_start: enable externally started DMA transfers
- * @external_pause: enable externally paused DMA transfers
- *
- * Holds a list of address / length pairs for use with the DMAEngine
- * DMA_SLAVE API implementation for the Freescale DMA controller.
- */
-struct fsl_dma_slave {
-
-        /* List of hardware address/length pairs */
-        struct list_head addresses;
-
-        /* Support for extra controller features */
-        unsigned int request_count;
-        unsigned int src_loop_size;
-        unsigned int dst_loop_size;
-        bool external_start;
-        bool external_pause;
-};
-
-/**
- * fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave
- * @slave: the &struct fsl_dma_slave to add to
- * @address: the hardware address to add
- * @length: the length of bytes to transfer from @address
- *
- * Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on
- * success, -ERRNO otherwise.
- */
-static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave,
-                                       dma_addr_t address, size_t length)
-{
-        struct fsl_dma_hw_addr *addr;
-
-        addr = kzalloc(sizeof(*addr), GFP_ATOMIC);
-        if (!addr)
-                return -ENOMEM;
-
-        INIT_LIST_HEAD(&addr->entry);
-        addr->address = address;
-        addr->length = length;
-
-        list_add_tail(&addr->entry, &slave->addresses);
-        return 0;
-}
-
-/**
- * fsl_dma_slave_free - free a struct fsl_dma_slave
- * @slave: the struct fsl_dma_slave to free
- *
- * Free a struct fsl_dma_slave and all associated address/length pairs
- */
-static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave)
-{
-        struct fsl_dma_hw_addr *addr, *tmp;
-
-        if (slave) {
-                list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) {
-                        list_del(&addr->entry);
-                        kfree(addr);
-                }
-
-                kfree(slave);
-        }
-}
-
-/**
- * fsl_dma_slave_alloc - allocate a struct fsl_dma_slave
- * @gfp: the flags to pass to kmalloc when allocating this structure
- *
- * Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new
- * struct fsl_dma_slave on success, or NULL on failure.
- */
-static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp)
-{
-        struct fsl_dma_slave *slave;
-
-        slave = kzalloc(sizeof(*slave), gfp);
-        if (!slave)
-                return NULL;
-
-        INIT_LIST_HEAD(&slave->addresses);
-        return slave;
-}
-
-#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */
diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h
index dde1296b8b41..169d039ed402 100644
--- a/arch/powerpc/include/asm/ftrace.h
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -60,4 +60,18 @@ struct dyn_arch_ftrace {
 
 #endif
 
+#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64) && !defined(__ASSEMBLY__)
+#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
+static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
+{
+        /*
+         * Compare the symbol name with the system call name. Skip the .sys or .SyS
+         * prefix from the symbol name and the sys prefix from the system call name and
+         * just match the rest. This is only needed on ppc64 since symbol names on
+         * 32bit do not start with a period so the generic function will work.
+         */
+        return !strcmp(sym + 4, name + 3);
+}
+#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 && !__ASSEMBLY__ */
+
 #endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index 7c589ef81fb0..c94e4a3fe2ef 100644
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -30,7 +30,7 @@
         : "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
         : "cr0", "memory")
 
-static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
 {
         int op = (encoded_op >> 28) & 7;
         int cmp = (encoded_op >> 24) & 15;
@@ -40,7 +40,7 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
         if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
                 oparg = 1 << oparg;
 
-        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
         pagefault_disable();
@@ -82,35 +82,38 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 }
 
 static inline int
-futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
 {
-        int prev;
+        int ret = 0;
+        u32 prev;
 
-        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
         __asm__ __volatile__ (
         PPC_RELEASE_BARRIER
-"1:     lwarx   %0,0,%2         # futex_atomic_cmpxchg_inatomic\n\
-        cmpw    0,%0,%3\n\
+"1:     lwarx   %1,0,%3         # futex_atomic_cmpxchg_inatomic\n\
+        cmpw    0,%1,%4\n\
         bne-    3f\n"
-        PPC405_ERR77(0,%2)
-"2:     stwcx.  %4,0,%2\n\
+        PPC405_ERR77(0,%3)
+"2:     stwcx.  %5,0,%3\n\
         bne-    1b\n"
         PPC_ACQUIRE_BARRIER
 "3:     .section .fixup,\"ax\"\n\
-4:      li      %0,%5\n\
+4:      li      %0,%6\n\
         b       3b\n\
         .previous\n\
         .section __ex_table,\"a\"\n\
         .align 3\n\
         " PPC_LONG "1b,4b,2b,4b\n\
         .previous" \
-        : "=&r" (prev), "+m" (*uaddr)
+        : "+r" (ret), "=&r" (prev), "+m" (*uaddr)
         : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
         : "cc", "memory");
 
-        return prev;
+        *uval = prev;
+        return ret;
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h
index d10d64a4be38..dbc264010d0b 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -60,9 +60,8 @@ extern pte_t *pkmap_page_table;
 
 extern void *kmap_high(struct page *page);
 extern void kunmap_high(struct page *page);
-extern void *kmap_atomic_prot(struct page *page, enum km_type type,
-                              pgprot_t prot);
-extern void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type);
+extern void *kmap_atomic_prot(struct page *page, pgprot_t prot);
+extern void __kunmap_atomic(void *kvaddr);
 
 static inline void *kmap(struct page *page)
 {
@@ -80,9 +79,9 @@ static inline void kunmap(struct page *page)
         kunmap_high(page);
 }
 
-static inline void *kmap_atomic(struct page *page, enum km_type type)
+static inline void *__kmap_atomic(struct page *page)
 {
-        return kmap_atomic_prot(page, type, kmap_prot);
+        return kmap_atomic_prot(page, kmap_prot);
 }
 
 static inline struct page *kmap_atomic_to_page(void *ptr)
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index de03ca58db5d..fd8201dddd4b 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -102,6 +102,7 @@
 #define H_ANDCOND               (1UL<<(63-33))
 #define H_ICACHE_INVALIDATE     (1UL<<(63-40))  /* icbi, etc.  (ignored for IO pages) */
 #define H_ICACHE_SYNCHRONIZE    (1UL<<(63-41))  /* dcbst, icbi, etc (ignored for IO pages */
+#define H_COALESCE_CAND (1UL<<(63-42))  /* page is a good candidate for coalescing */
 #define H_ZERO_PAGE             (1UL<<(63-48))  /* zero the page before mapping (ignored for IO pages) */
 #define H_COPY_PAGE             (1UL<<(63-49))
 #define H_N                     (1UL<<(63-61))
@@ -122,7 +123,7 @@
 #define H_DABRX_KERNEL          (1UL<<(63-62))
 #define H_DABRX_USER            (1UL<<(63-63))
 
-/* Each control block has to be on a 4K bondary */
+/* Each control block has to be on a 4K boundary */
 #define H_CB_ALIGNMENT          4096
 
 /* pSeries hypervisor opcodes */
@@ -232,7 +233,10 @@
 #define H_GET_EM_PARMS          0x2B8
 #define H_SET_MPP               0x2D0
 #define H_GET_MPP               0x2D4
-#define MAX_HCALL_OPCODE        H_GET_MPP
+#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
+#define H_BEST_ENERGY           0x2F4
+#define H_GET_MPP_X             0x314
+#define MAX_HCALL_OPCODE        H_GET_MPP_X
 
 #ifndef __ASSEMBLY__
 
@@ -310,6 +314,16 @@ struct hvcall_mpp_data {
 
 int h_get_mpp(struct hvcall_mpp_data *);
 
+struct hvcall_mpp_x_data {
+        unsigned long coalesced_bytes;
+        unsigned long pool_coalesced_bytes;
+        unsigned long pool_purr_cycles;
+        unsigned long pool_spurr_cycles;
+        unsigned long reserved[3];
+};
+
+int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
+
 #ifdef CONFIG_PPC_PSERIES
 extern int CMO_PrPSP;
 extern int CMO_SecPSP;
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index bd100fcf40d0..bb712c9488b3 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -16,42 +16,57 @@ extern void timer_interrupt(struct pt_regs *);
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 
-static inline unsigned long local_get_flags(void)
+static inline unsigned long arch_local_save_flags(void)
 {
         unsigned long flags;
 
-        __asm__ __volatile__("lbz %0,%1(13)"
-        : "=r" (flags)
-        : "i" (offsetof(struct paca_struct, soft_enabled)));
+        asm volatile(
+                "lbz %0,%1(13)"
+                : "=r" (flags)
+                : "i" (offsetof(struct paca_struct, soft_enabled)));
 
         return flags;
 }
 
-static inline unsigned long raw_local_irq_disable(void)
+static inline unsigned long arch_local_irq_disable(void)
 {
         unsigned long flags, zero;
 
-        __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
-        : "=r" (flags), "=&r" (zero)
-        : "i" (offsetof(struct paca_struct, soft_enabled))
-        : "memory");
+        asm volatile(
+                "li %1,0; lbz %0,%2(13); stb %1,%2(13)"
+                : "=r" (flags), "=&r" (zero)
+                : "i" (offsetof(struct paca_struct, soft_enabled))
+                : "memory");
 
         return flags;
 }
 
-extern void raw_local_irq_restore(unsigned long);
+extern void arch_local_irq_restore(unsigned long);
 extern void iseries_handle_interrupts(void);
 
-#define raw_local_irq_enable()          raw_local_irq_restore(1)
-#define raw_local_save_flags(flags)     ((flags) = local_get_flags())
-#define raw_local_irq_save(flags)       ((flags) = raw_local_irq_disable())
+static inline void arch_local_irq_enable(void)
+{
+        arch_local_irq_restore(1);
+}
+
+static inline unsigned long arch_local_irq_save(void)
+{
+        return arch_local_irq_disable();
+}
+
+static inline bool arch_irqs_disabled_flags(unsigned long flags)
+{
+        return flags == 0;
+}
 
-#define raw_irqs_disabled()             (local_get_flags() == 0)
-#define raw_irqs_disabled_flags(flags)  ((flags) == 0)
+static inline bool arch_irqs_disabled(void)
+{
+        return arch_irqs_disabled_flags(arch_local_save_flags());
+}
 
 #ifdef CONFIG_PPC_BOOK3E
-#define __hard_irq_enable()     __asm__ __volatile__("wrteei 1": : :"memory");
-#define __hard_irq_disable()    __asm__ __volatile__("wrteei 0": : :"memory");
+#define __hard_irq_enable()     asm volatile("wrteei 1" : : : "memory");
+#define __hard_irq_disable()    asm volatile("wrteei 0" : : : "memory");
 #else
 #define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
 #define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
@@ -64,66 +79,70 @@ extern void iseries_handle_interrupts(void);
                 get_paca()->hard_enabled = 0;   \
         } while(0)
 
-#else
+#else /* CONFIG_PPC64 */
 
-#if defined(CONFIG_BOOKE)
 #define SET_MSR_EE(x)   mtmsr(x)
-#define raw_local_irq_restore(flags)    __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
+
+static inline unsigned long arch_local_save_flags(void)
+{
+        return mfmsr();
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+#if defined(CONFIG_BOOKE)
+        asm volatile("wrtee %0" : : "r" (flags) : "memory");
 #else
-#define SET_MSR_EE(x)   mtmsr(x)
-#define raw_local_irq_restore(flags)    mtmsr(flags)
+        mtmsr(flags);
 #endif
+}
 
-static inline void raw_local_irq_disable(void)
+static inline unsigned long arch_local_irq_save(void)
 {
+        unsigned long flags = arch_local_save_flags();
 #ifdef CONFIG_BOOKE
-        __asm__ __volatile__("wrteei 0": : :"memory");
+        asm volatile("wrteei 0" : : : "memory");
 #else
-        unsigned long msr;
-
-        msr = mfmsr();
-        SET_MSR_EE(msr & ~MSR_EE);
+        SET_MSR_EE(flags & ~MSR_EE);
 #endif
+        return flags;
 }
 
-static inline void raw_local_irq_enable(void)
+static inline void arch_local_irq_disable(void)
 {
 #ifdef CONFIG_BOOKE
-        __asm__ __volatile__("wrteei 1": : :"memory");
+        asm volatile("wrteei 0" : : : "memory");
 #else
-        unsigned long msr;
-
-        msr = mfmsr();
-        SET_MSR_EE(msr | MSR_EE);
+        arch_local_irq_save();
 #endif
 }
 
-static inline void raw_local_irq_save_ptr(unsigned long *flags)
+static inline void arch_local_irq_enable(void)
 {
-        unsigned long msr;
-        msr = mfmsr();
-        *flags = msr;
 #ifdef CONFIG_BOOKE
-        __asm__ __volatile__("wrteei 0": : :"memory");
+        asm volatile("wrteei 1" : : : "memory");
 #else
-        SET_MSR_EE(msr & ~MSR_EE);
+        unsigned long msr = mfmsr();
+        SET_MSR_EE(msr | MSR_EE);
 #endif
 }
 
-#define raw_local_save_flags(flags)     ((flags) = mfmsr())
-#define raw_local_irq_save(flags)       raw_local_irq_save_ptr(&flags)
-#define raw_irqs_disabled()             ((mfmsr() & MSR_EE) == 0)
-#define raw_irqs_disabled_flags(flags)  (((flags) & MSR_EE) == 0)
-
-#define hard_irq_disable()              raw_local_irq_disable()
-
-static inline int irqs_disabled_flags(unsigned long flags)
+static inline bool arch_irqs_disabled_flags(unsigned long flags)
 {
         return (flags & MSR_EE) == 0;
 }
 
+static inline bool arch_irqs_disabled(void)
+{
+        return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+
+#define hard_irq_disable()              arch_local_irq_disable()
+
 #endif /* CONFIG_PPC64 */
 
+#define ARCH_IRQ_INIT_FLAGS     IRQ_NOREQUEST
+
 /*
  * interrupt-retrigger: should we handle this via lost interrupts and IPIs
  * or should we not care like we do now ? --BenH.
diff --git a/arch/powerpc/include/asm/hydra.h b/arch/powerpc/include/asm/hydra.h
index 1ad4eed07fbe..5b0c98bd46ab 100644
--- a/arch/powerpc/include/asm/hydra.h
+++ b/arch/powerpc/include/asm/hydra.h
@@ -10,7 +10,7 @@
  *
  *      © Copyright 1995 Apple Computer, Inc. All rights reserved.
  *
- *  It's available online from http://chrp.apple.com/MacTech.pdf.
+ *  It's available online from http://www.cpu.lu/~mlan/ftp/MacTech.pdf
  *  You can obtain paper copies of this book from computer bookstores or by
  *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
  *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 4e10f508570a..0edb6842b13d 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -467,13 +467,22 @@ struct qe_immap {
 extern struct qe_immap __iomem *qe_immr;
 extern phys_addr_t get_qe_base(void);
 
-static inline unsigned long immrbar_virt_to_phys(void *address)
+/*
+ * Returns the offset within the QE address space of the given pointer.
+ *
+ * Note that the QE does not support 36-bit physical addresses, so if
+ * get_qe_base() returns a number above 4GB, the caller will probably fail.
+ */
+static inline phys_addr_t immrbar_virt_to_phys(void *address)
 {
-        if ( ((u32)address >= (u32)qe_immr) &&
-                        ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
-                return (unsigned long)(address - (u32)qe_immr +
-                                (u32)get_qe_base());
-        return (unsigned long)virt_to_phys(address);
+        void *q = (void *)qe_immr;
+
+        /* Is it a MURAM address? */
+        if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
+                return get_qe_base() + (address - q);
+
+        /* It's an address returned by kmalloc */
+        return virt_to_phys(address);
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/io-workarounds.h b/arch/powerpc/include/asm/io-workarounds.h
new file mode 100644
index 000000000000..fbae49286926
--- /dev/null
+++ b/arch/powerpc/include/asm/io-workarounds.h
@@ -0,0 +1,48 @@
+/*
+ * Support PCI IO workaround
+ *
+ * (C) Copyright 2007-2008 TOSHIBA CORPORATION
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _IO_WORKAROUNDS_H
+#define _IO_WORKAROUNDS_H
+
+#include <linux/io.h>
+#include <asm/pci-bridge.h>
+
+/* Bus info */
+struct iowa_bus {
+        struct pci_controller *phb;
+        struct ppc_pci_io *ops;
+        void   *private;
+};
+
+void __devinit iowa_register_bus(struct pci_controller *, struct ppc_pci_io *,
+                                 int (*)(struct iowa_bus *, void *), void *);
+struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR);
+struct iowa_bus *iowa_pio_find_bus(unsigned long);
+
+extern struct ppc_pci_io spiderpci_ops;
+extern int spiderpci_iowa_init(struct iowa_bus *, void *);
+
+#define SPIDER_PCI_REG_BASE             0xd000
+#define SPIDER_PCI_REG_SIZE             0x1000
+#define SPIDER_PCI_VCI_CNTL_STAT        0x0110
+#define SPIDER_PCI_DUMMY_READ           0x0810
+#define SPIDER_PCI_DUMMY_READ_BASE      0x0814
+
+#endif /* _IO_WORKAROUNDS_H */
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 001f2f11c19b..45698d55cd6a 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -2,6 +2,8 @@
 #define _ASM_POWERPC_IO_H
 #ifdef __KERNEL__
 
+#define ARCH_HAS_IOREMAP_WC
+
 /*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -481,10 +483,16 @@ __do_out_asm(_rec_outl, "stwbrx")
                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 #endif /* !CONFIG_EEH */
 
-#ifdef CONFIG_PPC_INDIRECT_IO
-#define DEF_PCI_HOOK(x)         x
+#ifdef CONFIG_PPC_INDIRECT_PIO
+#define DEF_PCI_HOOK_pio(x)     x
+#else
+#define DEF_PCI_HOOK_pio(x)     NULL
+#endif
+
+#ifdef CONFIG_PPC_INDIRECT_MMIO
+#define DEF_PCI_HOOK_mem(x)     x
 #else
-#define DEF_PCI_HOOK(x)         NULL
+#define DEF_PCI_HOOK_mem(x)     NULL
 #endif
 
 /* Structure containing all the hooks */
@@ -504,7 +512,7 @@ extern struct ppc_pci_io {
 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 static inline ret name at                                       \
 {                                                               \
-        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+        if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
                 return ppc_pci_io.name al;                      \
         return __do_##name al;                                  \
 }
@@ -512,7 +520,7 @@ static inline ret name at					\
 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 static inline void name at                                      \
 {                                                               \
-        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+        if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)              \
                 ppc_pci_io.name al;                             \
         else                                                    \
                 __do_##name al;                                 \
@@ -616,12 +624,13 @@ static inline void iosync(void)
  * * ioremap is the standard one and provides non-cacheable guarded mappings
  *   and can be hooked by the platform via ppc_md
  *
- * * ioremap_flags allows to specify the page flags as an argument and can
- *   also be hooked by the platform via ppc_md. ioremap_prot is the exact
- *   same thing as ioremap_flags.
+ * * ioremap_prot allows to specify the page flags as an argument and can
+ *   also be hooked by the platform via ppc_md.
  *
  * * ioremap_nocache is identical to ioremap
  *
+ * * ioremap_wc enables write combining
+ *
  * * iounmap undoes such a mapping and can be hooked
  *
  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
@@ -629,7 +638,7 @@ static inline void iosync(void)
  *   currently be hooked. Must be page aligned.
  *
  * * __ioremap is the low level implementation used by ioremap and
- *   ioremap_flags and cannot be hooked (but can be used by a hook on one
+ *   ioremap_prot and cannot be hooked (but can be used by a hook on one
  *   of the previous ones)
  *
  * * __ioremap_caller is the same as above but takes an explicit caller
@@ -640,10 +649,10 @@ static inline void iosync(void)
  *
  */
 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
-                                   unsigned long flags);
+extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
+                                  unsigned long flags);
+extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
-#define ioremap_prot(addr, size, prot)  ioremap_flags((addr), (size), (prot))
 
 extern void iounmap(volatile void __iomem *addr);
 
diff --git a/arch/powerpc/include/asm/io_event_irq.h b/arch/powerpc/include/asm/io_event_irq.h
new file mode 100644
index 000000000000..b1a9a1be3c21
--- /dev/null
+++ b/arch/powerpc/include/asm/io_event_irq.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2010, 2011 Mark Nelson and Tseng-Hui (Frank) Lin, IBM Corporation
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_IO_EVENT_IRQ_H
+#define _ASM_POWERPC_IO_EVENT_IRQ_H
+
+#include <linux/types.h>
+#include <linux/notifier.h>
+
+#define PSERIES_IOEI_RPC_MAX_LEN 216
+
+#define PSERIES_IOEI_TYPE_ERR_DETECTED          0x01
+#define PSERIES_IOEI_TYPE_ERR_RECOVERED         0x02
+#define PSERIES_IOEI_TYPE_EVENT                 0x03
+#define PSERIES_IOEI_TYPE_RPC_PASS_THRU         0x04
+
+#define PSERIES_IOEI_SUBTYPE_NOT_APP            0x00
+#define PSERIES_IOEI_SUBTYPE_REBALANCE_REQ      0x01
+#define PSERIES_IOEI_SUBTYPE_NODE_ONLINE        0x03
+#define PSERIES_IOEI_SUBTYPE_NODE_OFFLINE       0x04
+#define PSERIES_IOEI_SUBTYPE_DUMP_SIZE_CHANGE   0x05
+#define PSERIES_IOEI_SUBTYPE_TORRENT_IRV_UPDATE 0x06
+#define PSERIES_IOEI_SUBTYPE_TORRENT_HFI_CFGED  0x07
+
+#define PSERIES_IOEI_SCOPE_NOT_APP              0x00
+#define PSERIES_IOEI_SCOPE_RIO_HUB              0x36
+#define PSERIES_IOEI_SCOPE_RIO_BRIDGE           0x37
+#define PSERIES_IOEI_SCOPE_PHB                  0x38
+#define PSERIES_IOEI_SCOPE_EADS_GLOBAL          0x39
+#define PSERIES_IOEI_SCOPE_EADS_SLOT            0x3A
+#define PSERIES_IOEI_SCOPE_TORRENT_HUB          0x3B
+#define PSERIES_IOEI_SCOPE_SERVICE_PROC         0x51
+
+/* Platform Event Log Format, Version 6, data portition of IO event section */
+struct pseries_io_event {
+        uint8_t event_type;             /* 0x00 IO-Event Type           */
+        uint8_t rpc_data_len;           /* 0x01 RPC data length         */
+        uint8_t scope;                  /* 0x02 Error/Event Scope       */
+        uint8_t event_subtype;          /* 0x03 I/O-Event Sub-Type      */
+        uint32_t drc_index;             /* 0x04 DRC Index               */
+        uint8_t rpc_data[PSERIES_IOEI_RPC_MAX_LEN];
+                                        /* 0x08 RPC Data (0-216 bytes,  */
+                                        /* padded to 4 bytes alignment) */
+};
+
+extern struct atomic_notifier_head pseries_ioei_notifier_list;
+
+#endif /* _ASM_POWERPC_IO_EVENT_IRQ_H */
diff --git a/arch/powerpc/include/asm/ioctls.h b/arch/powerpc/include/asm/ioctls.h
index 851920052e08..e9b78870aaab 100644
--- a/arch/powerpc/include/asm/ioctls.h
+++ b/arch/powerpc/include/asm/ioctls.h
@@ -94,7 +94,9 @@
 #define TIOCSRS485      0x542f
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
+#define TIOCVHANGUP     0x5437
 
 #define TIOCSERCONFIG   0x5453
 #define TIOCSERGWILD    0x5454
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index 67ab5fb7d153..1bff591f7f72 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -88,9 +88,6 @@ struct irq_host_ops {
         /* Dispose of such a mapping */
         void (*unmap)(struct irq_host *h, unsigned int virq);
 
-        /* Update of such a mapping  */
-        void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
-
         /* Translate device-tree interrupt specifier from raw format coming
          * from the firmware to a irq_hw_number_t (interrupt line number) and
          * type (sense) that can be passed to set_irq_type(). In the absence
@@ -128,19 +125,10 @@ struct irq_host {
         struct device_node      *of_node;
 };
 
-/* The main irq map itself is an array of NR_IRQ entries containing the
- * associate host and irq number. An entry with a host of NULL is free.
- * An entry can be allocated if it's free, the allocator always then sets
- * hwirq first to the host's invalid irq number and then fills ops.
- */
-struct irq_map_entry {
-        irq_hw_number_t hwirq;
-        struct irq_host *host;
-};
-
-extern struct irq_map_entry irq_map[NR_IRQS];
-
+struct irq_data;
+extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
 extern irq_hw_number_t virq_to_hw(unsigned int virq);
+extern bool virq_is_host(unsigned int virq, struct irq_host *host);
 
 /**
  * irq_alloc_host - Allocate a new irq_host data structure
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
index 5f68ecfdf516..b0b06d85788d 100644
--- a/arch/powerpc/include/asm/irqflags.h
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -6,30 +6,50 @@
 
 #ifndef __ASSEMBLY__
 /*
- * Get definitions for raw_local_save_flags(x), etc.
+ * Get definitions for arch_local_save_flags(x), etc.
  */
 #include <asm/hw_irq.h>
 
 #else
 #ifdef CONFIG_TRACE_IRQFLAGS
+#ifdef CONFIG_IRQSOFF_TRACER
+/*
+ * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
+ * which is the stack frame here, we need to force a stack frame
+ * in case we came from user space.
+ */
+#define TRACE_WITH_FRAME_BUFFER(func)           \
+        mflr    r0;                             \
+        stdu    r1, -32(r1);                    \
+        std     r0, 16(r1);                     \
+        stdu    r1, -32(r1);                    \
+        bl func;                                \
+        ld      r1, 0(r1);                      \
+        ld      r1, 0(r1);
+#else
+#define TRACE_WITH_FRAME_BUFFER(func)           \
+        bl func;
+#endif
+
 /*
  * Most of the CPU's IRQ-state tracing is done from assembly code; we
  * have to call a C function so call a wrapper that saves all the
  * C-clobbered registers.
  */
-#define TRACE_ENABLE_INTS       bl .trace_hardirqs_on
-#define TRACE_DISABLE_INTS      bl .trace_hardirqs_off
-#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)  \
-        cmpdi   en,0;                           \
-        bne     95f;                            \
-        stb     en,PACASOFTIRQEN(r13);          \
-        bl      .trace_hardirqs_off;            \
-        b       skip;                           \
-95:     bl      .trace_hardirqs_on;             \
+#define TRACE_ENABLE_INTS       TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)
+#define TRACE_DISABLE_INTS      TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
+
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)          \
+        cmpdi   en,0;                                   \
+        bne     95f;                                    \
+        stb     en,PACASOFTIRQEN(r13);                  \
+        TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)    \
+        b       skip;                                   \
+95:     TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)     \
         li      en,1;
 #define TRACE_AND_RESTORE_IRQ(en)               \
         TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f);  \
-        stb     en,PACASOFTIRQEN(r13);          \
+        stb     en,PACASOFTIRQEN(r13);          \
 96:
 #else
 #define TRACE_ENABLE_INTS
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 076327f2eff7..8a33698c61bd 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -76,7 +76,7 @@ extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
 extern cpumask_t cpus_in_sr;
 static inline int kexec_sr_activated(int cpu)
 {
-        return cpu_isset(cpu,cpus_in_sr);
+        return cpumask_test_cpu(cpu, &cpus_in_sr);
 }
 
 struct kimage;
@@ -91,6 +91,7 @@ extern void machine_kexec_simple(struct kimage *image);
 extern void crash_kexec_secondary(struct pt_regs *regs);
 extern int overlaps_crashkernel(unsigned long start, unsigned long size);
 extern void reserve_crashkernel(void);
+extern void machine_kexec_mask_interrupts(void);
 
 #else /* !CONFIG_KEXEC */
 static inline int kexec_sr_activated(int cpu) { return 0; }
diff --git a/arch/powerpc/include/asm/kgdb.h b/arch/powerpc/include/asm/kgdb.h
index edd217006d27..9db24e77b9f4 100644
--- a/arch/powerpc/include/asm/kgdb.h
+++ b/arch/powerpc/include/asm/kgdb.h
@@ -31,6 +31,7 @@ static inline void arch_kgdb_breakpoint(void)
         asm(".long 0x7d821008"); /* twge r2, r2 */
 }
 #define CACHE_FLUSH_IS_SAFE     1
+#define DBG_MAX_REG_NUM     70
 
 /* The number bytes of registers we have to save depends on a few
  * things.  For 64bit we default to not including vector registers and
diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h
index d0e7701fa1f6..be0171afdc0f 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -50,7 +50,7 @@ typedef unsigned int kprobe_opcode_t;
  * Handle cases where:
  *              - User passes a <.symbol> or <module:.symbol>
  *              - User passes a <symbol> or <module:symbol>
- *              - User passes a non-existant symbol, kallsyms_lookup_name
+ *              - User passes a non-existent symbol, kallsyms_lookup_name
  *                returns 0. Don't deref the NULL pointer in that case
  */
 #define kprobe_lookup_name(name, addr)                                  \
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index 6c5547d82bbe..d2ca5ed3877b 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -45,6 +45,114 @@ struct kvm_regs {
         __u64 gpr[32];
 };
 
+#define KVM_SREGS_E_IMPL_NONE   0
+#define KVM_SREGS_E_IMPL_FSL    1
+
+#define KVM_SREGS_E_FSL_PIDn    (1 << 0) /* PID1/PID2 */
+
+/*
+ * Feature bits indicate which sections of the sregs struct are valid,
+ * both in KVM_GET_SREGS and KVM_SET_SREGS.  On KVM_SET_SREGS, registers
+ * corresponding to unset feature bits will not be modified.  This allows
+ * restoring a checkpoint made without that feature, while keeping the
+ * default values of the new registers.
+ *
+ * KVM_SREGS_E_BASE contains:
+ * CSRR0/1 (refers to SRR2/3 on 40x)
+ * ESR
+ * DEAR
+ * MCSR
+ * TSR
+ * TCR
+ * DEC
+ * TB
+ * VRSAVE (USPRG0)
+ */
+#define KVM_SREGS_E_BASE                (1 << 0)
+
+/*
+ * KVM_SREGS_E_ARCH206 contains:
+ *
+ * PIR
+ * MCSRR0/1
+ * DECAR
+ * IVPR
+ */
+#define KVM_SREGS_E_ARCH206             (1 << 1)
+
+/*
+ * Contains EPCR, plus the upper half of 64-bit registers
+ * that are 32-bit on 32-bit implementations.
+ */
+#define KVM_SREGS_E_64                  (1 << 2)
+
+#define KVM_SREGS_E_SPRG8               (1 << 3)
+#define KVM_SREGS_E_MCIVPR              (1 << 4)
+
+/*
+ * IVORs are used -- contains IVOR0-15, plus additional IVORs
+ * in combination with an appropriate feature bit.
+ */
+#define KVM_SREGS_E_IVOR                (1 << 5)
+
+/*
+ * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
+ * Also TLBnPS if MMUCFG[MAVN] = 1.
+ */
+#define KVM_SREGS_E_ARCH206_MMU         (1 << 6)
+
+/* DBSR, DBCR, IAC, DAC, DVC */
+#define KVM_SREGS_E_DEBUG               (1 << 7)
+
+/* Enhanced debug -- DSRR0/1, SPRG9 */
+#define KVM_SREGS_E_ED                  (1 << 8)
+
+/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
+#define KVM_SREGS_E_SPE                 (1 << 9)
+
+/* External Proxy (EXP) -- EPR */
+#define KVM_SREGS_EXP                   (1 << 10)
+
+/* External PID (E.PD) -- EPSC/EPLC */
+#define KVM_SREGS_E_PD                  (1 << 11)
+
+/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
+#define KVM_SREGS_E_PC                  (1 << 12)
+
+/* Page table (E.PT) -- EPTCFG */
+#define KVM_SREGS_E_PT                  (1 << 13)
+
+/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
+#define KVM_SREGS_E_PM                  (1 << 14)
+
+/*
+ * Special updates:
+ *
+ * Some registers may change even while a vcpu is not running.
+ * To avoid losing these changes, by default these registers are
+ * not updated by KVM_SET_SREGS.  To force an update, set the bit
+ * in u.e.update_special corresponding to the register to be updated.
+ *
+ * The update_special field is zero on return from KVM_GET_SREGS.
+ *
+ * When restoring a checkpoint, the caller can set update_special
+ * to 0xffffffff to ensure that everything is restored, even new features
+ * that the caller doesn't know about.
+ */
+#define KVM_SREGS_E_UPDATE_MCSR         (1 << 0)
+#define KVM_SREGS_E_UPDATE_TSR          (1 << 1)
+#define KVM_SREGS_E_UPDATE_DEC          (1 << 2)
+#define KVM_SREGS_E_UPDATE_DBSR         (1 << 3)
+
+/*
+ * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
+ * previous KVM_GET_REGS.
+ *
+ * Unless otherwise indicated, setting any register with KVM_SET_SREGS
+ * directly sets its value.  It does not trigger any special semantics such
+ * as write-one-to-clear.  Calling KVM_SET_SREGS on an unmodified struct
+ * just received from KVM_GET_SREGS is always a no-op.
+ */
 struct kvm_sregs {
         __u32 pvr;
         union {
@@ -62,6 +170,82 @@ struct kvm_sregs {
                                 __u64 dbat[8]; 
                         } ppc32;
                 } s;
+                struct {
+                        union {
+                                struct { /* KVM_SREGS_E_IMPL_FSL */
+                                        __u32 features; /* KVM_SREGS_E_FSL_ */
+                                        __u32 svr;
+                                        __u64 mcar;
+                                        __u32 hid0;
+
+                                        /* KVM_SREGS_E_FSL_PIDn */
+                                        __u32 pid1, pid2;
+                                } fsl;
+                                __u8 pad[256];
+                        } impl;
+
+                        __u32 features; /* KVM_SREGS_E_ */
+                        __u32 impl_id;  /* KVM_SREGS_E_IMPL_ */
+                        __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
+                        __u32 pir;      /* read-only */
+                        __u64 sprg8;
+                        __u64 sprg9;    /* E.ED */
+                        __u64 csrr0;
+                        __u64 dsrr0;    /* E.ED */
+                        __u64 mcsrr0;
+                        __u32 csrr1;
+                        __u32 dsrr1;    /* E.ED */
+                        __u32 mcsrr1;
+                        __u32 esr;
+                        __u64 dear;
+                        __u64 ivpr;
+                        __u64 mcivpr;
+                        __u64 mcsr;     /* KVM_SREGS_E_UPDATE_MCSR */
+
+                        __u32 tsr;      /* KVM_SREGS_E_UPDATE_TSR */
+                        __u32 tcr;
+                        __u32 decar;
+                        __u32 dec;      /* KVM_SREGS_E_UPDATE_DEC */
+
+                        /*
+                         * Userspace can read TB directly, but the
+                         * value reported here is consistent with "dec".
+                         *
+                         * Read-only.
+                         */
+                        __u64 tb;
+
+                        __u32 dbsr;     /* KVM_SREGS_E_UPDATE_DBSR */
+                        __u32 dbcr[3];
+                        __u32 iac[4];
+                        __u32 dac[2];
+                        __u32 dvc[2];
+                        __u8 num_iac;   /* read-only */
+                        __u8 num_dac;   /* read-only */
+                        __u8 num_dvc;   /* read-only */
+                        __u8 pad;
+
+                        __u32 epr;      /* EXP */
+                        __u32 vrsave;   /* a.k.a. USPRG0 */
+                        __u32 epcr;     /* KVM_SREGS_E_64 */
+
+                        __u32 mas0;
+                        __u32 mas1;
+                        __u64 mas2;
+                        __u64 mas7_3;
+                        __u32 mas4;
+                        __u32 mas6;
+
+                        __u32 ivor_low[16]; /* IVOR0-15 */
+                        __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
+
+                        __u32 mmucfg;   /* read-only */
+                        __u32 eptcfg;   /* E.PT, read-only */
+                        __u32 tlbcfg[4];/* read-only */
+                        __u32 tlbps[4]; /* read-only */
+
+                        __u32 eplc, epsc; /* E.PD */
+                } e;
                 __u8 pad[1020];
         } u;
 };
@@ -86,5 +270,6 @@ struct kvm_guest_debug_arch {
 
 #define KVM_INTERRUPT_SET       -1U
 #define KVM_INTERRUPT_UNSET     -2U
+#define KVM_INTERRUPT_SET_LEVEL -3U
 
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/include/asm/kvm_44x.h b/arch/powerpc/include/asm/kvm_44x.h
index d22d39942a92..a0e57618ff33 100644
--- a/arch/powerpc/include/asm/kvm_44x.h
+++ b/arch/powerpc/include/asm/kvm_44x.h
@@ -61,7 +61,6 @@ static inline struct kvmppc_vcpu_44x *to_44x(struct kvm_vcpu *vcpu)
         return container_of(vcpu, struct kvmppc_vcpu_44x, vcpu);
 }
 
-void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 new_pid);
 void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu);
 void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu);
 
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index c5ea4cda34b3..0951b17f4eb5 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -58,6 +58,8 @@
 #define BOOK3S_INTERRUPT_INST_STORAGE   0x400
 #define BOOK3S_INTERRUPT_INST_SEGMENT   0x480
 #define BOOK3S_INTERRUPT_EXTERNAL       0x500
+#define BOOK3S_INTERRUPT_EXTERNAL_LEVEL 0x501
+#define BOOK3S_INTERRUPT_EXTERNAL_HV    0x502
 #define BOOK3S_INTERRUPT_ALIGNMENT      0x600
 #define BOOK3S_INTERRUPT_PROGRAM        0x700
 #define BOOK3S_INTERRUPT_FP_UNAVAIL     0x800
@@ -84,7 +86,8 @@
 #define BOOK3S_IRQPRIO_EXTERNAL                 13
 #define BOOK3S_IRQPRIO_DECREMENTER              14
 #define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR      15
-#define BOOK3S_IRQPRIO_MAX                      16
+#define BOOK3S_IRQPRIO_EXTERNAL_LEVEL           16
+#define BOOK3S_IRQPRIO_MAX                      17
 
 #define BOOK3S_HFLAG_DCBZ32                     0x1
 #define BOOK3S_HFLAG_SLB                        0x2
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 8274a2d43925..d62e703f1214 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -38,15 +38,6 @@ struct kvmppc_slb {
         bool class      : 1;
 };
 
-struct kvmppc_sr {
-        u32 raw;
-        u32 vsid;
-        bool Ks         : 1;
-        bool Kp         : 1;
-        bool nx         : 1;
-        bool valid      : 1;
-};
-
 struct kvmppc_bat {
         u64 raw;
         u32 bepi;
@@ -69,6 +60,13 @@ struct kvmppc_sid_map {
 #define SID_MAP_NUM     (1 << SID_MAP_BITS)
 #define SID_MAP_MASK    (SID_MAP_NUM - 1)
 
+#ifdef CONFIG_PPC_BOOK3S_64
+#define SID_CONTEXTS    1
+#else
+#define SID_CONTEXTS    128
+#define VSID_POOL_SIZE  (SID_CONTEXTS * 16)
+#endif
+
 struct kvmppc_vcpu_book3s {
         struct kvm_vcpu vcpu;
         struct kvmppc_book3s_shadow_vcpu *shadow_vcpu;
@@ -79,20 +77,22 @@ struct kvmppc_vcpu_book3s {
                 u64 vsid;
         } slb_shadow[64];
         u8 slb_shadow_max;
-        struct kvmppc_sr sr[16];
         struct kvmppc_bat ibat[8];
         struct kvmppc_bat dbat[8];
         u64 hid[6];
         u64 gqr[8];
         int slb_nr;
-        u32 dsisr;
         u64 sdr1;
         u64 hior;
         u64 msr_mask;
-        u64 vsid_first;
         u64 vsid_next;
+#ifdef CONFIG_PPC_BOOK3S_32
+        u32 vsid_pool[VSID_POOL_SIZE];
+#else
+        u64 vsid_first;
         u64 vsid_max;
-        int context_id;
+#endif
+        int context_id[SID_CONTEXTS];
         ulong prog_flags; /* flags to inject when giving a 700 trap */
 };
 
@@ -131,9 +131,10 @@ extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
                            bool upper, u32 val);
 extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
 extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu);
+extern pfn_t kvmppc_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn);
 
-extern u32 kvmppc_trampoline_lowmem;
-extern u32 kvmppc_trampoline_enter;
+extern ulong kvmppc_trampoline_lowmem;
+extern ulong kvmppc_trampoline_enter;
 extern void kvmppc_rmcall(ulong srr0, ulong srr1);
 extern void kvmppc_load_up_fpu(void);
 extern void kvmppc_load_up_altivec(void);
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 36fdb3aff30b..d5a8a3861635 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -34,6 +34,7 @@
             (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
             (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
             (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
+            (\intno == BOOK3S_INTERRUPT_EXTERNAL_HV) || \
             (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
             (\intno == BOOK3S_INTERRUPT_PROGRAM) || \
             (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
diff --git a/arch/powerpc/include/asm/kvm_e500.h b/arch/powerpc/include/asm/kvm_e500.h
index 7fea26fffb25..7a2a565f88c4 100644
--- a/arch/powerpc/include/asm/kvm_e500.h
+++ b/arch/powerpc/include/asm/kvm_e500.h
@@ -43,6 +43,7 @@ struct kvmppc_vcpu_e500 {
 
         u32 host_pid[E500_PID_NUM];
         u32 pid[E500_PID_NUM];
+        u32 svr;
 
         u32 mas0;
         u32 mas1;
@@ -58,6 +59,7 @@ struct kvmppc_vcpu_e500 {
         u32 hid1;
         u32 tlb0cfg;
         u32 tlb1cfg;
+        u64 mcar;
 
         struct kvm_vcpu vcpu;
 };
diff --git a/arch/powerpc/include/asm/kvm_fpu.h b/arch/powerpc/include/asm/kvm_fpu.h
index c3d4f0518a67..92daae132492 100644
--- a/arch/powerpc/include/asm/kvm_fpu.h
+++ b/arch/powerpc/include/asm/kvm_fpu.h
@@ -82,7 +82,7 @@ FPD_THREE_IN(fmadd)
 FPD_THREE_IN(fnmsub)
 FPD_THREE_IN(fnmadd)
 
-extern void kvm_cvt_fd(u32 *from, u64 *to, u64 *fpscr);
-extern void kvm_cvt_df(u64 *from, u32 *to, u64 *fpscr);
+extern void kvm_cvt_fd(u32 *from, u64 *to);
+extern void kvm_cvt_df(u64 *from, u32 *to);
 
 #endif
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index b0b23c007d6e..186f150b9b89 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/types.h>
 #include <linux/kvm_types.h>
+#include <linux/kvm_para.h>
 #include <asm/kvm_asm.h>
 
 #define KVM_MAX_VCPUS 1
@@ -41,12 +42,17 @@
 
 #define HPTEG_CACHE_NUM                 (1 << 15)
 #define HPTEG_HASH_BITS_PTE             13
+#define HPTEG_HASH_BITS_PTE_LONG        12
 #define HPTEG_HASH_BITS_VPTE            13
 #define HPTEG_HASH_BITS_VPTE_LONG       5
 #define HPTEG_HASH_NUM_PTE              (1 << HPTEG_HASH_BITS_PTE)
+#define HPTEG_HASH_NUM_PTE_LONG         (1 << HPTEG_HASH_BITS_PTE_LONG)
 #define HPTEG_HASH_NUM_VPTE             (1 << HPTEG_HASH_BITS_VPTE)
 #define HPTEG_HASH_NUM_VPTE_LONG        (1 << HPTEG_HASH_BITS_VPTE_LONG)
 
+/* Physical Address Mask - allowed range of real mode RAM access */
+#define KVM_PAM                 0x0fffffffffffffffULL
+
 struct kvm;
 struct kvm_run;
 struct kvm_vcpu;
@@ -159,8 +165,10 @@ struct kvmppc_mmu {
 
 struct hpte_cache {
         struct hlist_node list_pte;
+        struct hlist_node list_pte_long;
         struct hlist_node list_vpte;
         struct hlist_node list_vpte_long;
+        struct rcu_head rcu_head;
         u64 host_va;
         u64 pfn;
         ulong slot;
@@ -210,28 +218,24 @@ struct kvm_vcpu_arch {
         u32 cr;
 #endif
 
-        ulong msr;
 #ifdef CONFIG_PPC_BOOK3S
         ulong shadow_msr;
         ulong hflags;
         ulong guest_owned_ext;
 #endif
+        u32 vrsave; /* also USPRG0 */
         u32 mmucr;
-        ulong sprg0;
-        ulong sprg1;
-        ulong sprg2;
-        ulong sprg3;
         ulong sprg4;
         ulong sprg5;
         ulong sprg6;
         ulong sprg7;
-        ulong srr0;
-        ulong srr1;
         ulong csrr0;
         ulong csrr1;
         ulong dsrr0;
         ulong dsrr1;
-        ulong dear;
+        ulong mcsrr0;
+        ulong mcsrr1;
+        ulong mcsr;
         ulong esr;
         u32 dec;
         u32 decar;
@@ -255,6 +259,7 @@ struct kvm_vcpu_arch {
         u32 dbsr;
 
 #ifdef CONFIG_KVM_EXIT_TIMING
+        struct mutex exit_timing_lock;
         struct kvmppc_exit_timing timing_exit;
         struct kvmppc_exit_timing timing_last_enter;
         u32 last_exit_type;
@@ -290,12 +295,17 @@ struct kvm_vcpu_arch {
         struct tasklet_struct tasklet;
         u64 dec_jiffies;
         unsigned long pending_exceptions;
+        struct kvm_vcpu_arch_shared *shared;
+        unsigned long magic_page_pa; /* phys addr to map the magic page to */
+        unsigned long magic_page_ea; /* effect. addr to map the magic page to */
 
 #ifdef CONFIG_PPC_BOOK3S
         struct hlist_head hpte_hash_pte[HPTEG_HASH_NUM_PTE];
+        struct hlist_head hpte_hash_pte_long[HPTEG_HASH_NUM_PTE_LONG];
         struct hlist_head hpte_hash_vpte[HPTEG_HASH_NUM_VPTE];
         struct hlist_head hpte_hash_vpte_long[HPTEG_HASH_NUM_VPTE_LONG];
         int hpte_cache_count;
+        spinlock_t mmu_lock;
 #endif
 };
 
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
index 2d48f6a63d0b..50533f9adf40 100644
--- a/arch/powerpc/include/asm/kvm_para.h
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -20,16 +20,153 @@
 #ifndef __POWERPC_KVM_PARA_H__
 #define __POWERPC_KVM_PARA_H__
 
+#include <linux/types.h>
+
+struct kvm_vcpu_arch_shared {
+        __u64 scratch1;
+        __u64 scratch2;
+        __u64 scratch3;
+        __u64 critical;         /* Guest may not get interrupts if == r1 */
+        __u64 sprg0;
+        __u64 sprg1;
+        __u64 sprg2;
+        __u64 sprg3;
+        __u64 srr0;
+        __u64 srr1;
+        __u64 dar;
+        __u64 msr;
+        __u32 dsisr;
+        __u32 int_pending;      /* Tells the guest if we have an interrupt */
+        __u32 sr[16];
+};
+
+#define KVM_SC_MAGIC_R0         0x4b564d21 /* "KVM!" */
+#define HC_VENDOR_KVM           (42 << 16)
+#define HC_EV_SUCCESS           0
+#define HC_EV_UNIMPLEMENTED     12
+
+#define KVM_FEATURE_MAGIC_PAGE  1
+
+#define KVM_MAGIC_FEAT_SR       (1 << 0)
+
 #ifdef __KERNEL__
 
+#ifdef CONFIG_KVM_GUEST
+
+#include <linux/of.h>
+
+static inline int kvm_para_available(void)
+{
+        struct device_node *hyper_node;
+
+        hyper_node = of_find_node_by_path("/hypervisor");
+        if (!hyper_node)
+                return 0;
+
+        if (!of_device_is_compatible(hyper_node, "linux,kvm"))
+                return 0;
+
+        return 1;
+}
+
+extern unsigned long kvm_hypercall(unsigned long *in,
+                                   unsigned long *out,
+                                   unsigned long nr);
+
+#else
+
 static inline int kvm_para_available(void)
 {
         return 0;
 }
 
+static unsigned long kvm_hypercall(unsigned long *in,
+                                   unsigned long *out,
+                                   unsigned long nr)
+{
+        return HC_EV_UNIMPLEMENTED;
+}
+
+#endif
+
+static inline long kvm_hypercall0_1(unsigned int nr, unsigned long *r2)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+        unsigned long r;
+
+        r = kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+        *r2 = out[0];
+
+        return r;
+}
+
+static inline long kvm_hypercall0(unsigned int nr)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+}
+
+static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+}
+
+static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
+                                  unsigned long p2)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+}
+
+static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
+                                  unsigned long p2, unsigned long p3)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        in[2] = p3;
+        return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+}
+
+static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
+                                  unsigned long p2, unsigned long p3,
+                                  unsigned long p4)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        in[2] = p3;
+        in[3] = p4;
+        return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
+}
+
+
 static inline unsigned int kvm_arch_para_features(void)
 {
-        return 0;
+        unsigned long r;
+
+        if (!kvm_para_available())
+                return 0;
+
+        if(kvm_hypercall0_1(KVM_HC_FEATURES, &r))
+                return 0;
+
+        return r;
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 18d139ec2d22..9345238edecf 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -61,6 +61,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
                                       struct kvm_vcpu *vcpu);
 extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
 extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
+extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
 
 /* Core-specific hooks */
 
@@ -107,6 +108,7 @@ extern int kvmppc_booke_init(void);
 extern void kvmppc_booke_exit(void);
 
 extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu);
+extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu);
 
 /*
  * Cuts out inst bits with ordering according to spec.
@@ -141,4 +143,12 @@ static inline u32 kvmppc_set_field(u64 inst, int msb, int lsb, int value)
         return r;
 }
 
+void kvmppc_core_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
+int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
+
+void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
+int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
+
+void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
+
 #endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 14b592dfb4e8..e0298d26ce5d 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -33,9 +33,25 @@
 //
 //----------------------------------------------------------------------------
 #include <linux/cache.h>
+#include <linux/threads.h>
 #include <asm/types.h>
 #include <asm/mmu.h>
 
+/*
+ * We only have to have statically allocated lppaca structs on
+ * legacy iSeries, which supports at most 64 cpus.
+ */
+#ifdef CONFIG_PPC_ISERIES
+#if NR_CPUS < 64
+#define NR_LPPACAS      NR_CPUS
+#else
+#define NR_LPPACAS      64
+#endif
+#else /* not iSeries */
+#define NR_LPPACAS      1
+#endif
+
+
 /* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
  * alignment is sufficient to prevent this */
 struct lppaca {
@@ -62,7 +78,10 @@ struct lppaca {
         volatile u32 dyn_pir;           // Dynamic ProcIdReg value      x20-x23
         u32     dsei_data;              // DSEI data                    x24-x27
         u64     sprg3;                  // SPRG3 value                  x28-x2F
-        u8      reserved3[80];          // Reserved                     x30-x7F
+        u8      reserved3[40];          // Reserved                     x30-x57
+        volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
+                                        // associativity change counters x58-x5F
+        u8      reserved4[32];          // Reserved                     x60-x7F
 
 //=============================================================================
 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
@@ -86,7 +105,7 @@ struct lppaca {
         // processing of external interrupts.  Note that PLIC will store the
         // XIRR directly into the xXirrValue field so that another XIRR will
         // not be presented until this one clears.  The layout of the low
-        // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
+        // 4-bytes of this Dword is up to SLIC - PLIC just checks whether the
         // entire Dword is zero or not.  A non-zero value in the low order
         // 2-bytes will result in SLIC being granted the highest thread
         // priority upon return.  A 0 will return to SLIC as medium priority.
@@ -153,6 +172,8 @@ struct lppaca {
 
 extern struct lppaca lppaca[];
 
+#define lppaca_of(cpu)  (*paca[cpu].lppaca_ptr)
+
 /*
  * SLB shadow buffer structure as defined in the PAPR.  The save_area
  * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
@@ -170,6 +191,35 @@ struct slb_shadow {
 
 extern struct slb_shadow slb_shadow[];
 
+/*
+ * Layout of entries in the hypervisor's dispatch trace log buffer.
+ */
+struct dtl_entry {
+        u8      dispatch_reason;
+        u8      preempt_reason;
+        u16     processor_id;
+        u32     enqueue_to_dispatch_time;
+        u32     ready_to_enqueue_time;
+        u32     waiting_to_ready_time;
+        u64     timebase;
+        u64     fault_addr;
+        u64     srr0;
+        u64     srr1;
+};
+
+#define DISPATCH_LOG_BYTES      4096    /* bytes per cpu */
+#define N_DISPATCH_LOG          (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
+
+extern struct kmem_cache *dtl_cache;
+
+/*
+ * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
+ * reading from the dispatch trace log.  If other code wants to consume
+ * DTL entries, it can set this pointer to a function that will get
+ * called once for each DTL entry that gets processed.
+ */
+extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
+
 #endif /* CONFIG_PPC_BOOK3S */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index adc8e6cdf339..47cacddb14cf 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -27,24 +27,7 @@ struct iommu_table;
 struct rtc_time;
 struct file;
 struct pci_controller;
-#ifdef CONFIG_KEXEC
 struct kimage;
-#endif
-
-#ifdef CONFIG_SMP
-struct smp_ops_t {
-        void  (*message_pass)(int target, int msg);
-        int   (*probe)(void);
-        void  (*kick_cpu)(int nr);
-        void  (*setup_cpu)(int nr);
-        void  (*take_timebase)(void);
-        void  (*give_timebase)(void);
-        int   (*cpu_enable)(unsigned int nr);
-        int   (*cpu_disable)(void);
-        void  (*cpu_die)(unsigned int nr);
-        int   (*cpu_bootable)(unsigned int nr);
-};
-#endif
 
 struct machdep_calls {
         char            *name;
@@ -72,7 +55,7 @@ struct machdep_calls {
                                              int psize, int ssize);
         void            (*flush_hash_range)(unsigned long number, int local);
 
-        /* special for kexec, to be called in real mode, linar mapping is
+        /* special for kexec, to be called in real mode, linear mapping is
          * destroyed as well */
         void            (*hpte_clear_all)(void);
 
@@ -102,6 +85,9 @@ struct machdep_calls {
         void            (*pci_dma_dev_setup)(struct pci_dev *dev);
         void            (*pci_dma_bus_setup)(struct pci_bus *bus);
 
+        /* Platform set_dma_mask override */
+        int             (*dma_set_mask)(struct device *dev, u64 dma_mask);
+
         int             (*probe)(void);
         void            (*setup_arch)(void); /* Optional, may be NULL */
         void            (*init_early)(void);
@@ -115,9 +101,6 @@ struct machdep_calls {
          * If for some reason there is no irq, but the interrupt
          * shouldn't be counted as spurious, return NO_IRQ_IGNORE. */
         unsigned int    (*get_irq)(void);
-#ifdef CONFIG_KEXEC
-        void            (*kexec_cpu_down)(int crash_shutdown, int secondary);
-#endif
 
         /* PCI stuff */
         /* Called after scanning the bus, before allocating resources */
@@ -234,11 +217,7 @@ struct machdep_calls {
         void (*machine_shutdown)(void);
 
 #ifdef CONFIG_KEXEC
-        /* Called to do the minimal shutdown needed to run a kexec'd kernel
-         * to run successfully.
-         * XXX Should we move this one out of kexec scope?
-         */
-        void (*machine_crash_shutdown)(struct pt_regs *regs);
+        void (*kexec_cpu_down)(int crash_shutdown, int secondary);
 
         /* Called to do what every setup is needed on image and the
          * reboot code buffer. Returns 0 on success.
@@ -247,9 +226,6 @@ struct machdep_calls {
          */
         int (*machine_kexec_prepare)(struct kimage *image);
 
-        /* Called to handle any machine specific cleanup on image */
-        void (*machine_kexec_cleanup)(struct kimage *image);
-
         /* Called to perform the _real_ kexec.
          * Do NOT allocate memory or fail here. We are past the point of
          * no return.
@@ -276,7 +252,7 @@ struct machdep_calls {
 
 extern void e500_idle(void);
 extern void power4_idle(void);
-extern void power4_cpu_offline_powersave(void);
+extern void power7_idle(void);
 extern void ppc6xx_idle(void);
 extern void book3e_idle(void);
 
@@ -321,14 +297,6 @@ extern sys_ctrler_t sys_ctrler;
 
 #endif /* CONFIG_PPC_PMAC */
 
-extern void setup_pci_ptrs(void);
-
-#ifdef CONFIG_SMP
-/* Poor default implementations */
-extern void __devinit smp_generic_give_timebase(void);
-extern void __devinit smp_generic_take_timebase(void);
-#endif /* CONFIG_SMP */
-
 
 /* Functions to produce codes on the leds.
  * The SRC code should be unique for the message category and should
diff --git a/arch/powerpc/include/asm/memblock.h b/arch/powerpc/include/asm/memblock.h
index 3c29728b56b1..43efc345065e 100644
--- a/arch/powerpc/include/asm/memblock.h
+++ b/arch/powerpc/include/asm/memblock.h
@@ -5,11 +5,4 @@
 
 #define MEMBLOCK_DBG(fmt...) udbg_printf(fmt)
 
-#ifdef CONFIG_PPC32
-extern phys_addr_t lowmem_end_addr;
-#define MEMBLOCK_REAL_LIMIT     lowmem_end_addr
-#else
-#define MEMBLOCK_REAL_LIMIT     0
-#endif
-
 #endif /* _ASM_POWERPC_MEMBLOCK_H */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 87a1d787c5b6..3ea0f9a259d8 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -40,9 +40,10 @@
 
 /* MAS registers bit definitions */
 
-#define MAS0_TLBSEL(x)          ((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)            ((x << 16) & 0x0FFF0000)
+#define MAS0_TLBSEL(x)          (((x) << 28) & 0x30000000)
+#define MAS0_ESEL(x)            (((x) << 16) & 0x0FFF0000)
 #define MAS0_NV(x)              ((x) & 0x00000FFF)
+#define MAS0_ESEL_MASK          0x0FFF0000
 #define MAS0_HES                0x00004000
 #define MAS0_WQ_ALLWAYS         0x00000000
 #define MAS0_WQ_COND            0x00001000
@@ -50,12 +51,12 @@
 
 #define MAS1_VALID              0x80000000
 #define MAS1_IPROT              0x40000000
-#define MAS1_TID(x)             ((x << 16) & 0x3FFF0000)
+#define MAS1_TID(x)             (((x) << 16) & 0x3FFF0000)
 #define MAS1_IND                0x00002000
 #define MAS1_TS                 0x00001000
 #define MAS1_TSIZE_MASK         0x00000f80
 #define MAS1_TSIZE_SHIFT        7
-#define MAS1_TSIZE(x)           ((x << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
+#define MAS1_TSIZE(x)           (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
 
 #define MAS2_EPN                0xFFFFF000
 #define MAS2_X0                 0x00000040
@@ -114,6 +115,17 @@
 
 #define MAS7_RPN                0xFFFFFFFF
 
+/* Bit definitions for MMUCFG */
+#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
+#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
+#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
+#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
+#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
+#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
+#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
+#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
+
 /* Bit definitions for MMUCSR0 */
 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
@@ -126,6 +138,21 @@
 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 
+/* MMUCFG bits */
+#define MMUCFG_MAVN_NASK        0x00000003
+#define MMUCFG_MAVN_V1_0        0x00000000
+#define MMUCFG_MAVN_V2_0        0x00000001
+#define MMUCFG_NTLB_MASK        0x0000000c
+#define MMUCFG_NTLB_SHIFT       2
+#define MMUCFG_PIDSIZE_MASK     0x000007c0
+#define MMUCFG_PIDSIZE_SHIFT    6
+#define MMUCFG_TWC              0x00008000
+#define MMUCFG_LRAT             0x00010000
+#define MMUCFG_RASIZE_MASK      0x00fe0000
+#define MMUCFG_RASIZE_SHIFT     17
+#define MMUCFG_LPIDSIZE_MASK    0x0f000000
+#define MMUCFG_LPIDSIZE_SHIFT   24
+
 /* TLBnCFG encoding */
 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 #define TLBnCFG_HES             0x00002000      /* HW select supported */
@@ -133,6 +160,10 @@
 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
+#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
+#define TLBnCFG_MINSIZE_SHIFT   20
+#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
+#define TLBnCFG_MAXSIZE_SHIFT   16
 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 
 /* TLBnPS encoding */
@@ -214,6 +245,10 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 extern int mmu_linear_psize;
 extern int mmu_vmemmap_psize;
 
+#ifdef CONFIG_PPC64
+extern unsigned long linear_map_top;
+#endif
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index acac35d5b382..d865bd909c7d 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -27,7 +27,7 @@
 #define STE_VSID_SHIFT  12
 
 /* Location of cpu0's segment table */
-#define STAB0_PAGE      0x6
+#define STAB0_PAGE      0x8
 #define STAB0_OFFSET    (STAB0_PAGE << 12)
 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
 
@@ -408,6 +408,7 @@ static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 
 typedef unsigned long mm_context_id_t;
+struct spinlock;
 
 typedef struct {
         mm_context_id_t id;
@@ -423,6 +424,11 @@ typedef struct {
 #ifdef CONFIG_PPC_SUBPAGE_PROT
         struct subpage_prot_table spt;
 #endif /* CONFIG_PPC_SUBPAGE_PROT */
+#ifdef CONFIG_PPC_ICSWX
+        struct spinlock *cop_lockp; /* guard acop and cop_pid */
+        unsigned long acop;     /* mask of enabled coprocessor types */
+        unsigned int cop_pid;   /* pid value used with coprocessors */
+#endif /* CONFIG_PPC_ICSWX */
 } mm_context_t;
 
 
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 7ebf42ed84a2..4138b21ae80a 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -2,6 +2,8 @@
 #define _ASM_POWERPC_MMU_H_
 #ifdef __KERNEL__
 
+#include <linux/types.h>
+
 #include <asm/asm-compat.h>
 #include <asm/feature-fixups.h>
 
@@ -54,11 +56,6 @@
  */
 #define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
 
-/* This indicates that the processor uses the ISA 2.06 server tlbie
- * mnemonics
- */
-#define MMU_FTR_TLBIE_206               ASM_CONST(0x00400000)
-
 /* Enable use of TLB reservation.  Processor should support tlbsrx.
  * instruction and MAS0[WQ].
  */
@@ -68,6 +65,53 @@
  */
 #define MMU_FTR_USE_PAIRED_MAS          ASM_CONST(0x01000000)
 
+/* MMU is SLB-based
+ */
+#define MMU_FTR_SLB                     ASM_CONST(0x02000000)
+
+/* Support 16M large pages
+ */
+#define MMU_FTR_16M_PAGE                ASM_CONST(0x04000000)
+
+/* Supports TLBIEL variant
+ */
+#define MMU_FTR_TLBIEL                  ASM_CONST(0x08000000)
+
+/* Supports tlbies w/o locking
+ */
+#define MMU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x10000000)
+
+/* Large pages can be marked CI
+ */
+#define MMU_FTR_CI_LARGE_PAGE           ASM_CONST(0x20000000)
+
+/* 1T segments available
+ */
+#define MMU_FTR_1T_SEGMENT              ASM_CONST(0x40000000)
+
+/* Doesn't support the B bit (1T segment) in SLBIE
+ */
+#define MMU_FTR_NO_SLBIE_B              ASM_CONST(0x80000000)
+
+/* MMU feature bit sets for various CPUs */
+#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2   \
+        MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
+#define MMU_FTRS_POWER4         MMU_FTRS_DEFAULT_HPTE_ARCH_V2
+#define MMU_FTRS_PPC970         MMU_FTRS_POWER4
+#define MMU_FTRS_POWER5         MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER6         MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER7         MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_CELL           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+                                MMU_FTR_CI_LARGE_PAGE
+#define MMU_FTRS_PA6T           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+                                MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
+#define MMU_FTRS_A2             MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
+                                MMU_FTR_USE_TLBIVAX_BCAST | \
+                                MMU_FTR_LOCK_BCAST_INVAL | \
+                                MMU_FTR_USE_TLBRSRV | \
+                                MMU_FTR_USE_PAIRED_MAS | \
+                                MMU_FTR_TLBIEL | \
+                                MMU_FTR_16M_PAGE
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
 
@@ -82,6 +126,16 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
 extern void early_init_mmu(void);
 extern void early_init_mmu_secondary(void);
 
+extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                       phys_addr_t first_memblock_size);
+
+#ifdef CONFIG_PPC64
+/* This is our real memory area size on ppc64 server, on embedded, we
+ * make it match the size our of bolted TLB area
+ */
+extern u64 ppc64_rma_size;
+#endif /* CONFIG_PPC64 */
+
 #endif /* !__ASSEMBLY__ */
 
 /* The kernel use the constants below to index in the page sizes array.
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 81fb41289d6c..a73668a5f30d 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -32,6 +32,10 @@ extern void __destroy_context(unsigned long context_id);
 extern void mmu_context_init(void);
 #endif
 
+extern void switch_cop(struct mm_struct *next);
+extern int use_cop(unsigned long acop, struct mm_struct *mm);
+extern void drop_cop(unsigned long acop, struct mm_struct *mm);
+
 /*
  * switch_mm is the entry point called from the architecture independent
  * code in kernel/sched.c
@@ -55,6 +59,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         if (prev == next)
                 return;
 
+#ifdef CONFIG_PPC_ICSWX
+        /* Switch coprocessor context only if prev or next uses a coprocessor */
+        if (prev->context.acop || next->context.acop)
+                switch_cop(next);
+#endif /* CONFIG_PPC_ICSWX */
+
         /* We must stop all altivec streams before changing the HW
          * context
          */
@@ -67,7 +77,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
          * sub architectures.
          */
 #ifdef CONFIG_PPC_STD_MMU_64
-        if (cpu_has_feature(CPU_FTR_SLB))
+        if (mmu_has_feature(MMU_FTR_SLB))
                 switch_slb(tsk, next);
         else
                 switch_stab(tsk, next);
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
index aac87cbceb57..7b589178be46 100644
--- a/arch/powerpc/include/asm/mmzone.h
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -33,15 +33,13 @@ extern int numa_cpu_lookup_table[];
 extern cpumask_var_t node_to_cpumask_map[];
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern unsigned long max_pfn;
+u64 memory_hotplug_max(void);
+#else
+#define memory_hotplug_max() memblock_end_of_DRAM()
 #endif
 
-/*
- * Following are macros that each numa implmentation must define.
- */
-
-#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
-
+#else
+#define memory_hotplug_max() memblock_end_of_DRAM()
 #endif /* CONFIG_NEED_MULTIPLE_NODES */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e000cce8f6dd..df18989e78d4 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -3,7 +3,6 @@
 #ifdef __KERNEL__
 
 #include <linux/irq.h>
-#include <linux/sysdev.h>
 #include <asm/dcr.h>
 #include <asm/msi_bitmap.h>
 
@@ -263,6 +262,7 @@ struct mpic
 #ifdef CONFIG_SMP
         struct irq_chip         hc_ipi;
 #endif
+        struct irq_chip         hc_tm;
         const char              *name;
         /* Flags */
         unsigned int            flags;
@@ -281,7 +281,7 @@ struct mpic
 
         /* vector numbers used for internal sources (ipi/timers) */
         unsigned int            ipi_vecs[4];
-        unsigned int            timer_vecs[4];
+        unsigned int            timer_vecs[8];
 
         /* Spurious vector to program into unused sources */
         unsigned int            spurious_vec;
@@ -320,8 +320,6 @@ struct mpic
         /* link */
         struct mpic             *next;
 
-        struct sys_device       sysdev;
-
 #ifdef CONFIG_PM
         struct mpic_irq_save    *save_data;
 #endif
@@ -367,6 +365,12 @@ struct mpic
 #define MPIC_SINGLE_DEST_CPU            0x00001000
 /* Enable CoreInt delivery of interrupts */
 #define MPIC_ENABLE_COREINT             0x00002000
+/* Disable resetting of the MPIC.
+ * NOTE: This flag trumps MPIC_WANTS_RESET.
+ */
+#define MPIC_NO_RESET                   0x00004000
+/* Freescale MPIC (compatible includes "fsl,mpic") */
+#define MPIC_FSL                        0x00008000
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK                0xf0000000
@@ -467,11 +471,11 @@ extern void mpic_request_ipis(void);
 void smp_mpic_message_pass(int target, int msg);
 
 /* Unmask a specific virq */
-extern void mpic_unmask_irq(unsigned int irq);
+extern void mpic_unmask_irq(struct irq_data *d);
 /* Mask a specific virq */
-extern void mpic_mask_irq(unsigned int irq);
+extern void mpic_mask_irq(struct irq_data *d);
 /* EOI a specific virq */
-extern void mpic_end_irq(unsigned int irq);
+extern void mpic_end_irq(struct irq_data *d);
 
 /* Fetch interrupt from a given mpic */
 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index 850b72f27445..9d1aafe607c7 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -10,31 +10,7 @@
 #ifndef _ASM_POWERPC_NVRAM_H
 #define _ASM_POWERPC_NVRAM_H
 
-#include <linux/errno.h>
-
-#define NVRW_CNT 0x20
-#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
-#define NVRAM_BLOCK_LEN 16
-#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
-#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
-
-#define NVRAM_AS0  0x74
-#define NVRAM_AS1  0x75
-#define NVRAM_DATA 0x77
-
-
-/* RTC Offsets */
-
-#define MOTO_RTC_SECONDS        0x1FF9
-#define MOTO_RTC_MINUTES        0x1FFA
-#define MOTO_RTC_HOURS          0x1FFB
-#define MOTO_RTC_DAY_OF_WEEK    0x1FFC
-#define MOTO_RTC_DAY_OF_MONTH   0x1FFD
-#define MOTO_RTC_MONTH          0x1FFE
-#define MOTO_RTC_YEAR           0x1FFF
-#define MOTO_RTC_CONTROLA       0x1FF8
-#define MOTO_RTC_CONTROLB       0x1FF9
-
+/* Signatures for nvram partitions */
 #define NVRAM_SIG_SP    0x02    /* support processor */
 #define NVRAM_SIG_OF    0x50    /* open firmware config */
 #define NVRAM_SIG_FW    0x51    /* general firmware */
@@ -49,32 +25,19 @@
 #define NVRAM_SIG_OS    0xa0    /* OS defined */
 #define NVRAM_SIG_PANIC 0xa1    /* Apple OSX "panic" */
 
-/* If change this size, then change the size of NVNAME_LEN */
-struct nvram_header {
-        unsigned char signature;
-        unsigned char checksum;
-        unsigned short length;
-        char name[12];
-};
-
 #ifdef __KERNEL__
 
+#include <linux/errno.h>
 #include <linux/list.h>
 
-struct nvram_partition {
-        struct list_head partition;
-        struct nvram_header header;
-        unsigned int index;
-};
-
-
+#ifdef CONFIG_PPC_PSERIES
 extern int nvram_write_error_log(char * buff, int length,
                                          unsigned int err_type, unsigned int err_seq);
 extern int nvram_read_error_log(char * buff, int length,
                                          unsigned int * err_type, unsigned int *err_seq);
 extern int nvram_clear_error_log(void);
-
 extern int pSeries_nvram_init(void);
+#endif /* CONFIG_PPC_PSERIES */
 
 #ifdef CONFIG_MMIO_NVRAM
 extern int mmio_nvram_init(void);
@@ -85,6 +48,14 @@ static inline int mmio_nvram_init(void)
 }
 #endif
 
+extern int __init nvram_scan_partitions(void);
+extern loff_t nvram_create_partition(const char *name, int sig,
+                                     int req_size, int min_size);
+extern int nvram_remove_partition(const char *name, int sig,
+                                        const char *exceptions[]);
+extern int nvram_get_partition_size(loff_t data_index);
+extern loff_t nvram_find_partition(const char *name, int sig, int *out_size);
+
 #endif /* __KERNEL__ */
 
 /* PowerMac specific nvram stuffs */
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
index d4b4bfa26fb3..89d2f99c1bf4 100644
--- a/arch/powerpc/include/asm/pSeries_reconfig.h
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -18,13 +18,18 @@
 extern int pSeries_reconfig_notifier_register(struct notifier_block *);
 extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
 extern struct blocking_notifier_head pSeries_reconfig_chain;
+/* Not the best place to put this, will be fixed when we move some
+ * of the rtas suspend-me stuff to pseries */
+extern void pSeries_coalesce_init(void);
 #else /* !CONFIG_PPC_PSERIES */
 static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
 {
         return 0;
 }
 static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
+static inline void pSeries_coalesce_init(void) { }
 #endif /* CONFIG_PPC_PSERIES */
 
+
 #endif /* __KERNEL__ */
 #endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 1ff6662f7faf..74126765106a 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -85,14 +85,16 @@ struct paca_struct {
         u8 kexec_state;         /* set when kexec down has irqs off */
 #ifdef CONFIG_PPC_STD_MMU_64
         struct slb_shadow *slb_shadow_ptr;
+        struct dtl_entry *dispatch_log;
+        struct dtl_entry *dispatch_log_end;
 
         /*
          * Now, starting in cacheline 2, the exception save areas
          */
         /* used for most interrupts/exceptions */
-        u64 exgen[10] __attribute__((aligned(0x80)));
-        u64 exmc[10];           /* used for machine checks */
-        u64 exslb[10];          /* used for SLB/segment table misses
+        u64 exgen[11] __attribute__((aligned(0x80)));
+        u64 exmc[11];           /* used for machine checks */
+        u64 exslb[11];          /* used for SLB/segment table misses
                                  * on the linear mapping */
         /* SLB related definitions */
         u16 vmalloc_sllp;
@@ -104,7 +106,8 @@ struct paca_struct {
         pgd_t *pgd;                     /* Current PGD */
         pgd_t *kernel_pgd;              /* Kernel PGD */
         u64 exgen[8] __attribute__((aligned(0x80)));
-        u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
+        /* We can have up to 3 levels of reentrancy in the TLB miss handler */
+        u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
         u64 exmc[8];            /* used for machine checks */
         u64 excrit[8];          /* used for crit interrupts */
         u64 exdbg[8];           /* used for debug interrupts */
@@ -123,19 +126,25 @@ struct paca_struct {
         struct task_struct *__current;  /* Pointer to current */
         u64 kstack;                     /* Saved Kernel stack addr */
         u64 stab_rr;                    /* stab/slb round-robin counter */
-        u64 saved_r1;                   /* r1 save for RTAS calls */
+        u64 saved_r1;                   /* r1 save for RTAS calls or PM */
         u64 saved_msr;                  /* MSR saved here by enter_rtas */
         u16 trap_save;                  /* Used when bad stack is encountered */
         u8 soft_enabled;                /* irq soft-enable flag */
         u8 hard_enabled;                /* set if irqs are enabled in MSR */
         u8 io_sync;                     /* writel() needs spin_unlock sync */
-        u8 perf_event_pending;          /* PM interrupt while soft-disabled */
+        u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
 
         /* Stuff for accurate time accounting */
         u64 user_time;                  /* accumulated usermode TB ticks */
         u64 system_time;                /* accumulated system TB ticks */
-        u64 startpurr;                  /* PURR/TB value snapshot */
+        u64 user_time_scaled;           /* accumulated usermode SPURR ticks */
+        u64 starttime;                  /* TB value snapshot */
+        u64 starttime_user;             /* TB value on exit to usermode */
         u64 startspurr;                 /* SPURR value snapshot */
+        u64 utime_sspurr;               /* ->user_time when ->startspurr set */
+        u64 stolen_time;                /* TB ticks taken by hypervisor */
+        u64 dtl_ridx;                   /* read index in dispatch log */
+        struct dtl_entry *dtl_curr;     /* pointer corresponding to dtl_ridx */
 
 #ifdef CONFIG_KVM_BOOK3S_HANDLER
         /* We use this to store guest state in */
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 53b64be40eb2..2cd664ef0a5e 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -100,8 +100,8 @@ extern phys_addr_t kernstart_addr;
 #endif
 
 #ifdef CONFIG_FLATMEM
-#define ARCH_PFN_OFFSET         (MEMORY_START >> PAGE_SHIFT)
-#define pfn_valid(pfn)          ((pfn) >= ARCH_PFN_OFFSET && (pfn) < (ARCH_PFN_OFFSET + max_mapnr))
+#define ARCH_PFN_OFFSET         ((unsigned long)(MEMORY_START >> PAGE_SHIFT))
+#define pfn_valid(pfn)          ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
 #endif
 
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 358ff14ea25e..9356262fd3cc 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -59,24 +59,7 @@ static __inline__ void clear_page(void *addr)
         : "ctr", "memory");
 }
 
-extern void copy_4K_page(void *to, void *from);
-
-#ifdef CONFIG_PPC_64K_PAGES
-static inline void copy_page(void *to, void *from)
-{
-        unsigned int i;
-        for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
-                copy_4K_page(to, from);
-                to += 4096;
-                from += 4096;
-        }
-}
-#else /* CONFIG_PPC_64K_PAGES */
-static inline void copy_page(void *to, void *from)
-{
-        copy_4K_page(to, from);
-}
-#endif /* CONFIG_PPC_64K_PAGES */
+extern void copy_page(void *to, void *from);
 
 /* Log 2 of page table size */
 extern u64 ppc64_pft_size;
@@ -130,7 +113,7 @@ extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
 extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
                                   unsigned long len, unsigned int psize);
 
-#define slice_mm_new_context(mm)        ((mm)->context.id == 0)
+#define slice_mm_new_context(mm)        ((mm)->context.id == MMU_NO_CONTEXT)
 
 #endif /* __ASSEMBLY__ */
 #else
@@ -163,13 +146,13 @@ do {						\
 #endif /* !CONFIG_HUGETLB_PAGE */
 
 #define VM_DATA_DEFAULT_FLAGS \
-        (test_thread_flag(TIF_32BIT) ? \
+        (is_32bit_task() ? \
          VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
 
 /*
  * This is the default if a program doesn't have a PT_GNU_STACK
  * program header entry. The PPC64 ELF ABI has a non executable stack
- * stack by default, so in the absense of a PT_GNU_STACK program header
+ * stack by default, so in the absence of a PT_GNU_STACK program header
  * we turn execute permission off.
  */
 #define VM_STACK_DEFAULT_FLAGS32        (VM_READ | VM_WRITE | VM_EXEC | \
@@ -179,7 +162,7 @@ do {						\
                                          VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
 #define VM_STACK_DEFAULT_FLAGS \
-        (test_thread_flag(TIF_32BIT) ? \
+        (is_32bit_task() ? \
          VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
 
 #include <asm-generic/getorder.h>
diff --git a/arch/powerpc/include/asm/pasemi_dma.h b/arch/powerpc/include/asm/pasemi_dma.h
index 19fd7933e2d9..eafa5a5f56de 100644
--- a/arch/powerpc/include/asm/pasemi_dma.h
+++ b/arch/powerpc/include/asm/pasemi_dma.h
@@ -522,7 +522,7 @@ extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
 extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
                                 dma_addr_t *handle);
 
-/* Routines to allocate flags (events) for channel syncronization */
+/* Routines to allocate flags (events) for channel synchronization */
 extern int  pasemi_dma_alloc_flag(void);
 extern void pasemi_dma_free_flag(int flag);
 extern void pasemi_dma_set_flag(int flag);
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 51e9e6f90d12..b90dbf8e5cd9 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -106,7 +106,7 @@ struct pci_controller {
          * Used for variants of PCI indirect handling and possible quirks:
          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
          *  EXT_REG - provides access to PCI-e extended registers
-         *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
+         *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
          *   to determine which bus number to match on when generating type0
          *   config cycles
@@ -164,13 +164,23 @@ extern void setup_indirect_pci(struct pci_controller* hose,
                                resource_size_t cfg_addr,
                                resource_size_t cfg_data, u32 flags);
 
-#ifndef CONFIG_PPC64
-
 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 {
         return bus->sysdata;
 }
 
+#ifndef CONFIG_PPC64
+
+static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
+{
+        struct pci_controller *host;
+
+        if (bus->self)
+                return pci_device_to_OF_node(bus->self);
+        host = pci_bus_to_host(bus);
+        return host ? host->dn : NULL;
+}
+
 static inline int isa_vaddr_is_ioport(void __iomem *address)
 {
         /* No specific ISA handling on ppc32 at this stage, it
@@ -218,19 +228,10 @@ extern void * update_dn_pci_info(struct device_node *dn, void *data);
 
 /* Get a device_node from a pci_dev.  This code must be fast except
  * in the case where the sysdata is incorrect and needs to be fixed
- * up (this will only happen once).
- * In this case the sysdata will have been inherited from a PCI host
- * bridge or a PCI-PCI bridge further up the tree, so it will point
- * to a valid struct pci_dn, just not the one we want.
- */
+ * up (this will only happen once). */
 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 {
-        struct device_node *dn = dev->sysdata;
-        struct pci_dn *pdn = dn->data;
-
-        if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
-                return dn;      /* fast path.  sysdata is good */
-        return fetch_dev_dn(dev);
+        return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev);
 }
 
 static inline int pci_device_from_OF_node(struct device_node *np,
@@ -248,7 +249,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
         if (bus->self)
                 return pci_device_to_OF_node(bus->self);
         else
-                return bus->sysdata; /* Must be root bus (PHB) */
+                return bus->dev.of_node; /* Must be root bus (PHB) */
 }
 
 /** Find the bus corresponding to the indicated device node */
@@ -260,14 +261,6 @@ extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 /** Discover new pci devices under this bus, and add them */
 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 
-static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
-{
-        struct device_node *busdn = bus->sysdata;
-
-        BUG_ON(busdn == NULL);
-        return PCI_DN(busdn)->phb;
-}
-
 
 extern void isa_bridge_find_early(struct pci_controller *hose);
 
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index a20a9ad2258b..7d7790954e02 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -201,7 +201,7 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
 extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
-extern void pcibios_scan_phb(struct pci_controller *hose, void *sysdata);
+extern void pcibios_scan_phb(struct pci_controller *hose);
 
 #endif  /* __KERNEL__ */
 #endif /* __ASM_POWERPC_PCI_H */
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index abe8532bd14e..bf301ac62f35 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -31,14 +31,29 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
 #endif
 
 #ifdef CONFIG_SMP
-extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift);
-extern void pte_free_finish(void);
+struct mmu_gather;
+extern void tlb_remove_table(struct mmu_gather *, void *);
+
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
+{
+        unsigned long pgf = (unsigned long)table;
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf |= shift;
+        tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+        pgtable_free(table, shift);
+}
 #else /* CONFIG_SMP */
 static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
 {
         pgtable_free(table, shift);
 }
-static inline void pte_free_finish(void) { }
 #endif /* !CONFIG_SMP */
 
 static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index a7db96f2b5c3..47edde8c3556 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -308,12 +308,8 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 #define pte_offset_kernel(dir, addr)    \
         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 #define pte_offset_map(dir, addr)               \
-        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
-#define pte_offset_map_nested(dir, addr)        \
-        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
-
-#define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
-#define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
+        ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
+#define pte_unmap(pte)          kunmap_atomic(pte)
 
 /*
  * Encode and decode a swap entry.
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 49865045d56f..81576ee0cfb1 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -193,9 +193,7 @@
   (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 
 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
-#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
 #define pte_unmap(pte)                  do { } while(0)
-#define pte_unmap_nested(pte)           do { } while(0)
 
 /* to find an entry in a kernel page-table-directory */
 /* This now only contains the vmalloc pages */
@@ -259,21 +257,20 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
                                       pte_t *ptep)
 {
-        unsigned long old;
 
-        if ((pte_val(*ptep) & _PAGE_RW) == 0)
-                return;
-        old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
+        if ((pte_val(*ptep) & _PAGE_RW) == 0)
+                return;
+
+        pte_update(mm, addr, ptep, _PAGE_RW, 0);
 }
 
 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
                                            unsigned long addr, pte_t *ptep)
 {
-        unsigned long old;
-
         if ((pte_val(*ptep) & _PAGE_RW) == 0)
                 return;
-        old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
+
+        pte_update(mm, addr, ptep, _PAGE_RW, 1);
 }
 
 /*
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 89f158731ce3..88b0bd925a8b 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,7 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
                                             _PAGE_COHERENT | _PAGE_WRITETHRU))
 
+#define pgprot_writecombine pgprot_noncached_wc
 
 struct file;
 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
index 00eedc5a4e61..10902c9375d0 100644
--- a/arch/powerpc/include/asm/pmac_feature.h
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -53,8 +53,8 @@
 
 /* Here is the infamous serie of OHare based machines
  */
-#define PMAC_TYPE_COMET                 0x20    /* Beleived to be PowerBook 2400 */
-#define PMAC_TYPE_HOOPER                0x21    /* Beleived to be PowerBook 3400 */
+#define PMAC_TYPE_COMET                 0x20    /* Believed to be PowerBook 2400 */
+#define PMAC_TYPE_HOOPER                0x21    /* Believed to be PowerBook 3400 */
 #define PMAC_TYPE_KANGA                 0x22    /* PowerBook 3500 (first G3) */
 #define PMAC_TYPE_ALCHEMY               0x23    /* Alchemy motherboard base */
 #define PMAC_TYPE_GAZELLE               0x24    /* Spartacus, some 5xxx/6xxx */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 43adc8b819ed..e472659d906c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -36,9 +36,15 @@
 #define PPC_INST_NOP                    0x60000000
 #define PPC_INST_POPCNTB                0x7c0000f4
 #define PPC_INST_POPCNTB_MASK           0xfc0007fe
+#define PPC_INST_POPCNTD                0x7c0003f4
+#define PPC_INST_POPCNTW                0x7c0002f4
 #define PPC_INST_RFCI                   0x4c000066
 #define PPC_INST_RFDI                   0x4c00004e
 #define PPC_INST_RFMCI                  0x4c00004c
+#define PPC_INST_MFSPR_DSCR             0x7c1102a6
+#define PPC_INST_MFSPR_DSCR_MASK        0xfc1fffff
+#define PPC_INST_MTSPR_DSCR             0x7c1103a6
+#define PPC_INST_MTSPR_DSCR_MASK        0xfc1fffff
 
 #define PPC_INST_STRING                 0x7c00042a
 #define PPC_INST_STRING_MASK            0xfc0007fe
@@ -54,6 +60,17 @@
 #define PPC_INST_TLBSRX_DOT             0x7c0006a5
 #define PPC_INST_XXLOR                  0xf0000510
 
+#define PPC_INST_NAP                    0x4c000364
+#define PPC_INST_SLEEP                  0x4c0003a4
+
+/* A2 specific instructions */
+#define PPC_INST_ERATWE                 0x7c0001a6
+#define PPC_INST_ERATRE                 0x7c000166
+#define PPC_INST_ERATILX                0x7c000066
+#define PPC_INST_ERATIVAX               0x7c000666
+#define PPC_INST_ERATSX                 0x7c000126
+#define PPC_INST_ERATSX_DOT             0x7c000127
+
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
@@ -65,6 +82,8 @@
 #define __PPC_XT(s)     __PPC_XS(s)
 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 #define __PPC_WC(w)     (((w) & 0x3) << 21)
+#define __PPC_WS(w)     (((w) & 0x1f) << 11)
+
 /*
  * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
  * larx with EH set as an illegal instruction.
@@ -88,6 +107,12 @@
                                         __PPC_RB(b) | __PPC_EH(eh))
 #define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
                                         __PPC_RB(b))
+#define PPC_POPCNTB(a, s)       stringify_in_c(.long PPC_INST_POPCNTB | \
+                                        __PPC_RA(a) | __PPC_RS(s))
+#define PPC_POPCNTD(a, s)       stringify_in_c(.long PPC_INST_POPCNTD | \
+                                        __PPC_RA(a) | __PPC_RS(s))
+#define PPC_POPCNTW(a, s)       stringify_in_c(.long PPC_INST_POPCNTW | \
+                                        __PPC_RA(a) | __PPC_RS(s))
 #define PPC_RFCI                stringify_in_c(.long PPC_INST_RFCI)
 #define PPC_RFDI                stringify_in_c(.long PPC_INST_RFDI)
 #define PPC_RFMCI               stringify_in_c(.long PPC_INST_RFMCI)
@@ -105,6 +130,21 @@
 #define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
                                         __PPC_RA(a) | __PPC_RB(b))
 
+#define PPC_ERATWE(s, a, w)     stringify_in_c(.long PPC_INST_ERATWE | \
+                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
+#define PPC_ERATRE(s, a, w)     stringify_in_c(.long PPC_INST_ERATRE | \
+                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
+#define PPC_ERATILX(t, a, b)    stringify_in_c(.long PPC_INST_ERATILX | \
+                                        __PPC_T_TLB(t) | __PPC_RA(a) | \
+                                        __PPC_RB(b))
+#define PPC_ERATIVAX(s, a, b)   stringify_in_c(.long PPC_INST_ERATIVAX | \
+                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
+#define PPC_ERATSX(t, a, w)     stringify_in_c(.long PPC_INST_ERATSX | \
+                                        __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
+                                        __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+
+
 /*
  * Define what the VSX XX1 form instructions will look like, then add
  * the 128 bit load store instructions based on that.
@@ -118,4 +158,7 @@
 #define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
                                                VSX_XX3((t), (a), (b)))
 
+#define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
+#define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
+
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 42fdff0e4b32..43268f15004e 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -28,8 +28,8 @@ extern void find_and_init_phbs(void);
 extern struct pci_dev *isa_bridge_pcidev;       /* may be NULL if no ISA bus */
 
 /** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
-#define BUID_HI(buid) ((buid) >> 32)
-#define BUID_LO(buid) ((buid) & 0xffffffff)
+#define BUID_HI(buid) upper_32_bits(buid)
+#define BUID_LO(buid) lower_32_bits(buid)
 
 /* PCI device_node operations */
 struct device_node;
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 498fe09263d3..1b422381fc16 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -9,6 +9,7 @@
 #include <asm/asm-compat.h>
 #include <asm/processor.h>
 #include <asm/ppc-opcode.h>
+#include <asm/firmware.h>
 
 #ifndef __ASSEMBLY__
 #error __FILE__ should only be used in assembler files
@@ -26,17 +27,13 @@
 #ifndef CONFIG_VIRT_CPU_ACCOUNTING
 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
+#define ACCOUNT_STOLEN_TIME
 #else
 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)                                  \
         beq     2f;                     /* if from kernel mode */       \
-BEGIN_FTR_SECTION;                                                      \
-        mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
-END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
-BEGIN_FTR_SECTION;                                                      \
-        MFTB(ra);                       /* or get TB if no PURR */      \
-END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
-        ld      rb,PACA_STARTPURR(r13);                                 \
-        std     ra,PACA_STARTPURR(r13);                                 \
+        MFTB(ra);                       /* get timebase */              \
+        ld      rb,PACA_STARTTIME_USER(r13);                            \
+        std     ra,PACA_STARTTIME(r13);                                 \
         subf    rb,rb,ra;               /* subtract start value */      \
         ld      ra,PACA_USER_TIME(r13);                                 \
         add     ra,ra,rb;               /* add on to user time */       \
@@ -44,19 +41,34 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 2:
 
 #define ACCOUNT_CPU_USER_EXIT(ra, rb)                                   \
-BEGIN_FTR_SECTION;                                                      \
-        mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
-END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
-BEGIN_FTR_SECTION;                                                      \
-        MFTB(ra);                       /* or get TB if no PURR */      \
-END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
-        ld      rb,PACA_STARTPURR(r13);                                 \
-        std     ra,PACA_STARTPURR(r13);                                 \
+        MFTB(ra);                       /* get timebase */              \
+        ld      rb,PACA_STARTTIME(r13);                                 \
+        std     ra,PACA_STARTTIME_USER(r13);                            \
         subf    rb,rb,ra;               /* subtract start value */      \
         ld      ra,PACA_SYSTEM_TIME(r13);                               \
-        add     ra,ra,rb;               /* add on to user time */       \
-        std     ra,PACA_SYSTEM_TIME(r13);
-#endif
+        add     ra,ra,rb;               /* add on to system time */     \
+        std     ra,PACA_SYSTEM_TIME(r13)
+
+#ifdef CONFIG_PPC_SPLPAR
+#define ACCOUNT_STOLEN_TIME                                             \
+BEGIN_FW_FTR_SECTION;                                                   \
+        beq     33f;                                                    \
+        /* from user - see if there are any DTL entries to process */   \
+        ld      r10,PACALPPACAPTR(r13); /* get ptr to VPA */            \
+        ld      r11,PACA_DTL_RIDX(r13); /* get log read index */        \
+        ld      r10,LPPACA_DTLIDX(r10); /* get log write index */       \
+        cmpd    cr1,r11,r10;                                            \
+        beq+    cr1,33f;                                                \
+        bl      .accumulate_stolen_time;                                \
+33:                                                                     \
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
+
+#else  /* CONFIG_PPC_SPLPAR */
+#define ACCOUNT_STOLEN_TIME
+
+#endif /* CONFIG_PPC_SPLPAR */
+
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
 
 /*
  * Macros for storing registers into and loading registers from
@@ -158,6 +170,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 #define HMT_MEDIUM      or      2,2,2
 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 #define HMT_HIGH        or      3,3,3
+#define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 
 #ifdef __KERNEL__
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 19c05b0f74be..d50c2b6d9bc3 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -118,17 +118,16 @@ extern struct task_struct *last_task_used_spe;
 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
 
-#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
+#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
                 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 #endif
 
-#ifdef __KERNEL__
 #ifdef __powerpc64__
 
 #define STACK_TOP_USER64 TASK_SIZE_USER64
 #define STACK_TOP_USER32 TASK_SIZE_USER32
 
-#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
+#define STACK_TOP (is_32bit_task() ? \
                    STACK_TOP_USER32 : STACK_TOP_USER64)
 
 #define STACK_TOP_MAX STACK_TOP_USER64
@@ -139,7 +138,6 @@ extern struct task_struct *last_task_used_spe;
 #define STACK_TOP_MAX   STACK_TOP
 
 #endif /* __powerpc64__ */
-#endif /* __KERNEL__ */
 
 typedef struct {
         unsigned long seg;
@@ -240,6 +238,10 @@ struct thread_struct {
 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
         void*           kvm_shadow_vcpu; /* KVM internal data */
 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
+#ifdef CONFIG_PPC64
+        unsigned long   dscr;
+        int             dscr_inherit;
+#endif
 };
 
 #define ARCH_MIN_TASKALIGN 16
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index ae26f2efd089..c189aa5fe1f4 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -42,7 +42,7 @@ extern void pci_create_OF_bus_map(void);
 
 /* Translate a DMA address from device space to CPU space */
 extern u64 of_translate_dma_address(struct device_node *dev,
-                                    const u32 *in_addr);
+                                    const __be32 *in_addr);
 
 #ifdef CONFIG_PCI
 extern unsigned long pci_address_to_pio(phys_addr_t address);
@@ -63,9 +63,6 @@ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
 /* cache lookup */
 struct device_node *of_find_next_cache_node(struct device_node *np);
 
-/* Get the MAC address */
-extern const void *of_get_mac_address(struct device_node *np);
-
 #ifdef CONFIG_NUMA
 extern int of_node_to_nid(struct device_node *device);
 #else
@@ -73,21 +70,6 @@ static inline int of_node_to_nid(struct device_node *device) { return 0; }
 #endif
 #define of_node_to_nid of_node_to_nid
 
-/**
- * of_irq_map_pci - Resolve the interrupt for a PCI device
- * @pdev:       the device whose interrupt is to be resolved
- * @out_irq:    structure of_irq filled by this function
- *
- * This function resolves the PCI interrupt for a given PCI device. If a
- * device-node exists for a given pci_dev, it will use normal OF tree
- * walking. If not, it will implement standard swizzling and walk up the
- * PCI tree until an device-node is found, at which point it will finish
- * resolving using the OF tree walking.
- */
-struct pci_dev;
-struct of_irq;
-extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
-
 extern void of_instantiate_rtc(void);
 
 /* These includes are put at the bottom because they may contain things
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index f2b370180a09..8d1569c29042 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -86,7 +86,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 #define PTE_RPN_MASK    (~((1UL<<PTE_RPN_SHIFT)-1))
 #endif
 
-/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
+/* _PAGE_CHG_MASK masks of bits that are to be preserved across
  * pgprot changes
  */
 #define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
@@ -162,7 +162,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
  * on platforms where such control is possible.
  */
 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
-        defined(CONFIG_KPROBES)
+        defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_X
 #else
 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_ROX
@@ -171,6 +171,13 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 /* Make modules code happy. We don't set RO yet */
 #define PAGE_KERNEL_EXEC        PAGE_KERNEL_X
 
+/*
+ * Don't just check for any non zero bits in __PAGE_USER, since for book3e
+ * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
+ * _PAGE_USER.  Need to explicitly match _PAGE_BAP_UR bit in that case too.
+ */
+#define pte_user(val)           ((val & _PAGE_USER) == _PAGE_USER)
+
 /* Advertise special mapping type for AGP */
 #define PAGE_AGP                (PAGE_KERNEL_NC)
 #define HAVE_PAGE_AGP
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index c4490f9c67c4..59247e816ac5 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -22,7 +22,7 @@
 #define _PAGE_HASHPTE   _PAGE_HPTE_SUB
 
 /* Note the full page bits must be in the same location as for normal
- * 4k pages as the same asssembly will be used to insert 64K pages
+ * 4k pages as the same assembly will be used to insert 64K pages
  * wether the kernel has CONFIG_PPC_64K_PAGES or not
  */
 #define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 0175a676b34b..48223f9b8728 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -125,8 +125,10 @@ extern int ptrace_put_reg(struct task_struct *task, int regno,
 #endif /* ! __powerpc64__ */
 #define TRAP(regs)              ((regs)->trap & ~0xF)
 #ifdef __powerpc64__
+#define NV_REG_POISON           0xdeadbeefdeadbeefUL
 #define CHECK_FULL_REGS(regs)   BUG_ON(regs->trap & 1)
 #else
+#define NV_REG_POISON           0xdeadbeef
 #define CHECK_FULL_REGS(regs)                                                 \
 do {                                                                          \
         if ((regs)->trap & 1)                                                 \
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h
index cf519663a791..f706164b0bd0 100644
--- a/arch/powerpc/include/asm/qe_ic.h
+++ b/arch/powerpc/include/asm/qe_ic.h
@@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
 static inline void qe_ic_cascade_low_ipic(unsigned int irq,
                                           struct irq_desc *desc)
 {
-        struct qe_ic *qe_ic = desc->handler_data;
+        struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 
         if (cascade_irq != NO_IRQ)
@@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq,
 static inline void qe_ic_cascade_high_ipic(unsigned int irq,
                                            struct irq_desc *desc)
 {
-        struct qe_ic *qe_ic = desc->handler_data;
+        struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 
         if (cascade_irq != NO_IRQ)
@@ -101,32 +101,35 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq,
 static inline void qe_ic_cascade_low_mpic(unsigned int irq,
                                           struct irq_desc *desc)
 {
-        struct qe_ic *qe_ic = desc->handler_data;
+        struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
         if (cascade_irq != NO_IRQ)
                 generic_handle_irq(cascade_irq);
 
-        desc->chip->eoi(irq);
+        chip->irq_eoi(&desc->irq_data);
 }
 
 static inline void qe_ic_cascade_high_mpic(unsigned int irq,
                                            struct irq_desc *desc)
 {
-        struct qe_ic *qe_ic = desc->handler_data;
+        struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
         if (cascade_irq != NO_IRQ)
                 generic_handle_irq(cascade_irq);
 
-        desc->chip->eoi(irq);
+        chip->irq_eoi(&desc->irq_data);
 }
 
 static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
                                             struct irq_desc *desc)
 {
-        struct qe_ic *qe_ic = desc->handler_data;
+        struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
         cascade_irq = qe_ic_get_high_irq(qe_ic);
         if (cascade_irq == NO_IRQ)
@@ -135,7 +138,7 @@ static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
         if (cascade_irq != NO_IRQ)
                 generic_handle_irq(cascade_irq);
 
-        desc->chip->eoi(irq);
+        chip->irq_eoi(&desc->irq_data);
 }
 
 #endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index ff0005eec7dd..c5cae0dd176c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -99,17 +99,23 @@
 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
 
 #if defined(CONFIG_PPC_BOOK3S_64)
+#define MSR_64BIT       MSR_SF
+
 /* Server variant */
 #define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
-#define MSR_KERNEL      MSR_ | MSR_SF
+#define MSR_KERNEL      MSR_ | MSR_64BIT
 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64      MSR_USER32 | MSR_SF
+#define MSR_USER64      MSR_USER32 | MSR_64BIT
 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
 /* Default MSR for kernel mode. */
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 #endif
 
+#ifndef MSR_64BIT
+#define MSR_64BIT       0
+#endif
+
 /* Floating Point Status and Control Register (FPSCR) Fields */
 #define FPSCR_FX        0x80000000      /* FPU exception summary */
 #define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
@@ -170,8 +176,20 @@
 #define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
 
 /* Special Purpose Registers (SPRNs)*/
+
+#ifdef CONFIG_40x
+#define SPRN_PID        0x3B1   /* Process ID */
+#else
+#define SPRN_PID        0x030   /* Process ID */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
+#endif
+#endif
+
 #define SPRN_CTR        0x009   /* Count Register */
 #define SPRN_DSCR       0x11
+#define SPRN_CFAR       0x1c    /* Come From Address Register */
+#define SPRN_ACOP       0x1F    /* Available Coprocessor Register */
 #define SPRN_CTRLF      0x088
 #define SPRN_CTRLT      0x098
 #define   CTRL_CT       0xc0000000      /* current thread */
@@ -200,8 +218,43 @@
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
 #define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
 #define SPRN_SPURR      0x134   /* Scaled PURR */
+#define SPRN_HSPRG0     0x130   /* Hypervisor Scratch 0 */
+#define SPRN_HSPRG1     0x131   /* Hypervisor Scratch 1 */
+#define SPRN_HDSISR     0x132
+#define SPRN_HDAR       0x133
+#define SPRN_HDEC       0x136   /* Hypervisor Decrementer */
 #define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
+#define SPRN_RMOR       0x138   /* Real mode offset register */
+#define SPRN_HRMOR      0x139   /* Real mode offset register */
+#define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
+#define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_LPCR       0x13E   /* LPAR Control Register */
+#define   LPCR_VPM0     (1ul << (63-0))
+#define   LPCR_VPM1     (1ul << (63-1))
+#define   LPCR_ISL      (1ul << (63-2))
+#define   LPCR_DPFD_SH  (63-11)
+#define   LPCR_VRMA_L   (1ul << (63-12))
+#define   LPCR_VRMA_LP0 (1ul << (63-15))
+#define   LPCR_VRMA_LP1 (1ul << (63-16))
+#define   LPCR_RMLS    0x1C000000      /* impl dependent rmo limit sel */
+#define   LPCR_ILE     0x02000000      /* !HV irqs set MSR:LE */
+#define   LPCR_PECE     0x00007000      /* powersave exit cause enable */
+#define     LPCR_PECE0  0x00004000      /* ext. exceptions can cause exit */
+#define     LPCR_PECE1  0x00002000      /* decrementer can cause exit */
+#define     LPCR_PECE2  0x00001000      /* machine check etc can cause exit */
+#define   LPCR_MER      0x00000800      /* Mediated External Exception */
+#define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */
+#define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
+#define   LPCR_RMI     0x00000002      /* real mode is cache inhibit */
+#define   LPCR_HDICE   0x00000001      /* Hyp Decr enable (HV,PR,EE) */
+#define SPRN_LPID       0x13F   /* Logical Partition Identifier */
+#define SPRN_HMER       0x150   /* Hardware m? error recovery */
+#define SPRN_HMEER      0x151   /* Hardware m? enable error recovery */
+#define SPRN_HEIR       0x153   /* Hypervisor Emulated Instruction Register */
+#define SPRN_TLBINDEXR  0x154   /* P7 TLB control register */
+#define SPRN_TLBVPNR    0x155   /* P7 TLB control register */
+#define SPRN_TLBRPNR    0x156   /* P7 TLB control register */
+#define SPRN_TLBLPIDR   0x157   /* P7 TLB control register */
 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
 #define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
@@ -283,6 +336,7 @@
 #define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
 
 #define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
+#ifdef CONFIG_6xx
 #define HID1_EMCP       (1<<31)         /* 7450 Machine Check Pin Enable */
 #define HID1_DFS        (1<<22)         /* 7447A Dynamic Frequency Scaling */
 #define HID1_PC0        (1<<16)         /* 7450 PLL_CFG[0] */
@@ -292,6 +346,7 @@
 #define HID1_SYNCBE     (1<<11)         /* 7450 ABE for sync, eieio */
 #define HID1_ABE        (1<<10)         /* 7450 Address Broadcast Enable */
 #define HID1_PS         (1<<16)         /* 750FX PLL selection */
+#endif
 #define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
 #define SPRN_HID2_GEKKO 0x398           /* Gekko HID2 Register */
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
@@ -422,16 +477,23 @@
 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 #define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
-#define   SRR1_WAKERESET        0x00380000 /* System reset */
 #define   SRR1_WAKESYSERR       0x00300000 /* System error */
 #define   SRR1_WAKEEE           0x00200000 /* External interrupt */
 #define   SRR1_WAKEMT           0x00280000 /* mtctrl */
+#define   SRR1_WAKEHMI          0x00280000 /* Hypervisor maintenance */
 #define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
 #define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
+#define   SRR1_WAKERESET        0x00100000 /* System reset */
+#define   SRR1_WAKESTATE        0x00030000 /* Powersave exit mask [46:47] */
+#define   SRR1_WS_DEEPEST       0x00030000 /* Some resources not maintained,
+                                          * may not be recoverable */
+#define   SRR1_WS_DEEPER        0x00020000 /* Some resources not maintained */
+#define   SRR1_WS_DEEP          0x00010000 /* All resources maintained */
 #define   SRR1_PROGFPE          0x00100000 /* Floating Point Enabled */
 #define   SRR1_PROGPRIV         0x00040000 /* Privileged instruction */
 #define   SRR1_PROGTRAP         0x00020000 /* Trap */
 #define   SRR1_PROGADDR         0x00010000 /* SRR0 contains subsequent addr */
+
 #define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
 
@@ -661,12 +723,15 @@
  * SPRG usage:
  *
  * All 64-bit:
- *      - SPRG1 stores PACA pointer
+ *      - SPRG1 stores PACA pointer except 64-bit server in
+ *        HV mode in which case it is HSPRG0
  *
  * 64-bit server:
  *      - SPRG0 unused (reserved for HV on Power4)
  *      - SPRG2 scratch for exception vectors
  *      - SPRG3 unused (user visible)
+ *      - HSPRG0 stores PACA in HV mode
+ *      - HSPRG1 scratch for "HV" exceptions
  *
  * 64-bit embedded
  *      - SPRG0 generic exception scratch
@@ -729,6 +794,41 @@
 
 #ifdef CONFIG_PPC_BOOK3S_64
 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
+#define SPRN_SPRG_HPACA         SPRN_HSPRG0
+#define SPRN_SPRG_HSCRATCH0     SPRN_HSPRG1
+
+#define GET_PACA(rX)                                    \
+        BEGIN_FTR_SECTION_NESTED(66);                   \
+        mfspr   rX,SPRN_SPRG_PACA;                      \
+        FTR_SECTION_ELSE_NESTED(66);                    \
+        mfspr   rX,SPRN_SPRG_HPACA;                     \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
+
+#define SET_PACA(rX)                                    \
+        BEGIN_FTR_SECTION_NESTED(66);                   \
+        mtspr   SPRN_SPRG_PACA,rX;                      \
+        FTR_SECTION_ELSE_NESTED(66);                    \
+        mtspr   SPRN_SPRG_HPACA,rX;                     \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
+
+#define GET_SCRATCH0(rX)                                \
+        BEGIN_FTR_SECTION_NESTED(66);                   \
+        mfspr   rX,SPRN_SPRG_SCRATCH0;                  \
+        FTR_SECTION_ELSE_NESTED(66);                    \
+        mfspr   rX,SPRN_SPRG_HSCRATCH0;                 \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
+
+#define SET_SCRATCH0(rX)                                \
+        BEGIN_FTR_SECTION_NESTED(66);                   \
+        mtspr   SPRN_SPRG_SCRATCH0,rX;                  \
+        FTR_SECTION_ELSE_NESTED(66);                    \
+        mtspr   SPRN_SPRG_HSCRATCH0,rX;                 \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
+
+#else /* CONFIG_PPC_BOOK3S_64 */
+#define GET_SCRATCH0(rX)        mfspr   rX,SPRN_SPRG_SCRATCH0
+#define SET_SCRATCH0(rX)        mtspr   SPRN_SPRG_SCRATCH0,rX
+
 #endif
 
 #ifdef CONFIG_PPC_BOOK3E_64
@@ -738,6 +838,10 @@
 #define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
 #define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
+
+#define SET_PACA(rX)    mtspr   SPRN_SPRG_PACA,rX
+#define GET_PACA(rX)    mfspr   rX,SPRN_SPRG_PACA
+
 #endif
 
 #ifdef CONFIG_PPC_BOOK3S_32
@@ -788,6 +892,8 @@
 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
 #endif
 
+
+
 /*
  * An mtfsf instruction with the L bit set. On CPUs that support this a
  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
@@ -850,6 +956,8 @@
 #define PVR_7450        0x80000000
 #define PVR_8540        0x80200000
 #define PVR_8560        0x80200000
+#define PVR_VER_E500V1  0x8020
+#define PVR_VER_E500V2  0x8021
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
@@ -878,7 +986,10 @@
 #define PV_970          0x0039
 #define PV_POWER5       0x003A
 #define PV_POWER5p      0x003B
+#define PV_POWER7       0x003F
 #define PV_970FX        0x003C
+#define PV_POWER6       0x003E
+#define PV_POWER7       0x003F
 #define PV_630          0x0040
 #define PV_630p 0x0041
 #define PV_970MP        0x0044
diff --git a/arch/powerpc/include/asm/reg_a2.h b/arch/powerpc/include/asm/reg_a2.h
new file mode 100644
index 000000000000..3d52a1132f3d
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_a2.h
@@ -0,0 +1,165 @@
+/*
+ *  Register definitions specific to the A2 core
+ *
+ *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_REG_A2_H__
+#define __ASM_POWERPC_REG_A2_H__
+
+#define SPRN_TENSR      0x1b5
+#define SPRN_TENS       0x1b6   /* Thread ENable Set */
+#define SPRN_TENC       0x1b7   /* Thread ENable Clear */
+
+#define SPRN_A2_CCR0    0x3f0   /* Core Configuration Register 0 */
+#define SPRN_A2_CCR1    0x3f1   /* Core Configuration Register 1 */
+#define SPRN_A2_CCR2    0x3f2   /* Core Configuration Register 2 */
+#define SPRN_MMUCR0     0x3fc   /* MMU Control Register 0 */
+#define SPRN_MMUCR1     0x3fd   /* MMU Control Register 1 */
+#define SPRN_MMUCR2     0x3fe   /* MMU Control Register 2 */
+#define SPRN_MMUCR3     0x3ff   /* MMU Control Register 3 */
+
+#define SPRN_IAR        0x372
+
+#define SPRN_IUCR0      0x3f3
+#define IUCR0_ICBI_ACK  0x1000
+
+#define SPRN_XUCR0      0x3f6   /* Execution Unit Config Register 0 */
+
+#define A2_IERAT_SIZE   16
+#define A2_DERAT_SIZE   32
+
+/* A2 MMUCR0 bits */
+#define MMUCR0_ECL      0x80000000      /* Extended Class for TLB fills */
+#define MMUCR0_TID_NZ   0x40000000      /* TID is non-zero */
+#define MMUCR0_TS       0x10000000      /* Translation space for TLB fills */
+#define MMUCR0_TGS      0x20000000      /* Guest space for TLB fills */
+#define MMUCR0_TLBSEL   0x0c000000      /* TLB or ERAT target for TLB fills */
+#define MMUCR0_TLBSEL_U 0x00000000      /*  TLBSEL = UTLB */
+#define MMUCR0_TLBSEL_I 0x08000000      /*  TLBSEL = I-ERAT */
+#define MMUCR0_TLBSEL_D 0x0c000000      /*  TLBSEL = D-ERAT */
+#define MMUCR0_LOCKSRSH 0x02000000      /* Use TLB lock on tlbsx. */
+#define MMUCR0_TID_MASK 0x000000ff      /* TID field */
+
+/* A2 MMUCR1 bits */
+#define MMUCR1_IRRE             0x80000000      /* I-ERAT round robin enable */
+#define MMUCR1_DRRE             0x40000000      /* D-ERAT round robin enable */
+#define MMUCR1_REE              0x20000000      /* Reference Exception Enable*/
+#define MMUCR1_CEE              0x10000000      /* Change exception enable */
+#define MMUCR1_CSINV_ALL        0x00000000      /* Inval ERAT on all CS evts */
+#define MMUCR1_CSINV_NISYNC     0x04000000      /* Inval ERAT on all ex isync*/
+#define MMUCR1_CSINV_NEVER      0x0c000000      /* Don't inval ERAT on CS */
+#define MMUCR1_ICTID            0x00080000      /* IERAT class field as TID */
+#define MMUCR1_ITTID            0x00040000      /* IERAT thdid field as TID */
+#define MMUCR1_DCTID            0x00020000      /* DERAT class field as TID */
+#define MMUCR1_DTTID            0x00010000      /* DERAT thdid field as TID */
+#define MMUCR1_DCCD             0x00008000      /* DERAT class ignore */
+#define MMUCR1_TLBWE_BINV       0x00004000      /* back invalidate on tlbwe */
+
+/* A2 MMUCR2 bits */
+#define MMUCR2_PSSEL_SHIFT      4
+
+/* A2 MMUCR3 bits */
+#define MMUCR3_THID             0x0000000f      /* Thread ID */
+
+/* *** ERAT TLB bits definitions */
+#define TLB0_EPN_MASK           ASM_CONST(0xfffffffffffff000)
+#define TLB0_CLASS_MASK         ASM_CONST(0x0000000000000c00)
+#define TLB0_CLASS_00           ASM_CONST(0x0000000000000000)
+#define TLB0_CLASS_01           ASM_CONST(0x0000000000000400)
+#define TLB0_CLASS_10           ASM_CONST(0x0000000000000800)
+#define TLB0_CLASS_11           ASM_CONST(0x0000000000000c00)
+#define TLB0_V                  ASM_CONST(0x0000000000000200)
+#define TLB0_X                  ASM_CONST(0x0000000000000100)
+#define TLB0_SIZE_MASK          ASM_CONST(0x00000000000000f0)
+#define TLB0_SIZE_4K            ASM_CONST(0x0000000000000010)
+#define TLB0_SIZE_64K           ASM_CONST(0x0000000000000030)
+#define TLB0_SIZE_1M            ASM_CONST(0x0000000000000050)
+#define TLB0_SIZE_16M           ASM_CONST(0x0000000000000070)
+#define TLB0_SIZE_1G            ASM_CONST(0x00000000000000a0)
+#define TLB0_THDID_MASK         ASM_CONST(0x000000000000000f)
+#define TLB0_THDID_0            ASM_CONST(0x0000000000000001)
+#define TLB0_THDID_1            ASM_CONST(0x0000000000000002)
+#define TLB0_THDID_2            ASM_CONST(0x0000000000000004)
+#define TLB0_THDID_3            ASM_CONST(0x0000000000000008)
+#define TLB0_THDID_ALL          ASM_CONST(0x000000000000000f)
+
+#define TLB1_RESVATTR           ASM_CONST(0x00f0000000000000)
+#define TLB1_U0                 ASM_CONST(0x0008000000000000)
+#define TLB1_U1                 ASM_CONST(0x0004000000000000)
+#define TLB1_U2                 ASM_CONST(0x0002000000000000)
+#define TLB1_U3                 ASM_CONST(0x0001000000000000)
+#define TLB1_R                  ASM_CONST(0x0000800000000000)
+#define TLB1_C                  ASM_CONST(0x0000400000000000)
+#define TLB1_RPN_MASK           ASM_CONST(0x000003fffffff000)
+#define TLB1_W                  ASM_CONST(0x0000000000000800)
+#define TLB1_I                  ASM_CONST(0x0000000000000400)
+#define TLB1_M                  ASM_CONST(0x0000000000000200)
+#define TLB1_G                  ASM_CONST(0x0000000000000100)
+#define TLB1_E                  ASM_CONST(0x0000000000000080)
+#define TLB1_VF                 ASM_CONST(0x0000000000000040)
+#define TLB1_UX                 ASM_CONST(0x0000000000000020)
+#define TLB1_SX                 ASM_CONST(0x0000000000000010)
+#define TLB1_UW                 ASM_CONST(0x0000000000000008)
+#define TLB1_SW                 ASM_CONST(0x0000000000000004)
+#define TLB1_UR                 ASM_CONST(0x0000000000000002)
+#define TLB1_SR                 ASM_CONST(0x0000000000000001)
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
+#define WSP_UART_PHYS   0xffc000c000
+/* This needs to be careful chosen to hit a !0 congruence class
+ * in the TLB since we bolt it in way 3, which is already occupied
+ * by our linear mapping primary bolted entry in CC 0.
+ */
+#define WSP_UART_VIRT   0xf000000000001000
+#endif
+
+/* A2 erativax attributes definitions */
+#define ERATIVAX_RS_IS_ALL              0x000
+#define ERATIVAX_RS_IS_TID              0x040
+#define ERATIVAX_RS_IS_CLASS            0x080
+#define ERATIVAX_RS_IS_FULLMATCH        0x0c0
+#define ERATIVAX_CLASS_00               0x000
+#define ERATIVAX_CLASS_01               0x010
+#define ERATIVAX_CLASS_10               0x020
+#define ERATIVAX_CLASS_11               0x030
+#define ERATIVAX_PSIZE_4K               (TLB_PSIZE_4K >> 1)
+#define ERATIVAX_PSIZE_64K              (TLB_PSIZE_64K >> 1)
+#define ERATIVAX_PSIZE_1M               (TLB_PSIZE_1M >> 1)
+#define ERATIVAX_PSIZE_16M              (TLB_PSIZE_16M >> 1)
+#define ERATIVAX_PSIZE_1G               (TLB_PSIZE_1G >> 1)
+
+/* A2 eratilx attributes definitions */
+#define ERATILX_T_ALL                   0
+#define ERATILX_T_TID                   1
+#define ERATILX_T_TGS                   2
+#define ERATILX_T_FULLMATCH             3
+#define ERATILX_T_CLASS0                4
+#define ERATILX_T_CLASS1                5
+#define ERATILX_T_CLASS2                6
+#define ERATILX_T_CLASS3                7
+
+/* XUCR0 bits */
+#define XUCR0_TRACE_UM_T0               0x40000000      /* Thread 0 */
+#define XUCR0_TRACE_UM_T1               0x20000000      /* Thread 1 */
+#define XUCR0_TRACE_UM_T2               0x10000000      /* Thread 2 */
+#define XUCR0_TRACE_UM_T3               0x08000000      /* Thread 3 */
+
+/* A2 CCR0 register */
+#define A2_CCR0_PME_DISABLED            0x00000000
+#define A2_CCR0_PME_SLEEP               0x40000000
+#define A2_CCR0_PME_RVW                 0x80000000
+#define A2_CCR0_PME_DISABLED2           0xc0000000
+
+/* A2 CCR2 register */
+#define A2_CCR2_ERAT_ONLY_MODE          0x00000001
+#define A2_CCR2_ENABLE_ICSWX            0x00000002
+#define A2_CCR2_ENABLE_PC               0x20000000
+#define A2_CCR2_ENABLE_TRACE            0x40000000
+
+#endif /* __ASM_POWERPC_REG_A2_H__ */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 667a498eaee1..0f0ad9fa01c1 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -2,7 +2,7 @@
  * Contains register definitions common to the Book E PowerPC
  * specification.  Notice that while the IBM-40x series of CPUs
  * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well.  Unfortunatly,
+ * before Book E was finalized, and are included here as well.  Unfortunately,
  * they sometimes used different locations than true Book E CPUs did.
  *
  * This program is free software; you can redistribute it and/or
@@ -27,10 +27,12 @@
 #define MSR_CM          (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
 
 #if defined(CONFIG_PPC_BOOK3E_64)
+#define MSR_64BIT       MSR_CM
+
 #define MSR_            MSR_ME | MSR_CE
-#define MSR_KERNEL      MSR_ | MSR_CM
+#define MSR_KERNEL      MSR_ | MSR_64BIT
 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE | MSR_DE
-#define MSR_USER64      MSR_USER32 | MSR_CM | MSR_DE
+#define MSR_USER64      MSR_USER32 | MSR_64BIT
 #elif defined (CONFIG_40x)
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
@@ -81,6 +83,10 @@
 #define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
 #define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
 #define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
+#define SPRN_IVOR38     0x1B0   /* Interrupt Vector Offset Register 38 */
+#define SPRN_IVOR39     0x1B1   /* Interrupt Vector Offset Register 39 */
+#define SPRN_IVOR40     0x1B2   /* Interrupt Vector Offset Register 40 */
+#define SPRN_IVOR41     0x1B3   /* Interrupt Vector Offset Register 41 */
 #define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
 #define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
@@ -110,7 +116,7 @@
 #define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
 #define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
 #define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
-#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
+#define SPRN_MAS5       0x153   /* MMU Assist Register 5 */
 #define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 #define SPRN_PID2       0x27A   /* Process ID Register 2 */
@@ -150,8 +156,6 @@
  * or IBM 40x.
  */
 #ifdef CONFIG_BOOKE
-#define SPRN_PID        0x030   /* Process ID */
-#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
 #define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
 #define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
 #define SPRN_DEAR       0x03D   /* Data Error Address Register */
@@ -168,7 +172,6 @@
 #define SPRN_TCR        0x154   /* Timer Control Register */
 #endif /* Book E */
 #ifdef CONFIG_40x
-#define SPRN_PID        0x3B1   /* Process ID */
 #define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */          
 #define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 #define SPRN_DEAR       0x3D5   /* Data Error Address Register */
@@ -246,6 +249,20 @@
                                         store or cache line push */
 #endif
 
+/* Bit definitions for the HID1 */
+#ifdef CONFIG_E500
+/* e500v1/v2 */
+#define HID1_PLL_CFG_MASK 0xfc000000    /* PLL_CFG input pins */
+#define HID1_RFXE       0x00020000      /* Read fault exception enable */
+#define HID1_R1DPE      0x00008000      /* R1 data bus parity enable */
+#define HID1_R2DPE      0x00004000      /* R2 data bus parity enable */
+#define HID1_ASTME      0x00002000      /* Address bus streaming mode enable */
+#define HID1_ABE        0x00001000      /* Address broadcast enable */
+#define HID1_MPXTT      0x00000400      /* MPX re-map transfer type */
+#define HID1_ATS        0x00000080      /* Atomic status */
+#define HID1_MID_MASK   0x0000000f      /* MID input pins */
+#endif
+
 /* Bit definitions for the DBSR. */
 /*
  * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
index 0018bf80cb25..b1d2deceeedb 100644
--- a/arch/powerpc/include/asm/rio.h
+++ b/arch/powerpc/include/asm/rio.h
@@ -14,5 +14,10 @@
 #define ASM_PPC_RIO_H
 
 extern void platform_rio_init(void);
+#ifdef CONFIG_FSL_RIO
+extern int fsl_rio_mcheck_exception(struct pt_regs *);
+#else
+static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }
+#endif
 
 #endif                          /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 3d35f8ae377e..58625d1e7802 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -158,7 +158,50 @@ struct rtas_error_log {
         unsigned long target:4;                 /* Target of failed operation */
         unsigned long type:8;                   /* General event or error*/
         unsigned long extended_log_length:32;   /* length in bytes */
-        unsigned char buffer[1];
+        unsigned char buffer[1];                /* Start of extended log */
+                                                /* Variable length.      */
+};
+
+#define RTAS_V6EXT_LOG_FORMAT_EVENT_LOG 14
+
+#define RTAS_V6EXT_COMPANY_ID_IBM       (('I' << 24) | ('B' << 16) | ('M' << 8))
+
+/* RTAS general extended event log, Version 6. The extended log starts
+ * from "buffer" field of struct rtas_error_log defined above.
+ */
+struct rtas_ext_event_log_v6 {
+        /* Byte 0 */
+        uint32_t log_valid:1;           /* 1:Log valid */
+        uint32_t unrecoverable_error:1; /* 1:Unrecoverable error */
+        uint32_t recoverable_error:1;   /* 1:recoverable (correctable   */
+                                        /*   or successfully retried)   */
+        uint32_t degraded_operation:1;  /* 1:Unrecoverable err, bypassed*/
+                                        /*   - degraded operation (e.g. */
+                                        /*   CPU or mem taken off-line) */
+        uint32_t predictive_error:1;
+        uint32_t new_log:1;             /* 1:"New" log (Always 1 for    */
+                                        /*   data returned from RTAS    */
+        uint32_t big_endian:1;          /* 1: Big endian */
+        uint32_t :1;                    /* reserved */
+        /* Byte 1 */
+        uint32_t :8;                    /* reserved */
+        /* Byte 2 */
+        uint32_t powerpc_format:1;      /* Set to 1 (indicating log is  */
+                                        /* in PowerPC format            */
+        uint32_t :3;                    /* reserved */
+        uint32_t log_format:4;          /* Log format indicator. Define */
+                                        /* format used for byte 12-2047 */
+        /* Byte 3 */
+        uint32_t :8;                    /* reserved */
+        /* Byte 4-11 */
+        uint8_t reserved[8];            /* reserved */
+        /* Byte 12-15 */
+        uint32_t company_id;            /* Company ID of the company    */
+                                        /* that defines the format for  */
+                                        /* the vendor specific log type */
+        /* Byte 16-end of log */
+        uint8_t vendor_log[1];          /* Start of vendor specific log */
+                                        /* Variable length.             */
 };
 
 /*
@@ -187,6 +230,7 @@ extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
 extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
 extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
+extern int rtas_ibm_suspend_me(struct rtas_args *);
 
 struct rtc_time;
 extern unsigned long rtas_get_boot_time(void);
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
index 8447d89fbe72..bb1e2cdeb9bf 100644
--- a/arch/powerpc/include/asm/rwsem.h
+++ b/arch/powerpc/include/asm/rwsem.h
@@ -13,11 +13,6 @@
  * by Paul Mackerras <paulus@samba.org>.
  */
 
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <asm/atomic.h>
-#include <asm/system.h>
-
 /*
  * the semaphore definition
  */
@@ -33,47 +28,6 @@
 #define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
 
-struct rw_semaphore {
-        long                    count;
-        spinlock_t              wait_lock;
-        struct list_head        wait_list;
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-        struct lockdep_map      dep_map;
-#endif
-};
-
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
-#else
-# define __RWSEM_DEP_MAP_INIT(lockname)
-#endif
-
-#define __RWSEM_INITIALIZER(name)                               \
-{                                                               \
-        RWSEM_UNLOCKED_VALUE,                                   \
-        __SPIN_LOCK_UNLOCKED((name).wait_lock),                 \
-        LIST_HEAD_INIT((name).wait_list)                        \
-        __RWSEM_DEP_MAP_INIT(name)                              \
-}
-
-#define DECLARE_RWSEM(name)             \
-        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-
-extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
-                         struct lock_class_key *key);
-
-#define init_rwsem(sem)                                 \
-        do {                                            \
-                static struct lock_class_key __key;     \
-                                                        \
-                __init_rwsem((sem), #sem, &__key);      \
-        } while (0)
-
 /*
  * lock for reading
  */
@@ -174,10 +128,5 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
         return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
 }
 
-static inline int rwsem_is_locked(struct rw_semaphore *sem)
-{
-        return sem->count != 0;
-}
-
 #endif  /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/scom.h b/arch/powerpc/include/asm/scom.h
new file mode 100644
index 000000000000..0cabfd7bc2d1
--- /dev/null
+++ b/arch/powerpc/include/asm/scom.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2010 Benjamin Herrenschmidt, IBM Corp
+ *                <benh@kernel.crashing.org>
+ *     and        David Gibson, IBM Corporation.
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_SCOM_H
+#define _ASM_POWERPC_SCOM_H
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC_SCOM
+
+/*
+ * The SCOM bus is a sideband bus used for accessing various internal
+ * registers of the processor or the chipset. The implementation details
+ * differ between processors and platforms, and the access method as
+ * well.
+ *
+ * This API allows to "map" ranges of SCOM register numbers associated
+ * with a given SCOM controller. The later must be represented by a
+ * device node, though some implementations might support NULL if there
+ * is no possible ambiguity
+ *
+ * Then, scom_read/scom_write can be used to accesses registers inside
+ * that range. The argument passed is a register number relative to
+ * the beginning of the range mapped.
+ */
+
+typedef void *scom_map_t;
+
+/* Value for an invalid SCOM map */
+#define SCOM_MAP_INVALID        (NULL)
+
+/* The scom_controller data structure is what the platform passes
+ * to the core code in scom_init, it provides the actual implementation
+ * of all the SCOM functions
+ */
+struct scom_controller {
+        scom_map_t (*map)(struct device_node *ctrl_dev, u64 reg, u64 count);
+        void (*unmap)(scom_map_t map);
+
+        u64 (*read)(scom_map_t map, u32 reg);
+        void (*write)(scom_map_t map, u32 reg, u64 value);
+};
+
+extern const struct scom_controller *scom_controller;
+
+/**
+ * scom_init - Initialize the SCOM backend, called by the platform
+ * @controller: The platform SCOM controller
+ */
+static inline void scom_init(const struct scom_controller *controller)
+{
+        scom_controller = controller;
+}
+
+/**
+ * scom_map_ok - Test is a SCOM mapping is successful
+ * @map: The result of scom_map to test
+ */
+static inline int scom_map_ok(scom_map_t map)
+{
+        return map != SCOM_MAP_INVALID;
+}
+
+/**
+ * scom_map - Map a block of SCOM registers
+ * @ctrl_dev: Device node of the SCOM controller
+ *            some implementations allow NULL here
+ * @reg: first SCOM register to map
+ * @count: Number of SCOM registers to map
+ */
+
+static inline scom_map_t scom_map(struct device_node *ctrl_dev,
+                                  u64 reg, u64 count)
+{
+        return scom_controller->map(ctrl_dev, reg, count);
+}
+
+/**
+ * scom_find_parent - Find the SCOM controller for a device
+ * @dev: OF node of the device
+ *
+ * This is not meant for general usage, but in combination with
+ * scom_map() allows to map registers not represented by the
+ * device own scom-reg property. Useful for applying HW workarounds
+ * on things not properly represented in the device-tree for example.
+ */
+struct device_node *scom_find_parent(struct device_node *dev);
+
+
+/**
+ * scom_map_device - Map a device's block of SCOM registers
+ * @dev: OF node of the device
+ * @index: Register bank index (index in "scom-reg" property)
+ *
+ * This function will use the device-tree binding for SCOM which
+ * is to follow "scom-parent" properties until it finds a node with
+ * a "scom-controller" property to find the controller. It will then
+ * use the "scom-reg" property which is made of reg/count pairs,
+ * each of them having a size defined by the controller's #scom-cells
+ * property
+ */
+extern scom_map_t scom_map_device(struct device_node *dev, int index);
+
+
+/**
+ * scom_unmap - Unmap a block of SCOM registers
+ * @map: Result of scom_map is to be unmapped
+ */
+static inline void scom_unmap(scom_map_t map)
+{
+        if (scom_map_ok(map))
+                scom_controller->unmap(map);
+}
+
+/**
+ * scom_read - Read a SCOM register
+ * @map: Result of scom_map
+ * @reg: Register index within that map
+ */
+static inline u64 scom_read(scom_map_t map, u32 reg)
+{
+        return scom_controller->read(map, reg);
+}
+
+/**
+ * scom_write - Write to a SCOM register
+ * @map: Result of scom_map
+ * @reg: Register index within that map
+ * @value: Value to write
+ */
+static inline void scom_write(scom_map_t map, u32 reg, u64 value)
+{
+        scom_controller->write(map, reg, value);
+}
+
+#endif /* CONFIG_PPC_SCOM */
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SCOM_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 66e237bbe15f..11eb404b5606 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -20,6 +20,7 @@
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/kernel.h>
+#include <linux/irqreturn.h>
 
 #ifndef __ASSEMBLY__
 
@@ -29,22 +30,41 @@
 #include <asm/percpu.h>
 
 extern int boot_cpuid;
+extern int boot_cpu_count;
 
 extern void cpu_die(void);
 
 #ifdef CONFIG_SMP
 
-extern void smp_send_debugger_break(int cpu);
-extern void smp_message_recv(int);
+struct smp_ops_t {
+        void  (*message_pass)(int cpu, int msg);
+#ifdef CONFIG_PPC_SMP_MUXED_IPI
+        void  (*cause_ipi)(int cpu, unsigned long data);
+#endif
+        int   (*probe)(void);
+        int   (*kick_cpu)(int nr);
+        void  (*setup_cpu)(int nr);
+        void  (*bringup_done)(void);
+        void  (*take_timebase)(void);
+        void  (*give_timebase)(void);
+        int   (*cpu_disable)(void);
+        void  (*cpu_die)(unsigned int nr);
+        int   (*cpu_bootable)(unsigned int nr);
+};
+
+extern void smp_send_debugger_break(void);
+extern void start_secondary_resume(void);
+extern void __devinit smp_generic_give_timebase(void);
+extern void __devinit smp_generic_take_timebase(void);
 
 DECLARE_PER_CPU(unsigned int, cpu_pvr);
 
 #ifdef CONFIG_HOTPLUG_CPU
-extern void fixup_irqs(const struct cpumask *map);
+extern void migrate_irqs(void);
 int generic_cpu_disable(void);
-int generic_cpu_enable(unsigned int cpu);
 void generic_cpu_die(unsigned int cpu);
 void generic_mach_cpu_die(void);
+void generic_set_cpu_dead(unsigned int cpu);
 #endif
 
 #ifdef CONFIG_PPC64
@@ -92,13 +112,16 @@ extern int cpu_to_core_id(int cpu);
 #define PPC_MSG_CALL_FUNC_SINGLE        2
 #define PPC_MSG_DEBUGGER_BREAK  3
 
-/*
- * irq controllers that have dedicated ipis per message and don't
- * need additional code in the action handler may use this
- */
+/* for irq controllers that have dedicated ipis per message (4) */
 extern int smp_request_message_ipi(int virq, int message);
 extern const char *smp_ipi_name[];
 
+/* for irq controllers with only a single ipi */
+extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
+extern void smp_muxed_ipi_message_pass(int cpu, int msg);
+extern void smp_muxed_ipi_resend(void);
+extern irqreturn_t smp_ipi_demux(void);
+
 void smp_init_iSeries(void);
 void smp_init_pSeries(void);
 void smp_init_cell(void);
@@ -148,7 +171,7 @@ extern int smt_enabled_at_boot;
 
 extern int smp_mpic_probe(void);
 extern void smp_mpic_setup_cpu(int cpu);
-extern void smp_generic_kick_cpu(int nr);
+extern int smp_generic_kick_cpu(int nr);
 
 extern void smp_generic_give_timebase(void);
 extern void smp_generic_take_timebase(void);
diff --git a/arch/powerpc/include/asm/spu.h b/arch/powerpc/include/asm/spu.h
index 0ab8d869e3d6..0c8b35d75232 100644
--- a/arch/powerpc/include/asm/spu.h
+++ b/arch/powerpc/include/asm/spu.h
@@ -203,14 +203,6 @@ void spu_irq_setaffinity(struct spu *spu, int cpu);
 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
                 void *code, int code_size);
 
-#ifdef CONFIG_KEXEC
-void crash_register_spus(struct list_head *list);
-#else
-static inline void crash_register_spus(struct list_head *list)
-{
-}
-#endif
-
 extern void spu_invalidate_slbs(struct spu *spu);
 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
 int spu_64k_pages_available(void);
diff --git a/arch/powerpc/include/asm/spu_priv1.h b/arch/powerpc/include/asm/spu_priv1.h
index 25020a34ce7f..d8f5c60f61c1 100644
--- a/arch/powerpc/include/asm/spu_priv1.h
+++ b/arch/powerpc/include/asm/spu_priv1.h
@@ -223,7 +223,7 @@ spu_disable_spu (struct spu_context *ctx)
 }
 
 /*
- * The declarations folowing are put here for convenience
+ * The declarations following are put here for convenience
  * and only intended to be used by the platform setup code.
  */
 
diff --git a/arch/powerpc/include/asm/suspend.h b/arch/powerpc/include/asm/suspend.h
deleted file mode 100644
index c6efc3466aa6..000000000000
--- a/arch/powerpc/include/asm/suspend.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_POWERPC_SUSPEND_H
-#define __ASM_POWERPC_SUSPEND_H
-
-static inline int arch_prepare_suspend(void) { return 0; }
-
-#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h
index 23913e902fc3..b54b2add07be 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -15,6 +15,11 @@
 
 #include <linux/sched.h>
 
+/* ftrace syscalls requires exporting the sys_call_table */
+#ifdef CONFIG_FTRACE_SYSCALLS
+extern const unsigned long *sys_call_table;
+#endif /* CONFIG_FTRACE_SYSCALLS */
+
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
 {
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 3d212669a130..f6736b7da463 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -329,3 +329,28 @@ COMPAT_SYS(rt_tgsigqueueinfo)
 SYSCALL(fanotify_init)
 COMPAT_SYS(fanotify_mark)
 SYSCALL_SPU(prlimit64)
+SYSCALL_SPU(socket)
+SYSCALL_SPU(bind)
+SYSCALL_SPU(connect)
+SYSCALL_SPU(listen)
+SYSCALL_SPU(accept)
+SYSCALL_SPU(getsockname)
+SYSCALL_SPU(getpeername)
+SYSCALL_SPU(socketpair)
+SYSCALL_SPU(send)
+SYSCALL_SPU(sendto)
+COMPAT_SYS_SPU(recv)
+COMPAT_SYS_SPU(recvfrom)
+SYSCALL_SPU(shutdown)
+COMPAT_SYS_SPU(setsockopt)
+COMPAT_SYS_SPU(getsockopt)
+COMPAT_SYS_SPU(sendmsg)
+COMPAT_SYS_SPU(recvmsg)
+COMPAT_SYS_SPU(recvmmsg)
+SYSCALL_SPU(accept4)
+SYSCALL_SPU(name_to_handle_at)
+COMPAT_SYS_SPU(open_by_handle_at)
+COMPAT_SYS_SPU(clock_adjtime)
+SYSCALL_SPU(syncfs)
+COMPAT_SYS_SPU(sendmmsg)
+SYSCALL_SPU(setns)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index 6c294acac848..2dc595dda03b 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -154,8 +154,8 @@ extern void enable_kernel_spe(void);
 extern void giveup_spe(struct task_struct *);
 extern void load_up_spe(struct task_struct *);
 extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
-extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+extern void cvt_fd(float *from, double *to);
+extern void cvt_df(double *from, float *to);
 
 #ifndef CONFIG_SMP
 extern void discard_lazy_cpu_state(void);
@@ -219,8 +219,6 @@ extern int mem_init_done;	/* set on boot once kmalloc can be called */
 extern int init_bootmem_done;   /* set once bootmem is available */
 extern phys_addr_t memory_limit;
 extern unsigned long klimit;
-
-extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
@@ -542,10 +540,6 @@ extern void reloc_got2(unsigned long);
 
 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
-extern void account_system_vtime(struct task_struct *);
-#endif
-
 extern struct dentry *powerpc_debugfs_root;
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 65eb85976a03..836f231ec1f0 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -72,7 +72,7 @@ struct thread_info {
 
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
-extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
+extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
 extern void free_thread_info(struct thread_info *ti);
 
 #endif /* THREAD_SHIFT < PAGE_SHIFT */
@@ -110,7 +110,8 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NOERROR             12      /* Force successful syscall return */
 #define TIF_NOTIFY_RESUME       13      /* callback before returning to user */
 #define TIF_FREEZE              14      /* Freezing for suspend */
-#define TIF_RUNLATCH            15      /* Is the runlatch enabled? */
+#define TIF_SYSCALL_TRACEPOINT  15      /* syscall tracepoint instrumentation */
+#define TIF_RUNLATCH            16      /* Is the runlatch enabled? */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -127,8 +128,10 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NOERROR            (1<<TIF_NOERROR)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 #define _TIF_RUNLATCH           (1<<TIF_RUNLATCH)
-#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
+#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+                                 _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
                                  _TIF_NOTIFY_RESUME)
@@ -139,10 +142,12 @@ static inline struct thread_info *current_thread_info(void)
 #define TLF_NAPPING             0       /* idle thread enabled NAP mode */
 #define TLF_SLEEPING            1       /* suspend code enabled SLEEP mode */
 #define TLF_RESTORE_SIGMASK     2       /* Restore signal mask in do_signal */
+#define TLF_LAZY_MMU            3       /* tlb_batch is active */
 
 #define _TLF_NAPPING            (1 << TLF_NAPPING)
 #define _TLF_SLEEPING           (1 << TLF_SLEEPING)
 #define _TLF_RESTORE_SIGMASK    (1 << TLF_RESTORE_SIGMASK)
+#define _TLF_LAZY_MMU           (1 << TLF_LAZY_MMU)
 
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index dc779dfcf258..fe6f7c2c9c68 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -34,7 +34,6 @@ extern void to_tm(int tim, struct rtc_time * tm);
 extern void GregorianDay(struct rtc_time *tm);
 
 extern void generic_calibrate_decr(void);
-extern void snapshot_timebase(void);
 
 extern void set_dec_cpu6(unsigned int val);
 
@@ -212,12 +211,8 @@ struct cpu_usage {
 DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
 
 #if defined(CONFIG_VIRT_CPU_ACCOUNTING)
-extern void calculate_steal_time(void);
-extern void snapshot_timebases(void);
 #define account_process_vtime(tsk)              account_process_tick(tsk, 0)
 #else
-#define calculate_steal_time()                  do { } while (0)
-#define snapshot_timebases()                    do { } while (0)
 #define account_process_vtime(tsk)              do { } while (0)
 #endif
 
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index d50a380b2b6f..81143fcbd113 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -79,6 +79,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
 
 #elif defined(CONFIG_PPC_STD_MMU_64)
 
+#define MMU_NO_CONTEXT          0
+
 /*
  * TLB flushing for 64-bit hash-MMU CPUs
  */
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index afe4aaa65c3b..7ef0d90defc8 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -106,9 +106,22 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
                                                 int nid)
 {
 }
-
 #endif /* CONFIG_NUMA */
 
+#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
+extern int start_topology_update(void);
+extern int stop_topology_update(void);
+#else
+static inline int start_topology_update(void)
+{
+        return 0;
+}
+static inline int stop_topology_update(void)
+{
+        return 0;
+}
+#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
+
 #include <asm-generic/topology.h>
 
 #ifdef CONFIG_SMP
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index a5aea0ca34e9..8947b9827bc4 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -44,13 +44,6 @@ typedef struct {
 
 typedef __vector128 vector128;
 
-#if defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT)
-typedef u64 dma_addr_t;
-#else
-typedef u32 dma_addr_t;
-#endif
-typedef u64 dma64_addr_t;
-
 typedef struct {
         unsigned long entry;
         unsigned long toc;
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 11ae699135ba..58580e94a2bb 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -52,6 +52,7 @@ extern void __init udbg_init_44x_as1(void);
 extern void __init udbg_init_40x_realmode(void);
 extern void __init udbg_init_cpm(void);
 extern void __init udbg_init_usbgecko(void);
+extern void __init udbg_init_wsp(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index f737732c3861..d12b11d7641e 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
  *
  * Obviously, the GART is not cache coherent and so any change to it
  * must be flushed to memory (or maybe just make the GART space non
- * cachable). AGP memory itself doens't seem to be cache coherent neither.
+ * cachable). AGP memory itself doesn't seem to be cache coherent neither.
  *
  * In order to invalidate the GART (which is probably necessary to inval
  * the bridge internal TLBs), the following sequence has to be written,
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 597e6f9d094a..b8b3f599362b 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -348,10 +348,35 @@
 #define __NR_fanotify_init      323
 #define __NR_fanotify_mark      324
 #define __NR_prlimit64          325
+#define __NR_socket             326
+#define __NR_bind               327
+#define __NR_connect            328
+#define __NR_listen             329
+#define __NR_accept             330
+#define __NR_getsockname        331
+#define __NR_getpeername        332
+#define __NR_socketpair         333
+#define __NR_send               334
+#define __NR_sendto             335
+#define __NR_recv               336
+#define __NR_recvfrom           337
+#define __NR_shutdown           338
+#define __NR_setsockopt         339
+#define __NR_getsockopt         340
+#define __NR_sendmsg            341
+#define __NR_recvmsg            342
+#define __NR_recvmmsg           343
+#define __NR_accept4            344
+#define __NR_name_to_handle_at  345
+#define __NR_open_by_handle_at  346
+#define __NR_clock_adjtime      347
+#define __NR_syncfs             348
+#define __NR_sendmmsg           349
+#define __NR_setns              350
 
 #ifdef __KERNEL__
 
-#define __NR_syscalls           326
+#define __NR_syscalls           351
 
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 08679c5319b8..b73a8199f161 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -57,7 +57,7 @@ struct vdso_data {
         } version;
 
         /* Note about the platform flags: it now only contains the lpar
-         * bit. The actual platform number is dead and burried
+         * bit. The actual platform number is dead and buried
          */
         __u32 platform;                 /* Platform flags               0x18 */
         __u32 processor;                /* Processor type               0x1C */
@@ -116,9 +116,7 @@ struct vdso_data {
 
 #endif /* CONFIG_PPC64 */
 
-#ifdef __KERNEL__
 extern struct vdso_data *vdso_data;
-#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/include/asm/wsp.h b/arch/powerpc/include/asm/wsp.h
new file mode 100644
index 000000000000..c7dc83088a33
--- /dev/null
+++ b/arch/powerpc/include/asm/wsp.h
@@ -0,0 +1,14 @@
+/*
+ *  Copyright 2011 Michael Ellerman, IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_POWERPC_WSP_H
+#define __ASM_POWERPC_WSP_H
+
+extern int wsp_get_chip_id(struct device_node *dn);
+
+#endif /* __ASM_POWERPC_WSP_H */
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
new file mode 100644
index 000000000000..b183a4062011
--- /dev/null
+++ b/arch/powerpc/include/asm/xics.h
@@ -0,0 +1,142 @@
+/*
+ * Common definitions accross all variants of ICP and ICS interrupt
+ * controllers.
+ */
+
+#ifndef _XICS_H
+#define _XICS_H
+
+#include <linux/interrupt.h>
+
+#define XICS_IPI                2
+#define XICS_IRQ_SPURIOUS       0
+
+/* Want a priority other than 0.  Various HW issues require this. */
+#define DEFAULT_PRIORITY        5
+
+/*
+ * Mark IPIs as higher priority so we can take them inside interrupts that
+ * arent marked IRQF_DISABLED
+ */
+#define IPI_PRIORITY            4
+
+/* The least favored priority */
+#define LOWEST_PRIORITY         0xFF
+
+/* The number of priorities defined above */
+#define MAX_NUM_PRIORITIES      3
+
+/* Native ICP */
+extern int icp_native_init(void);
+
+/* PAPR ICP */
+extern int icp_hv_init(void);
+
+/* ICP ops */
+struct icp_ops {
+        unsigned int (*get_irq)(void);
+        void (*eoi)(struct irq_data *d);
+        void (*set_priority)(unsigned char prio);
+        void (*teardown_cpu)(void);
+        void (*flush_ipi)(void);
+#ifdef CONFIG_SMP
+        void (*cause_ipi)(int cpu, unsigned long data);
+        irq_handler_t ipi_action;
+#endif
+};
+
+extern const struct icp_ops *icp_ops;
+
+/* Native ICS */
+extern int ics_native_init(void);
+
+/* RTAS ICS */
+extern int ics_rtas_init(void);
+
+/* ICS instance, hooked up to chip_data of an irq */
+struct ics {
+        struct list_head link;
+        int (*map)(struct ics *ics, unsigned int virq);
+        void (*mask_unknown)(struct ics *ics, unsigned long vec);
+        long (*get_server)(struct ics *ics, unsigned long vec);
+        int (*host_match)(struct ics *ics, struct device_node *node);
+        char data[];
+};
+
+/* Commons */
+extern unsigned int xics_default_server;
+extern unsigned int xics_default_distrib_server;
+extern unsigned int xics_interrupt_server_size;
+extern struct irq_host *xics_host;
+
+struct xics_cppr {
+        unsigned char stack[MAX_NUM_PRIORITIES];
+        int index;
+};
+
+DECLARE_PER_CPU(struct xics_cppr, xics_cppr);
+
+static inline void xics_push_cppr(unsigned int vec)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
+                return;
+
+        if (vec == XICS_IPI)
+                os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
+        else
+                os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
+}
+
+static inline unsigned char xics_pop_cppr(void)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        if (WARN_ON(os_cppr->index < 1))
+                return LOWEST_PRIORITY;
+
+        return os_cppr->stack[--os_cppr->index];
+}
+
+static inline void xics_set_base_cppr(unsigned char cppr)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+
+        /* we only really want to set the priority when there's
+         * just one cppr value on the stack
+         */
+        WARN_ON(os_cppr->index != 0);
+
+        os_cppr->stack[0] = cppr;
+}
+
+static inline unsigned char xics_cppr_top(void)
+{
+        struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
+        
+        return os_cppr->stack[os_cppr->index];
+}
+
+DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
+
+extern void xics_init(void);
+extern void xics_setup_cpu(void);
+extern void xics_update_irq_servers(void);
+extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
+extern void xics_mask_unknown_vec(unsigned int vec);
+extern irqreturn_t xics_ipi_dispatch(int cpu);
+extern int xics_smp_probe(void);
+extern void xics_register_ics(struct ics *ics);
+extern void xics_teardown_cpu(void);
+extern void xics_kexec_teardown_cpu(int secondary);
+extern void xics_migrate_irqs_away(void);
+#ifdef CONFIG_SMP
+extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
+                               unsigned int strict_check);
+#else
+#define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server)
+#endif
+
+
+#endif /* _XICS_H */