powerpc/powernv: Fix endianness problems in EEH

EEH information fetched from OPAL need fix before using in LE environment.
To be included in sparse's endian check, declare them as __beXX and
access them by accessors.

Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>

Signed-off-by: Guo Chao <yan@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 51 insertions, 51 deletions

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index cb15cbb51600..460018889ba9 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -599,9 +599,9 @@ enum {
 };
 
 struct OpalIoPhbErrorCommon {
-        uint32_t version;
-        uint32_t ioType;
-        uint32_t len;
+        __be32 version;
+        __be32 ioType;
+        __be32 len;
 };
 
 struct OpalIoP7IOCPhbErrorData {
@@ -666,64 +666,64 @@ struct OpalIoP7IOCPhbErrorData {
 struct OpalIoPhb3ErrorData {
         struct OpalIoPhbErrorCommon common;
 
-        uint32_t brdgCtl;
+        __be32 brdgCtl;
 
         /* PHB3 UTL regs */
-        uint32_t portStatusReg;
-        uint32_t rootCmplxStatus;
-        uint32_t busAgentStatus;
+        __be32 portStatusReg;
+        __be32 rootCmplxStatus;
+        __be32 busAgentStatus;
 
         /* PHB3 cfg regs */
-        uint32_t deviceStatus;
-        uint32_t slotStatus;
-        uint32_t linkStatus;
-        uint32_t devCmdStatus;
-        uint32_t devSecStatus;
+        __be32 deviceStatus;
+        __be32 slotStatus;
+        __be32 linkStatus;
+        __be32 devCmdStatus;
+        __be32 devSecStatus;
 
         /* cfg AER regs */
-        uint32_t rootErrorStatus;
-        uint32_t uncorrErrorStatus;
-        uint32_t corrErrorStatus;
-        uint32_t tlpHdr1;
-        uint32_t tlpHdr2;
-        uint32_t tlpHdr3;
-        uint32_t tlpHdr4;
-        uint32_t sourceId;
+        __be32 rootErrorStatus;
+        __be32 uncorrErrorStatus;
+        __be32 corrErrorStatus;
+        __be32 tlpHdr1;
+        __be32 tlpHdr2;
+        __be32 tlpHdr3;
+        __be32 tlpHdr4;
+        __be32 sourceId;
 
-        uint32_t rsv3;
+        __be32 rsv3;
 
         /* Record data about the call to allocate a buffer */
-        uint64_t errorClass;
-        uint64_t correlator;
+        __be64 errorClass;
+        __be64 correlator;
 
-        uint64_t nFir;                  /* 000 */
-        uint64_t nFirMask;              /* 003 */
-        uint64_t nFirWOF;               /* 008 */
+        __be64 nFir;                    /* 000 */
+        __be64 nFirMask;                /* 003 */
+        __be64 nFirWOF;         /* 008 */
 
         /* PHB3 MMIO Error Regs */
-        uint64_t phbPlssr;              /* 120 */
-        uint64_t phbCsr;                /* 110 */
-        uint64_t lemFir;                /* C00 */
-        uint64_t lemErrorMask;          /* C18 */
-        uint64_t lemWOF;                /* C40 */
-        uint64_t phbErrorStatus;        /* C80 */
-        uint64_t phbFirstErrorStatus;   /* C88 */
-        uint64_t phbErrorLog0;          /* CC0 */
-        uint64_t phbErrorLog1;          /* CC8 */
-        uint64_t mmioErrorStatus;       /* D00 */
-        uint64_t mmioFirstErrorStatus;  /* D08 */
-        uint64_t mmioErrorLog0;         /* D40 */
-        uint64_t mmioErrorLog1;         /* D48 */
-        uint64_t dma0ErrorStatus;       /* D80 */
-        uint64_t dma0FirstErrorStatus;  /* D88 */
-        uint64_t dma0ErrorLog0;         /* DC0 */
-        uint64_t dma0ErrorLog1;         /* DC8 */
-        uint64_t dma1ErrorStatus;       /* E00 */
-        uint64_t dma1FirstErrorStatus;  /* E08 */
-        uint64_t dma1ErrorLog0;         /* E40 */
-        uint64_t dma1ErrorLog1;         /* E48 */
-        uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
-        uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
+        __be64 phbPlssr;                /* 120 */
+        __be64 phbCsr;          /* 110 */
+        __be64 lemFir;          /* C00 */
+        __be64 lemErrorMask;            /* C18 */
+        __be64 lemWOF;          /* C40 */
+        __be64 phbErrorStatus;  /* C80 */
+        __be64 phbFirstErrorStatus;     /* C88 */
+        __be64 phbErrorLog0;            /* CC0 */
+        __be64 phbErrorLog1;            /* CC8 */
+        __be64 mmioErrorStatus; /* D00 */
+        __be64 mmioFirstErrorStatus;    /* D08 */
+        __be64 mmioErrorLog0;           /* D40 */
+        __be64 mmioErrorLog1;           /* D48 */
+        __be64 dma0ErrorStatus; /* D80 */
+        __be64 dma0FirstErrorStatus;    /* D88 */
+        __be64 dma0ErrorLog0;           /* DC0 */
+        __be64 dma0ErrorLog1;           /* DC8 */
+        __be64 dma1ErrorStatus; /* E00 */
+        __be64 dma1FirstErrorStatus;    /* E08 */
+        __be64 dma1ErrorLog0;           /* E40 */
+        __be64 dma1ErrorLog1;           /* E48 */
+        __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
+        __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 };
 
 enum {
@@ -851,8 +851,8 @@ int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t erro
 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 int64_t opal_get_epow_status(__be64 *status);
 int64_t opal_set_system_attention_led(uint8_t led_action);
-int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
-                            uint16_t *pci_error_type, uint16_t *severity);
+int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
+                            __be16 *pci_error_type, __be16 *severity);
 int64_t opal_pci_poll(uint64_t phb_id);
 int64_t opal_return_cpu(void);
 int64_t opal_reinit_cpus(uint64_t flags);