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authorJimi Xenidis <jimix@pobox.com>2011-09-29 06:55:13 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-11-24 22:11:28 -0500
commitfac26ad4f9cb794c9d1032f55f40a31cb55be09a (patch)
tree6acb31ab3fbc959de6f62aa4dd6ea08c004205f4 /arch/powerpc/include/asm/reg_booke.h
parent9d670280908013004f173b2b86414d9b6918511b (diff)
powerpc/book3e: Add ICSWX/ACOP support to Book3e cores like A2
ICSWX is also used by the A2 processor to access coprocessors, although not all "chips" that contain A2s have coprocessors. Signed-off-by: Jimi Xenidis <jimix@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
-rw-r--r--arch/powerpc/include/asm/reg_booke.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 03c48e819c8e..500fe1dc43e6 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
188#endif 188#endif
189 189
190#ifdef CONFIG_PPC_ICSWX
191#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
192#endif
193
190/* Bit definitions for CCR1. */ 194/* Bit definitions for CCR1. */
191#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 195#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
192#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 196#define CCR1_TCS 0x00000080 /* Timer Clock Select */