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authorKumar Gala <galak@kernel.crashing.org>2009-08-18 15:08:33 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-28 00:24:14 -0400
commitbb1af71ecbfdbecbe9f7e43f703da5840b76c2e4 (patch)
tree91167c249090c0636d56316afb08ca56f51bdfc8 /arch/powerpc/include/asm/reg_booke.h
parent4b98d9e713a03bd79ced8800e24a56359f9effbf (diff)
powerpc/book3e-64: Add support to initial_tlb_book3e for non-HES TLB
We now search through TLBnCFG looking for the first array that has IPROT support (we assume that there is only one). If that TLB has hardware entry select (HES) support we use the existing code and with the proper TLB select (the HES code still needs to clean up bolted entries from firmware). The non-HES code is pretty similiar to the 32-bit FSL Book-E code but does make some new assumtions (like that we have tlbilx) and simplifies things down a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
-rw-r--r--arch/powerpc/include/asm/reg_booke.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 9bb81d99b765..3bf783505528 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -108,6 +108,8 @@
108#define SPRN_PID2 0x27A /* Process ID Register 2 */ 108#define SPRN_PID2 0x27A /* Process ID Register 2 */
109#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 109#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
110#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 110#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
111#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */
112#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */
111#define SPRN_EPR 0x2BE /* External Proxy Register */ 113#define SPRN_EPR 0x2BE /* External Proxy Register */
112#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 114#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
113#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 115#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */