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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-04-08 07:28:02 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-04-08 07:28:02 -0400
commitfe10739284bae68b57d3dbcad81f34772cfd2716 (patch)
tree896fa694b7f6a46266ff8eb5291c35781be53e25 /arch/powerpc/include/asm/reg.h
parent8c73c4d8319f38ec1a1fc630a88cbcb79cb1a8f6 (diff)
parentf334a1e8434c49b6f9c947d3eb7caf712fbcc3fa (diff)
Merge branch 'pm-cpufreq'
* pm-cpufreq: cpufreq: ppc: Remove duplicate inclusion of fsl_soc.h cpufreq: create another field .flags in cpufreq_frequency_table cpufreq: use kzalloc() to allocate memory for cpufreq_frequency_table cpufreq: don't print value of .driver_data from core cpufreq: ia64: don't set .driver_data to index cpufreq: powernv: Select CPUFreq related Kconfig options for powernv cpufreq: powernv: Use cpufreq_frequency_table.driver_data to store pstate ids cpufreq: powernv: cpufreq driver for powernv platform cpufreq: at32ap: don't declare local variable as static cpufreq: loongson2_cpufreq: don't declare local variable as static cpufreq: unicore32: fix typo issue for 'clk' cpufreq: exynos: Disable on multiplatform build
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
-rw-r--r--arch/powerpc/include/asm/reg.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 0dcc48af25a3..e5d2e0bc7e03 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -272,6 +272,10 @@
272#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 272#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
273#define SPRN_IC 0x350 /* Virtual Instruction Count */ 273#define SPRN_IC 0x350 /* Virtual Instruction Count */
274#define SPRN_VTB 0x351 /* Virtual Time Base */ 274#define SPRN_VTB 0x351 /* Virtual Time Base */
275#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
276#define SPRN_PMSR 0x355 /* Power Management Status Reg */
277#define SPRN_PMCR 0x374 /* Power Management Control Register */
278
275/* HFSCR and FSCR bit numbers are the same */ 279/* HFSCR and FSCR bit numbers are the same */
276#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 280#define FSCR_TAR_LG 8 /* Enable Target Address Register */
277#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 281#define FSCR_EBB_LG 7 /* Enable Event Based Branching */