powerpc/perf: Fix instruction address sampling on 970 and Power4

970 and Power4 don't support "continuous sampling" which means that
when we aren't in marked instruction sampling mode (marked events),
SIAR isn't updated with the last instruction sampled before the
perf interrupt. On those processors, we must thus use the exception
SRR0 value as the sampled instruction pointer.

Those processors also don't support the SIPR and SIHV bits in MMCRA
which means we need some kind of heuristic to decide if SIAR values
represent kernel or user addresses.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 1a8093fa8f71..078019b5b353 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -47,6 +47,8 @@ struct power_pmu {
  */
 #define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
+#define PPMU_NO_SIPR            4       /* no SIPR/HV in MMCRA at all */
+#define PPMU_NO_CONT_SAMPLING   8       /* no continuous sampling */
 
 /*
  * Values for flags to get_alternatives()