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authorStephen Rothwell <sfr@canb.auug.org.au>2008-08-01 01:20:30 -0400
committerPaul Mackerras <paulus@samba.org>2008-08-03 22:02:00 -0400
commitb8b572e1015f81b4e748417be2629dfe51ab99f9 (patch)
tree7df58667d5ed71d6c8f8f4ce40ca16b6fb776d0b /arch/powerpc/include/asm/immap_qe.h
parent2b12a4c524812fb3f6ee590a02e65b95c8c32229 (diff)
powerpc: Move include files to arch/powerpc/include/asm
from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/include/asm/immap_qe.h')
-rw-r--r--arch/powerpc/include/asm/immap_qe.h483
1 files changed, 483 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
new file mode 100644
index 000000000000..3c2fced3ac22
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -0,0 +1,483 @@
1/*
2 * QUICC Engine (QE) Internal Memory Map.
3 * The Internal Memory Map for devices with QE on them. This
4 * is the superset of all QE devices (8360, etc.).
5
6 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#ifndef _ASM_POWERPC_IMMAP_QE_H
17#define _ASM_POWERPC_IMMAP_QE_H
18#ifdef __KERNEL__
19
20#include <linux/kernel.h>
21#include <asm/io.h>
22
23#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
24
25/* QE I-RAM */
26struct qe_iram {
27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */
29 u8 res0[0x78];
30} __attribute__ ((packed));
31
32/* QE Interrupt Controller */
33struct qe_ic_regs {
34 __be32 qicr;
35 __be32 qivec;
36 __be32 qripnr;
37 __be32 qipnr;
38 __be32 qipxcc;
39 __be32 qipycc;
40 __be32 qipwcc;
41 __be32 qipzcc;
42 __be32 qimr;
43 __be32 qrimr;
44 __be32 qicnr;
45 u8 res0[0x4];
46 __be32 qiprta;
47 __be32 qiprtb;
48 u8 res1[0x4];
49 __be32 qricr;
50 u8 res2[0x20];
51 __be32 qhivec;
52 u8 res3[0x1C];
53} __attribute__ ((packed));
54
55/* Communications Processor */
56struct cp_qe {
57 __be32 cecr; /* QE command register */
58 __be32 ceccr; /* QE controller configuration register */
59 __be32 cecdr; /* QE command data register */
60 u8 res0[0xA];
61 __be16 ceter; /* QE timer event register */
62 u8 res1[0x2];
63 __be16 cetmr; /* QE timers mask register */
64 __be32 cetscr; /* QE time-stamp timer control register */
65 __be32 cetsr1; /* QE time-stamp register 1 */
66 __be32 cetsr2; /* QE time-stamp register 2 */
67 u8 res2[0x8];
68 __be32 cevter; /* QE virtual tasks event register */
69 __be32 cevtmr; /* QE virtual tasks mask register */
70 __be16 cercr; /* QE RAM control register */
71 u8 res3[0x2];
72 u8 res4[0x24];
73 __be16 ceexe1; /* QE external request 1 event register */
74 u8 res5[0x2];
75 __be16 ceexm1; /* QE external request 1 mask register */
76 u8 res6[0x2];
77 __be16 ceexe2; /* QE external request 2 event register */
78 u8 res7[0x2];
79 __be16 ceexm2; /* QE external request 2 mask register */
80 u8 res8[0x2];
81 __be16 ceexe3; /* QE external request 3 event register */
82 u8 res9[0x2];
83 __be16 ceexm3; /* QE external request 3 mask register */
84 u8 res10[0x2];
85 __be16 ceexe4; /* QE external request 4 event register */
86 u8 res11[0x2];
87 __be16 ceexm4; /* QE external request 4 mask register */
88 u8 res12[0x3A];
89 __be32 ceurnr; /* QE microcode revision number register */
90 u8 res13[0x244];
91} __attribute__ ((packed));
92
93/* QE Multiplexer */
94struct qe_mux {
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
100 __be32 cmxupcr; /* CMX UPC clock route register */
101 u8 res0[0x1C];
102} __attribute__ ((packed));
103
104/* QE Timers */
105struct qe_timers {
106 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
107 u8 res0[0x3];
108 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
109 u8 res1[0xB];
110 __be16 gtmdr1; /* Timer 1 mode register */
111 __be16 gtmdr2; /* Timer 2 mode register */
112 __be16 gtrfr1; /* Timer 1 reference register */
113 __be16 gtrfr2; /* Timer 2 reference register */
114 __be16 gtcpr1; /* Timer 1 capture register */
115 __be16 gtcpr2; /* Timer 2 capture register */
116 __be16 gtcnr1; /* Timer 1 counter */
117 __be16 gtcnr2; /* Timer 2 counter */
118 __be16 gtmdr3; /* Timer 3 mode register */
119 __be16 gtmdr4; /* Timer 4 mode register */
120 __be16 gtrfr3; /* Timer 3 reference register */
121 __be16 gtrfr4; /* Timer 4 reference register */
122 __be16 gtcpr3; /* Timer 3 capture register */
123 __be16 gtcpr4; /* Timer 4 capture register */
124 __be16 gtcnr3; /* Timer 3 counter */
125 __be16 gtcnr4; /* Timer 4 counter */
126 __be16 gtevr1; /* Timer 1 event register */
127 __be16 gtevr2; /* Timer 2 event register */
128 __be16 gtevr3; /* Timer 3 event register */
129 __be16 gtevr4; /* Timer 4 event register */
130 __be16 gtps; /* Timer 1 prescale register */
131 u8 res2[0x46];
132} __attribute__ ((packed));
133
134/* BRG */
135struct qe_brg {
136 __be32 brgc[16]; /* BRG configuration registers */
137 u8 res0[0x40];
138} __attribute__ ((packed));
139
140/* SPI */
141struct spi {
142 u8 res0[0x20];
143 __be32 spmode; /* SPI mode register */
144 u8 res1[0x2];
145 u8 spie; /* SPI event register */
146 u8 res2[0x1];
147 u8 res3[0x2];
148 u8 spim; /* SPI mask register */
149 u8 res4[0x1];
150 u8 res5[0x1];
151 u8 spcom; /* SPI command register */
152 u8 res6[0x2];
153 __be32 spitd; /* SPI transmit data register (cpu mode) */
154 __be32 spird; /* SPI receive data register (cpu mode) */
155 u8 res7[0x8];
156} __attribute__ ((packed));
157
158/* SI */
159struct si1 {
160 __be16 siamr1; /* SI1 TDMA mode register */
161 __be16 sibmr1; /* SI1 TDMB mode register */
162 __be16 sicmr1; /* SI1 TDMC mode register */
163 __be16 sidmr1; /* SI1 TDMD mode register */
164 u8 siglmr1_h; /* SI1 global mode register high */
165 u8 res0[0x1];
166 u8 sicmdr1_h; /* SI1 command register high */
167 u8 res2[0x1];
168 u8 sistr1_h; /* SI1 status register high */
169 u8 res3[0x1];
170 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
171 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
172 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
173 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
174 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
175 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
176 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
177 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
178 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
179 u8 res4[0x8];
180 __be16 siemr1; /* SI1 TDME mode register 16 bits */
181 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
182 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
183 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
184 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
185 u8 res5[0x1];
186 u8 sicmdr1_l; /* SI1 command register low 8 bits */
187 u8 res6[0x1];
188 u8 sistr1_l; /* SI1 status register low 8 bits */
189 u8 res7[0x1];
190 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
191 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
192 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
193 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
194 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
195 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
196 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
197 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
198 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
199 u8 res8[0x8];
200 __be32 siml1; /* SI1 multiframe limit register */
201 u8 siedm1; /* SI1 extended diagnostic mode register */
202 u8 res9[0xBB];
203} __attribute__ ((packed));
204
205/* SI Routing Tables */
206struct sir {
207 u8 tx[0x400];
208 u8 rx[0x400];
209 u8 res0[0x800];
210} __attribute__ ((packed));
211
212/* USB Controller */
213struct usb_ctlr {
214 u8 usb_usmod;
215 u8 usb_usadr;
216 u8 usb_uscom;
217 u8 res1[1];
218 __be16 usb_usep1;
219 __be16 usb_usep2;
220 __be16 usb_usep3;
221 __be16 usb_usep4;
222 u8 res2[4];
223 __be16 usb_usber;
224 u8 res3[2];
225 __be16 usb_usbmr;
226 u8 res4[1];
227 u8 usb_usbs;
228 __be16 usb_ussft;
229 u8 res5[2];
230 __be16 usb_usfrn;
231 u8 res6[0x22];
232} __attribute__ ((packed));
233
234/* MCC */
235struct mcc {
236 __be32 mcce; /* MCC event register */
237 __be32 mccm; /* MCC mask register */
238 __be32 mccf; /* MCC configuration register */
239 __be32 merl; /* MCC emergency request level register */
240 u8 res0[0xF0];
241} __attribute__ ((packed));
242
243/* QE UCC Slow */
244struct ucc_slow {
245 __be32 gumr_l; /* UCCx general mode register (low) */
246 __be32 gumr_h; /* UCCx general mode register (high) */
247 __be16 upsmr; /* UCCx protocol-specific mode register */
248 u8 res0[0x2];
249 __be16 utodr; /* UCCx transmit on demand register */
250 __be16 udsr; /* UCCx data synchronization register */
251 __be16 ucce; /* UCCx event register */
252 u8 res1[0x2];
253 __be16 uccm; /* UCCx mask register */
254 u8 res2[0x1];
255 u8 uccs; /* UCCx status register */
256 u8 res3[0x24];
257 __be16 utpt;
258 u8 res4[0x52];
259 u8 guemr; /* UCC general extended mode register */
260} __attribute__ ((packed));
261
262/* QE UCC Fast */
263struct ucc_fast {
264 __be32 gumr; /* UCCx general mode register */
265 __be32 upsmr; /* UCCx protocol-specific mode register */
266 __be16 utodr; /* UCCx transmit on demand register */
267 u8 res0[0x2];
268 __be16 udsr; /* UCCx data synchronization register */
269 u8 res1[0x2];
270 __be32 ucce; /* UCCx event register */
271 __be32 uccm; /* UCCx mask register */
272 u8 uccs; /* UCCx status register */
273 u8 res2[0x7];
274 __be32 urfb; /* UCC receive FIFO base */
275 __be16 urfs; /* UCC receive FIFO size */
276 u8 res3[0x2];
277 __be16 urfet; /* UCC receive FIFO emergency threshold */
278 __be16 urfset; /* UCC receive FIFO special emergency
279 threshold */
280 __be32 utfb; /* UCC transmit FIFO base */
281 __be16 utfs; /* UCC transmit FIFO size */
282 u8 res4[0x2];
283 __be16 utfet; /* UCC transmit FIFO emergency threshold */
284 u8 res5[0x2];
285 __be16 utftt; /* UCC transmit FIFO transmit threshold */
286 u8 res6[0x2];
287 __be16 utpt; /* UCC transmit polling timer */
288 u8 res7[0x2];
289 __be32 urtry; /* UCC retry counter register */
290 u8 res8[0x4C];
291 u8 guemr; /* UCC general extended mode register */
292} __attribute__ ((packed));
293
294struct ucc {
295 union {
296 struct ucc_slow slow;
297 struct ucc_fast fast;
298 u8 res[0x200]; /* UCC blocks are 512 bytes each */
299 };
300} __attribute__ ((packed));
301
302/* MultiPHY UTOPIA POS Controllers (UPC) */
303struct upc {
304 __be32 upgcr; /* UTOPIA/POS general configuration register */
305 __be32 uplpa; /* UTOPIA/POS last PHY address */
306 __be32 uphec; /* ATM HEC register */
307 __be32 upuc; /* UTOPIA/POS UCC configuration */
308 __be32 updc1; /* UTOPIA/POS device 1 configuration */
309 __be32 updc2; /* UTOPIA/POS device 2 configuration */
310 __be32 updc3; /* UTOPIA/POS device 3 configuration */
311 __be32 updc4; /* UTOPIA/POS device 4 configuration */
312 __be32 upstpa; /* UTOPIA/POS STPA threshold */
313 u8 res0[0xC];
314 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
315 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
316 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
317 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
318 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
319 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
320 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
321 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
322 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
323 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
324 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
325 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
326 __be32 upde1; /* UTOPIA/POS device 1 event */
327 __be32 upde2; /* UTOPIA/POS device 2 event */
328 __be32 upde3; /* UTOPIA/POS device 3 event */
329 __be32 upde4; /* UTOPIA/POS device 4 event */
330 __be16 uprp1;
331 __be16 uprp2;
332 __be16 uprp3;
333 __be16 uprp4;
334 u8 res1[0x8];
335 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
336 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
337 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
338 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
339 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
340 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
341 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
342 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
343 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
344 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
345 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
346 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
347 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
348 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
349 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
350 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
351 __be32 uper1; /* Device 1 port enable register */
352 __be32 uper2; /* Device 2 port enable register */
353 __be32 uper3; /* Device 3 port enable register */
354 __be32 uper4; /* Device 4 port enable register */
355 u8 res2[0x150];
356} __attribute__ ((packed));
357
358/* SDMA */
359struct sdma {
360 __be32 sdsr; /* Serial DMA status register */
361 __be32 sdmr; /* Serial DMA mode register */
362 __be32 sdtr1; /* SDMA system bus threshold register */
363 __be32 sdtr2; /* SDMA secondary bus threshold register */
364 __be32 sdhy1; /* SDMA system bus hysteresis register */
365 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
366 __be32 sdta1; /* SDMA system bus address register */
367 __be32 sdta2; /* SDMA secondary bus address register */
368 __be32 sdtm1; /* SDMA system bus MSNUM register */
369 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
370 u8 res0[0x10];
371 __be32 sdaqr; /* SDMA address bus qualify register */
372 __be32 sdaqmr; /* SDMA address bus qualify mask register */
373 u8 res1[0x4];
374 __be32 sdebcr; /* SDMA CAM entries base register */
375 u8 res2[0x38];
376} __attribute__ ((packed));
377
378/* Debug Space */
379struct dbg {
380 __be32 bpdcr; /* Breakpoint debug command register */
381 __be32 bpdsr; /* Breakpoint debug status register */
382 __be32 bpdmr; /* Breakpoint debug mask register */
383 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
384 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
385 u8 res0[0x8];
386 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
387 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
388 u8 res1[0x8];
389 __be32 bprmir; /* Breakpoint request mode immediate register */
390 __be32 bprmsr; /* Breakpoint request mode serial register */
391 __be32 bpemr; /* Breakpoint exit mode register */
392 u8 res2[0x48];
393} __attribute__ ((packed));
394
395/*
396 * RISC Special Registers (Trap and Breakpoint). These are described in
397 * the QE Developer's Handbook.
398 */
399struct rsp {
400 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
401 u8 res0[64];
402 __be32 ibcr0;
403 __be32 ibs0;
404 __be32 ibcnr0;
405 u8 res1[4];
406 __be32 ibcr1;
407 __be32 ibs1;
408 __be32 ibcnr1;
409 __be32 npcr;
410 __be32 dbcr;
411 __be32 dbar;
412 __be32 dbamr;
413 __be32 dbsr;
414 __be32 dbcnr;
415 u8 res2[12];
416 __be32 dbdr_h;
417 __be32 dbdr_l;
418 __be32 dbdmr_h;
419 __be32 dbdmr_l;
420 __be32 bsr;
421 __be32 bor;
422 __be32 bior;
423 u8 res3[4];
424 __be32 iatr[4];
425 __be32 eccr; /* Exception control configuration register */
426 __be32 eicr;
427 u8 res4[0x100-0xf8];
428} __attribute__ ((packed));
429
430struct qe_immap {
431 struct qe_iram iram; /* I-RAM */
432 struct qe_ic_regs ic; /* Interrupt Controller */
433 struct cp_qe cp; /* Communications Processor */
434 struct qe_mux qmx; /* QE Multiplexer */
435 struct qe_timers qet; /* QE Timers */
436 struct spi spi[0x2]; /* spi */
437 struct mcc mcc; /* mcc */
438 struct qe_brg brg; /* brg */
439 struct usb_ctlr usb; /* USB */
440 struct si1 si1; /* SI */
441 u8 res11[0x800];
442 struct sir sir; /* SI Routing Tables */
443 struct ucc ucc1; /* ucc1 */
444 struct ucc ucc3; /* ucc3 */
445 struct ucc ucc5; /* ucc5 */
446 struct ucc ucc7; /* ucc7 */
447 u8 res12[0x600];
448 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
449 struct ucc ucc2; /* ucc2 */
450 struct ucc ucc4; /* ucc4 */
451 struct ucc ucc6; /* ucc6 */
452 struct ucc ucc8; /* ucc8 */
453 u8 res13[0x600];
454 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
455 struct sdma sdma; /* SDMA */
456 struct dbg dbg; /* 0x104080 - 0x1040FF
457 Debug Space */
458 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
459 RISC Special Registers
460 (Trap and Breakpoint) */
461 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
462 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
463 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
464 u8 muram[0xC000]; /* 0x110000 - 0x11C000
465 Multi-user RAM */
466 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
467 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
468} __attribute__ ((packed));
469
470extern struct qe_immap __iomem *qe_immr;
471extern phys_addr_t get_qe_base(void);
472
473static inline unsigned long immrbar_virt_to_phys(void *address)
474{
475 if ( ((u32)address >= (u32)qe_immr) &&
476 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
477 return (unsigned long)(address - (u32)qe_immr +
478 (u32)get_qe_base());
479 return (unsigned long)virt_to_phys(address);
480}
481
482#endif /* __KERNEL__ */
483#endif /* _ASM_POWERPC_IMMAP_QE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 06:21:56 -0400