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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-12-18 14:13:22 -0500
committerPaul Mackerras <paulus@samba.org>2008-12-20 22:21:15 -0500
commit6d2170be4561293a6aa821c773687bd3f18e8206 (patch)
treeb267fb2405c6029dcc7958c5786699741064e43f /arch/powerpc/include/asm/cputable.h
parentfecba96268fc48ab9b4a016356a8f2371df25e64 (diff)
powerpc/4xx: Extended DCR support v2
This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/include/asm/cputable.h')
-rw-r--r--arch/powerpc/include/asm/cputable.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index f3d9d7417166..31888322d76a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -164,6 +164,7 @@ extern const char *powerpc_base_platform;
164#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 164#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
165#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) 165#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
166#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000) 166#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
167#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
167 168
168/* 169/*
169 * Add the 64-bit processor unique features in the top half of the word; 170 * Add the 64-bit processor unique features in the top half of the word;
@@ -369,6 +370,8 @@ extern const char *powerpc_base_platform;
369#define CPU_FTRS_8XX (CPU_FTR_USE_TB) 370#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
370#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 371#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
371#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 372#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
373#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
374 CPU_FTR_INDEXED_DCR)
372#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 375#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
373 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 376 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
374 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE) 377 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@@ -455,7 +458,7 @@ enum {
455 CPU_FTRS_40X | 458 CPU_FTRS_40X |
456#endif 459#endif
457#ifdef CONFIG_44x 460#ifdef CONFIG_44x
458 CPU_FTRS_44X | 461 CPU_FTRS_44X | CPU_FTRS_440x6 |
459#endif 462#endif
460#ifdef CONFIG_E200 463#ifdef CONFIG_E200
461 CPU_FTRS_E200 | 464 CPU_FTRS_E200 |
@@ -495,7 +498,7 @@ enum {
495 CPU_FTRS_40X & 498 CPU_FTRS_40X &
496#endif 499#endif
497#ifdef CONFIG_44x 500#ifdef CONFIG_44x
498 CPU_FTRS_44X & 501 CPU_FTRS_44X & CPU_FTRS_440x6 &
499#endif 502#endif
500#ifdef CONFIG_E200 503#ifdef CONFIG_E200
501 CPU_FTRS_E200 & 504 CPU_FTRS_E200 &