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authorDiana Craciun <Diana.Craciun@freescale.com>2014-05-05 12:04:27 -0400
committerScott Wood <scottwood@freescale.com>2014-05-22 19:08:26 -0400
commitf2e7bfbb0440e7010f421ceddb9eb400cd1eee63 (patch)
treef655a747c06ec60d8d8e5a7eaa01f33dbb327240 /arch/powerpc/boot
parent385510beda1da138f2f725abd351c16e370427f1 (diff)
powerpc/fsl: Updated device trees for platforms with corenet version 2
Updated the device trees according to the corenet-cf binding definition. Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/b4860emu.dts7
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi12
-rw-r--r--arch/powerpc/boot/dts/t4240emu.dts15
9 files changed, 42 insertions, 12 deletions
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021f2dfc..85646b4f96e1 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -61,21 +61,25 @@
61 device_type = "cpu"; 61 device_type = "cpu";
62 reg = <0 1>; 62 reg = <0 1>;
63 next-level-cache = <&L2>; 63 next-level-cache = <&L2>;
64 fsl,portid-mapping = <0x80000000>;
64 }; 65 };
65 cpu1: PowerPC,e6500@2 { 66 cpu1: PowerPC,e6500@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 reg = <2 3>; 68 reg = <2 3>;
68 next-level-cache = <&L2>; 69 next-level-cache = <&L2>;
70 fsl,portid-mapping = <0x80000000>;
69 }; 71 };
70 cpu2: PowerPC,e6500@4 { 72 cpu2: PowerPC,e6500@4 {
71 device_type = "cpu"; 73 device_type = "cpu";
72 reg = <4 5>; 74 reg = <4 5>;
73 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
74 }; 77 };
75 cpu3: PowerPC,e6500@6 { 78 cpu3: PowerPC,e6500@6 {
76 device_type = "cpu"; 79 device_type = "cpu";
77 reg = <6 7>; 80 reg = <6 7>;
78 next-level-cache = <&L2>; 81 next-level-cache = <&L2>;
82 fsl,portid-mapping = <0x80000000>;
79 }; 83 };
80 }; 84 };
81}; 85};
@@ -157,7 +161,7 @@
157 }; 161 };
158 162
159 corenet-cf@18000 { 163 corenet-cf@18000 {
160 compatible = "fsl,b4-corenet-cf"; 164 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
161 reg = <0x18000 0x1000>; 165 reg = <0x18000 0x1000>;
162 interrupts = <16 2 1 0>; 166 interrupts = <16 2 1 0>;
163 fsl,ccf-num-csdids = <32>; 167 fsl,ccf-num-csdids = <32>;
@@ -167,6 +171,7 @@
167 iommu@20000 { 171 iommu@20000 {
168 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 172 compatible = "fsl,pamu-v1.0", "fsl,pamu";
169 reg = <0x20000 0x4000>; 173 reg = <0x20000 0x4000>;
174 fsl,portid-mapping = <0x8000>;
170 #address-cells = <1>; 175 #address-cells = <1>;
171 #size-cells = <1>; 176 #size-cells = <1>;
172 interrupts = < 177 interrupts = <
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f9927be..d67894459ac8 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
76 compatible = "fsl,b4420-l3-cache-controller", "cache"; 76 compatible = "fsl,b4420-l3-cache-controller", "cache";
77 }; 77 };
78 78
79 corenet-cf@18000 {
80 compatible = "fsl,b4420-corenet-cf";
81 };
82
83 guts: global-utilities@e0000 { 79 guts: global-utilities@e0000 {
84 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; 80 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85 }; 81 };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 2419731c2c54..338af7e39dd9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -66,12 +66,14 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 }; 78 };
77}; 79};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b05117..582381dba1d7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
120 compatible = "fsl,b4860-l3-cache-controller", "cache"; 120 compatible = "fsl,b4860-l3-cache-controller", "cache";
121 }; 121 };
122 122
123 corenet-cf@18000 {
124 compatible = "fsl,b4860-corenet-cf";
125 };
126
127 guts: global-utilities@e0000 { 123 guts: global-utilities@e0000 {
128 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; 124 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
129 }; 125 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 142ac862cacf..1948f73fd26b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -66,24 +66,28 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 cpu2: PowerPC,e6500@4 { 78 cpu2: PowerPC,e6500@4 {
77 device_type = "cpu"; 79 device_type = "cpu";
78 reg = <4 5>; 80 reg = <4 5>;
79 clocks = <&mux0>; 81 clocks = <&mux0>;
80 next-level-cache = <&L2>; 82 next-level-cache = <&L2>;
83 fsl,portid-mapping = <0x80000000>;
81 }; 84 };
82 cpu3: PowerPC,e6500@6 { 85 cpu3: PowerPC,e6500@6 {
83 device_type = "cpu"; 86 device_type = "cpu";
84 reg = <6 7>; 87 reg = <6 7>;
85 clocks = <&mux0>; 88 clocks = <&mux0>;
86 next-level-cache = <&L2>; 89 next-level-cache = <&L2>;
90 fsl,portid-mapping = <0x80000000>;
87 }; 91 };
88 }; 92 };
89}; 93};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e48277c46..1a54ba71f685 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
158 }; 158 };
159 159
160 corenet-cf@18000 { 160 corenet-cf@18000 {
161 compatible = "fsl,b4-corenet-cf"; 161 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
162 reg = <0x18000 0x1000>; 162 reg = <0x18000 0x1000>;
163 interrupts = <16 2 1 0>; 163 interrupts = <16 2 1 0>;
164 fsl,ccf-num-csdids = <32>; 164 fsl,ccf-num-csdids = <32>;
@@ -168,6 +168,7 @@
168 iommu@20000 { 168 iommu@20000 {
169 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 169 compatible = "fsl,pamu-v1.0", "fsl,pamu";
170 reg = <0x20000 0x4000>; 170 reg = <0x20000 0x4000>;
171 fsl,portid-mapping = <0x8000>;
171 #address-cells = <1>; 172 #address-cells = <1>;
172 #size-cells = <1>; 173 #size-cells = <1>;
173 interrupts = < 174 interrupts = <
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74ff11b4..793669baa13e 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
343 }; 343 };
344 344
345 corenet-cf@18000 { 345 corenet-cf@18000 {
346 compatible = "fsl,corenet-cf"; 346 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
347 reg = <0x18000 0x1000>; 347 reg = <0x18000 0x1000>;
348 interrupts = <16 2 1 31>; 348 interrupts = <16 2 1 31>;
349 fsl,ccf-num-csdids = <32>; 349 fsl,ccf-num-csdids = <32>;
@@ -353,6 +353,7 @@
353 iommu@20000 { 353 iommu@20000 {
354 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 354 compatible = "fsl,pamu-v1.0", "fsl,pamu";
355 reg = <0x20000 0x6000>; 355 reg = <0x20000 0x6000>;
356 fsl,portid-mapping = <0x8000>;
356 interrupts = < 357 interrupts = <
357 24 2 0 0 358 24 2 0 0
358 16 2 1 30>; 359 16 2 1 30>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 0b8ccc5b4a46..d2f157edbe81 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,72 +69,84 @@
69 reg = <0 1>; 69 reg = <0 1>;
70 clocks = <&mux0>; 70 clocks = <&mux0>;
71 next-level-cache = <&L2_1>; 71 next-level-cache = <&L2_1>;
72 fsl,portid-mapping = <0x80000000>;
72 }; 73 };
73 cpu1: PowerPC,e6500@2 { 74 cpu1: PowerPC,e6500@2 {
74 device_type = "cpu"; 75 device_type = "cpu";
75 reg = <2 3>; 76 reg = <2 3>;
76 clocks = <&mux0>; 77 clocks = <&mux0>;
77 next-level-cache = <&L2_1>; 78 next-level-cache = <&L2_1>;
79 fsl,portid-mapping = <0x80000000>;
78 }; 80 };
79 cpu2: PowerPC,e6500@4 { 81 cpu2: PowerPC,e6500@4 {
80 device_type = "cpu"; 82 device_type = "cpu";
81 reg = <4 5>; 83 reg = <4 5>;
82 clocks = <&mux0>; 84 clocks = <&mux0>;
83 next-level-cache = <&L2_1>; 85 next-level-cache = <&L2_1>;
86 fsl,portid-mapping = <0x80000000>;
84 }; 87 };
85 cpu3: PowerPC,e6500@6 { 88 cpu3: PowerPC,e6500@6 {
86 device_type = "cpu"; 89 device_type = "cpu";
87 reg = <6 7>; 90 reg = <6 7>;
88 clocks = <&mux0>; 91 clocks = <&mux0>;
89 next-level-cache = <&L2_1>; 92 next-level-cache = <&L2_1>;
93 fsl,portid-mapping = <0x80000000>;
90 }; 94 };
91 cpu4: PowerPC,e6500@8 { 95 cpu4: PowerPC,e6500@8 {
92 device_type = "cpu"; 96 device_type = "cpu";
93 reg = <8 9>; 97 reg = <8 9>;
94 clocks = <&mux1>; 98 clocks = <&mux1>;
95 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
96 }; 101 };
97 cpu5: PowerPC,e6500@10 { 102 cpu5: PowerPC,e6500@10 {
98 device_type = "cpu"; 103 device_type = "cpu";
99 reg = <10 11>; 104 reg = <10 11>;
100 clocks = <&mux1>; 105 clocks = <&mux1>;
101 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x40000000>;
102 }; 108 };
103 cpu6: PowerPC,e6500@12 { 109 cpu6: PowerPC,e6500@12 {
104 device_type = "cpu"; 110 device_type = "cpu";
105 reg = <12 13>; 111 reg = <12 13>;
106 clocks = <&mux1>; 112 clocks = <&mux1>;
107 next-level-cache = <&L2_2>; 113 next-level-cache = <&L2_2>;
114 fsl,portid-mapping = <0x40000000>;
108 }; 115 };
109 cpu7: PowerPC,e6500@14 { 116 cpu7: PowerPC,e6500@14 {
110 device_type = "cpu"; 117 device_type = "cpu";
111 reg = <14 15>; 118 reg = <14 15>;
112 clocks = <&mux1>; 119 clocks = <&mux1>;
113 next-level-cache = <&L2_2>; 120 next-level-cache = <&L2_2>;
121 fsl,portid-mapping = <0x40000000>;
114 }; 122 };
115 cpu8: PowerPC,e6500@16 { 123 cpu8: PowerPC,e6500@16 {
116 device_type = "cpu"; 124 device_type = "cpu";
117 reg = <16 17>; 125 reg = <16 17>;
118 clocks = <&mux2>; 126 clocks = <&mux2>;
119 next-level-cache = <&L2_3>; 127 next-level-cache = <&L2_3>;
128 fsl,portid-mapping = <0x20000000>;
120 }; 129 };
121 cpu9: PowerPC,e6500@18 { 130 cpu9: PowerPC,e6500@18 {
122 device_type = "cpu"; 131 device_type = "cpu";
123 reg = <18 19>; 132 reg = <18 19>;
124 clocks = <&mux2>; 133 clocks = <&mux2>;
125 next-level-cache = <&L2_3>; 134 next-level-cache = <&L2_3>;
135 fsl,portid-mapping = <0x20000000>;
126 }; 136 };
127 cpu10: PowerPC,e6500@20 { 137 cpu10: PowerPC,e6500@20 {
128 device_type = "cpu"; 138 device_type = "cpu";
129 reg = <20 21>; 139 reg = <20 21>;
130 clocks = <&mux2>; 140 clocks = <&mux2>;
131 next-level-cache = <&L2_3>; 141 next-level-cache = <&L2_3>;
142 fsl,portid-mapping = <0x20000000>;
132 }; 143 };
133 cpu11: PowerPC,e6500@22 { 144 cpu11: PowerPC,e6500@22 {
134 device_type = "cpu"; 145 device_type = "cpu";
135 reg = <22 23>; 146 reg = <22 23>;
136 clocks = <&mux2>; 147 clocks = <&mux2>;
137 next-level-cache = <&L2_3>; 148 next-level-cache = <&L2_3>;
149 fsl,portid-mapping = <0x20000000>;
138 }; 150 };
139 }; 151 };
140}; 152};
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab335598..bc12127a03fb 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -60,63 +60,75 @@
60 device_type = "cpu"; 60 device_type = "cpu";
61 reg = <0 1>; 61 reg = <0 1>;
62 next-level-cache = <&L2_1>; 62 next-level-cache = <&L2_1>;
63 fsl,portid-mapping = <0x80000000>;
63 }; 64 };
64 cpu1: PowerPC,e6500@2 { 65 cpu1: PowerPC,e6500@2 {
65 device_type = "cpu"; 66 device_type = "cpu";
66 reg = <2 3>; 67 reg = <2 3>;
67 next-level-cache = <&L2_1>; 68 next-level-cache = <&L2_1>;
69 fsl,portid-mapping = <0x80000000>;
68 }; 70 };
69 cpu2: PowerPC,e6500@4 { 71 cpu2: PowerPC,e6500@4 {
70 device_type = "cpu"; 72 device_type = "cpu";
71 reg = <4 5>; 73 reg = <4 5>;
72 next-level-cache = <&L2_1>; 74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>;
73 }; 76 };
74 cpu3: PowerPC,e6500@6 { 77 cpu3: PowerPC,e6500@6 {
75 device_type = "cpu"; 78 device_type = "cpu";
76 reg = <6 7>; 79 reg = <6 7>;
77 next-level-cache = <&L2_1>; 80 next-level-cache = <&L2_1>;
81 fsl,portid-mapping = <0x80000000>;
78 }; 82 };
79 83
80 cpu4: PowerPC,e6500@8 { 84 cpu4: PowerPC,e6500@8 {
81 device_type = "cpu"; 85 device_type = "cpu";
82 reg = <8 9>; 86 reg = <8 9>;
83 next-level-cache = <&L2_2>; 87 next-level-cache = <&L2_2>;
88 fsl,portid-mapping = <0x40000000>;
84 }; 89 };
85 cpu5: PowerPC,e6500@10 { 90 cpu5: PowerPC,e6500@10 {
86 device_type = "cpu"; 91 device_type = "cpu";
87 reg = <10 11>; 92 reg = <10 11>;
88 next-level-cache = <&L2_2>; 93 next-level-cache = <&L2_2>;
94 fsl,portid-mapping = <0x40000000>;
89 }; 95 };
90 cpu6: PowerPC,e6500@12 { 96 cpu6: PowerPC,e6500@12 {
91 device_type = "cpu"; 97 device_type = "cpu";
92 reg = <12 13>; 98 reg = <12 13>;
93 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
94 }; 101 };
95 cpu7: PowerPC,e6500@14 { 102 cpu7: PowerPC,e6500@14 {
96 device_type = "cpu"; 103 device_type = "cpu";
97 reg = <14 15>; 104 reg = <14 15>;
98 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x40000000>;
99 }; 107 };
100 108
101 cpu8: PowerPC,e6500@16 { 109 cpu8: PowerPC,e6500@16 {
102 device_type = "cpu"; 110 device_type = "cpu";
103 reg = <16 17>; 111 reg = <16 17>;
104 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
113 fsl,portid-mapping = <0x20000000>;
105 }; 114 };
106 cpu9: PowerPC,e6500@18 { 115 cpu9: PowerPC,e6500@18 {
107 device_type = "cpu"; 116 device_type = "cpu";
108 reg = <18 19>; 117 reg = <18 19>;
109 next-level-cache = <&L2_3>; 118 next-level-cache = <&L2_3>;
119 fsl,portid-mapping = <0x20000000>;
110 }; 120 };
111 cpu10: PowerPC,e6500@20 { 121 cpu10: PowerPC,e6500@20 {
112 device_type = "cpu"; 122 device_type = "cpu";
113 reg = <20 21>; 123 reg = <20 21>;
114 next-level-cache = <&L2_3>; 124 next-level-cache = <&L2_3>;
125 fsl,portid-mapping = <0x20000000>;
115 }; 126 };
116 cpu11: PowerPC,e6500@22 { 127 cpu11: PowerPC,e6500@22 {
117 device_type = "cpu"; 128 device_type = "cpu";
118 reg = <22 23>; 129 reg = <22 23>;
119 next-level-cache = <&L2_3>; 130 next-level-cache = <&L2_3>;
131 fsl,portid-mapping = <0x20000000>;
120 }; 132 };
121 }; 133 };
122}; 134};
@@ -213,7 +225,7 @@
213 }; 225 };
214 226
215 corenet-cf@18000 { 227 corenet-cf@18000 {
216 compatible = "fsl,corenet-cf"; 228 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
217 reg = <0x18000 0x1000>; 229 reg = <0x18000 0x1000>;
218 interrupts = <16 2 1 31>; 230 interrupts = <16 2 1 31>;
219 fsl,ccf-num-csdids = <32>; 231 fsl,ccf-num-csdids = <32>;
@@ -223,6 +235,7 @@
223 iommu@20000 { 235 iommu@20000 {
224 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 236 compatible = "fsl,pamu-v1.0", "fsl,pamu";
225 reg = <0x20000 0x6000>; 237 reg = <0x20000 0x6000>;
238 fsl,portid-mapping = <0x8000>;
226 interrupts = < 239 interrupts = <
227 24 2 0 0 240 24 2 0 0
228 16 2 1 30>; 241 16 2 1 30>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 07:47:04 -0500