aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot
diff options
context:
space:
mode:
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-01-29 00:53:55 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-01-29 00:53:55 -0500
commite9a371100dfdfa4c9f994059d19d98c9b4fd80af (patch)
tree11e9d240d87834f9da927aaa4027e7dfcbd01eb8 /arch/powerpc/boot
parentd891ea23d5203e5c47439b2a174f86a00b356a6c (diff)
parentbc75059422338197ce487d338ac9c898761e1e61 (diff)
Merge remote-tracking branch 'agust/next' into next
<< Switch mpc512x to the common clock framework and adapt mpc512x drivers to use the new clock driver. Old PPC_CLOCK code is removed entirely since there are no users any more. >>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/ac14xx.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi113
-rw-r--r--arch/powerpc/boot/dts/mpc5125twr.dts53
3 files changed, 171 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c4088cba..a1b883730b31 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
139 }; 139 };
140 }; 140 };
141 141
142 clocks {
143 osc {
144 clock-frequency = <25000000>;
145 };
146 };
147
142 soc@80000000 { 148 soc@80000000 {
149 bus-frequency = <80000000>; /* 80 MHz ips bus */
143 150
144 clock@f00 { 151 clock@f00 {
145 compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock"; 152 compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 2d7cb04ac962..2c0e1552d20b 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12#include <dt-bindings/clock/mpc512x-clock.h>
13
12/dts-v1/; 14/dts-v1/;
13 15
14/ { 16/ {
@@ -49,6 +51,10 @@
49 compatible = "fsl,mpc5121-mbx"; 51 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>; 52 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>; 53 interrupts = <66 0x8>;
54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
57 clock-names = "mbx-bus", "mbx-3d", "mbx";
52 }; 58 };
53 59
54 sram@30000000 { 60 sram@30000000 {
@@ -62,6 +68,8 @@
62 interrupts = <6 8>; 68 interrupts = <6 8>;
63 #address-cells = <1>; 69 #address-cells = <1>;
64 #size-cells = <1>; 70 #size-cells = <1>;
71 clocks = <&clks MPC512x_CLK_NFC>;
72 clock-names = "ipg";
65 }; 73 };
66 74
67 localbus@80000020 { 75 localbus@80000020 {
@@ -73,6 +81,17 @@
73 ranges = <0x0 0x0 0xfc000000 0x04000000>; 81 ranges = <0x0 0x0 0xfc000000 0x04000000>;
74 }; 82 };
75 83
84 clocks {
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 osc: osc {
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <33000000>;
92 };
93 };
94
76 soc@80000000 { 95 soc@80000000 {
77 compatible = "fsl,mpc5121-immr"; 96 compatible = "fsl,mpc5121-immr";
78 #address-cells = <1>; 97 #address-cells = <1>;
@@ -117,9 +136,12 @@
117 }; 136 };
118 137
119 /* Clock control */ 138 /* Clock control */
120 clock@f00 { 139 clks: clock@f00 {
121 compatible = "fsl,mpc5121-clock"; 140 compatible = "fsl,mpc5121-clock";
122 reg = <0xf00 0x100>; 141 reg = <0xf00 0x100>;
142 #clock-cells = <1>;
143 clocks = <&osc>;
144 clock-names = "osc";
123 }; 145 };
124 146
125 /* Power Management Controller */ 147 /* Power Management Controller */
@@ -139,12 +161,24 @@
139 compatible = "fsl,mpc5121-mscan"; 161 compatible = "fsl,mpc5121-mscan";
140 reg = <0x1300 0x80>; 162 reg = <0x1300 0x80>;
141 interrupts = <12 0x8>; 163 interrupts = <12 0x8>;
164 clocks = <&clks MPC512x_CLK_BDLC>,
165 <&clks MPC512x_CLK_IPS>,
166 <&clks MPC512x_CLK_SYS>,
167 <&clks MPC512x_CLK_REF>,
168 <&clks MPC512x_CLK_MSCAN0_MCLK>;
169 clock-names = "ipg", "ips", "sys", "ref", "mclk";
142 }; 170 };
143 171
144 can@1380 { 172 can@1380 {
145 compatible = "fsl,mpc5121-mscan"; 173 compatible = "fsl,mpc5121-mscan";
146 reg = <0x1380 0x80>; 174 reg = <0x1380 0x80>;
147 interrupts = <13 0x8>; 175 interrupts = <13 0x8>;
176 clocks = <&clks MPC512x_CLK_BDLC>,
177 <&clks MPC512x_CLK_IPS>,
178 <&clks MPC512x_CLK_SYS>,
179 <&clks MPC512x_CLK_REF>,
180 <&clks MPC512x_CLK_MSCAN1_MCLK>;
181 clock-names = "ipg", "ips", "sys", "ref", "mclk";
148 }; 182 };
149 183
150 sdhc@1500 { 184 sdhc@1500 {
@@ -153,6 +187,9 @@
153 interrupts = <8 0x8>; 187 interrupts = <8 0x8>;
154 dmas = <&dma0 30>; 188 dmas = <&dma0 30>;
155 dma-names = "rx-tx"; 189 dma-names = "rx-tx";
190 clocks = <&clks MPC512x_CLK_IPS>,
191 <&clks MPC512x_CLK_SDHC>;
192 clock-names = "ipg", "per";
156 }; 193 };
157 194
158 i2c@1700 { 195 i2c@1700 {
@@ -161,6 +198,8 @@
161 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 198 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
162 reg = <0x1700 0x20>; 199 reg = <0x1700 0x20>;
163 interrupts = <9 0x8>; 200 interrupts = <9 0x8>;
201 clocks = <&clks MPC512x_CLK_I2C>;
202 clock-names = "ipg";
164 }; 203 };
165 204
166 i2c@1720 { 205 i2c@1720 {
@@ -169,6 +208,8 @@
169 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 208 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
170 reg = <0x1720 0x20>; 209 reg = <0x1720 0x20>;
171 interrupts = <10 0x8>; 210 interrupts = <10 0x8>;
211 clocks = <&clks MPC512x_CLK_I2C>;
212 clock-names = "ipg";
172 }; 213 };
173 214
174 i2c@1740 { 215 i2c@1740 {
@@ -177,6 +218,8 @@
177 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 218 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
178 reg = <0x1740 0x20>; 219 reg = <0x1740 0x20>;
179 interrupts = <11 0x8>; 220 interrupts = <11 0x8>;
221 clocks = <&clks MPC512x_CLK_I2C>;
222 clock-names = "ipg";
180 }; 223 };
181 224
182 i2ccontrol@1760 { 225 i2ccontrol@1760 {
@@ -188,30 +231,48 @@
188 compatible = "fsl,mpc5121-axe"; 231 compatible = "fsl,mpc5121-axe";
189 reg = <0x2000 0x100>; 232 reg = <0x2000 0x100>;
190 interrupts = <42 0x8>; 233 interrupts = <42 0x8>;
234 clocks = <&clks MPC512x_CLK_AXE>;
235 clock-names = "ipg";
191 }; 236 };
192 237
193 display@2100 { 238 display@2100 {
194 compatible = "fsl,mpc5121-diu"; 239 compatible = "fsl,mpc5121-diu";
195 reg = <0x2100 0x100>; 240 reg = <0x2100 0x100>;
196 interrupts = <64 0x8>; 241 interrupts = <64 0x8>;
242 clocks = <&clks MPC512x_CLK_DIU>;
243 clock-names = "ipg";
197 }; 244 };
198 245
199 can@2300 { 246 can@2300 {
200 compatible = "fsl,mpc5121-mscan"; 247 compatible = "fsl,mpc5121-mscan";
201 reg = <0x2300 0x80>; 248 reg = <0x2300 0x80>;
202 interrupts = <90 0x8>; 249 interrupts = <90 0x8>;
250 clocks = <&clks MPC512x_CLK_BDLC>,
251 <&clks MPC512x_CLK_IPS>,
252 <&clks MPC512x_CLK_SYS>,
253 <&clks MPC512x_CLK_REF>,
254 <&clks MPC512x_CLK_MSCAN2_MCLK>;
255 clock-names = "ipg", "ips", "sys", "ref", "mclk";
203 }; 256 };
204 257
205 can@2380 { 258 can@2380 {
206 compatible = "fsl,mpc5121-mscan"; 259 compatible = "fsl,mpc5121-mscan";
207 reg = <0x2380 0x80>; 260 reg = <0x2380 0x80>;
208 interrupts = <91 0x8>; 261 interrupts = <91 0x8>;
262 clocks = <&clks MPC512x_CLK_BDLC>,
263 <&clks MPC512x_CLK_IPS>,
264 <&clks MPC512x_CLK_SYS>,
265 <&clks MPC512x_CLK_REF>,
266 <&clks MPC512x_CLK_MSCAN3_MCLK>;
267 clock-names = "ipg", "ips", "sys", "ref", "mclk";
209 }; 268 };
210 269
211 viu@2400 { 270 viu@2400 {
212 compatible = "fsl,mpc5121-viu"; 271 compatible = "fsl,mpc5121-viu";
213 reg = <0x2400 0x400>; 272 reg = <0x2400 0x400>;
214 interrupts = <67 0x8>; 273 interrupts = <67 0x8>;
274 clocks = <&clks MPC512x_CLK_VIU>;
275 clock-names = "ipg";
215 }; 276 };
216 277
217 mdio@2800 { 278 mdio@2800 {
@@ -219,6 +280,8 @@
219 reg = <0x2800 0x800>; 280 reg = <0x2800 0x800>;
220 #address-cells = <1>; 281 #address-cells = <1>;
221 #size-cells = <0>; 282 #size-cells = <0>;
283 clocks = <&clks MPC512x_CLK_FEC>;
284 clock-names = "per";
222 }; 285 };
223 286
224 eth0: ethernet@2800 { 287 eth0: ethernet@2800 {
@@ -227,6 +290,8 @@
227 reg = <0x2800 0x800>; 290 reg = <0x2800 0x800>;
228 local-mac-address = [ 00 00 00 00 00 00 ]; 291 local-mac-address = [ 00 00 00 00 00 00 ];
229 interrupts = <4 0x8>; 292 interrupts = <4 0x8>;
293 clocks = <&clks MPC512x_CLK_FEC>;
294 clock-names = "per";
230 }; 295 };
231 296
232 /* USB1 using external ULPI PHY */ 297 /* USB1 using external ULPI PHY */
@@ -238,6 +303,8 @@
238 interrupts = <43 0x8>; 303 interrupts = <43 0x8>;
239 dr_mode = "otg"; 304 dr_mode = "otg";
240 phy_type = "ulpi"; 305 phy_type = "ulpi";
306 clocks = <&clks MPC512x_CLK_USB1>;
307 clock-names = "ipg";
241 }; 308 };
242 309
243 /* USB0 using internal UTMI PHY */ 310 /* USB0 using internal UTMI PHY */
@@ -249,6 +316,8 @@
249 interrupts = <44 0x8>; 316 interrupts = <44 0x8>;
250 dr_mode = "otg"; 317 dr_mode = "otg";
251 phy_type = "utmi_wide"; 318 phy_type = "utmi_wide";
319 clocks = <&clks MPC512x_CLK_USB2>;
320 clock-names = "ipg";
252 }; 321 };
253 322
254 /* IO control */ 323 /* IO control */
@@ -267,6 +336,8 @@
267 compatible = "fsl,mpc5121-pata"; 336 compatible = "fsl,mpc5121-pata";
268 reg = <0x10200 0x100>; 337 reg = <0x10200 0x100>;
269 interrupts = <5 0x8>; 338 interrupts = <5 0x8>;
339 clocks = <&clks MPC512x_CLK_PATA>;
340 clock-names = "ipg";
270 }; 341 };
271 342
272 /* 512x PSCs are not 52xx PSC compatible */ 343 /* 512x PSCs are not 52xx PSC compatible */
@@ -278,6 +349,9 @@
278 interrupts = <40 0x8>; 349 interrupts = <40 0x8>;
279 fsl,rx-fifo-size = <16>; 350 fsl,rx-fifo-size = <16>;
280 fsl,tx-fifo-size = <16>; 351 fsl,tx-fifo-size = <16>;
352 clocks = <&clks MPC512x_CLK_PSC0>,
353 <&clks MPC512x_CLK_PSC0_MCLK>;
354 clock-names = "ipg", "mclk";
281 }; 355 };
282 356
283 /* PSC1 */ 357 /* PSC1 */
@@ -287,6 +361,9 @@
287 interrupts = <40 0x8>; 361 interrupts = <40 0x8>;
288 fsl,rx-fifo-size = <16>; 362 fsl,rx-fifo-size = <16>;
289 fsl,tx-fifo-size = <16>; 363 fsl,tx-fifo-size = <16>;
364 clocks = <&clks MPC512x_CLK_PSC1>,
365 <&clks MPC512x_CLK_PSC1_MCLK>;
366 clock-names = "ipg", "mclk";
290 }; 367 };
291 368
292 /* PSC2 */ 369 /* PSC2 */
@@ -296,6 +373,9 @@
296 interrupts = <40 0x8>; 373 interrupts = <40 0x8>;
297 fsl,rx-fifo-size = <16>; 374 fsl,rx-fifo-size = <16>;
298 fsl,tx-fifo-size = <16>; 375 fsl,tx-fifo-size = <16>;
376 clocks = <&clks MPC512x_CLK_PSC2>,
377 <&clks MPC512x_CLK_PSC2_MCLK>;
378 clock-names = "ipg", "mclk";
299 }; 379 };
300 380
301 /* PSC3 */ 381 /* PSC3 */
@@ -305,6 +385,9 @@
305 interrupts = <40 0x8>; 385 interrupts = <40 0x8>;
306 fsl,rx-fifo-size = <16>; 386 fsl,rx-fifo-size = <16>;
307 fsl,tx-fifo-size = <16>; 387 fsl,tx-fifo-size = <16>;
388 clocks = <&clks MPC512x_CLK_PSC3>,
389 <&clks MPC512x_CLK_PSC3_MCLK>;
390 clock-names = "ipg", "mclk";
308 }; 391 };
309 392
310 /* PSC4 */ 393 /* PSC4 */
@@ -314,6 +397,9 @@
314 interrupts = <40 0x8>; 397 interrupts = <40 0x8>;
315 fsl,rx-fifo-size = <16>; 398 fsl,rx-fifo-size = <16>;
316 fsl,tx-fifo-size = <16>; 399 fsl,tx-fifo-size = <16>;
400 clocks = <&clks MPC512x_CLK_PSC4>,
401 <&clks MPC512x_CLK_PSC4_MCLK>;
402 clock-names = "ipg", "mclk";
317 }; 403 };
318 404
319 /* PSC5 */ 405 /* PSC5 */
@@ -323,6 +409,9 @@
323 interrupts = <40 0x8>; 409 interrupts = <40 0x8>;
324 fsl,rx-fifo-size = <16>; 410 fsl,rx-fifo-size = <16>;
325 fsl,tx-fifo-size = <16>; 411 fsl,tx-fifo-size = <16>;
412 clocks = <&clks MPC512x_CLK_PSC5>,
413 <&clks MPC512x_CLK_PSC5_MCLK>;
414 clock-names = "ipg", "mclk";
326 }; 415 };
327 416
328 /* PSC6 */ 417 /* PSC6 */
@@ -332,6 +421,9 @@
332 interrupts = <40 0x8>; 421 interrupts = <40 0x8>;
333 fsl,rx-fifo-size = <16>; 422 fsl,rx-fifo-size = <16>;
334 fsl,tx-fifo-size = <16>; 423 fsl,tx-fifo-size = <16>;
424 clocks = <&clks MPC512x_CLK_PSC6>,
425 <&clks MPC512x_CLK_PSC6_MCLK>;
426 clock-names = "ipg", "mclk";
335 }; 427 };
336 428
337 /* PSC7 */ 429 /* PSC7 */
@@ -341,6 +433,9 @@
341 interrupts = <40 0x8>; 433 interrupts = <40 0x8>;
342 fsl,rx-fifo-size = <16>; 434 fsl,rx-fifo-size = <16>;
343 fsl,tx-fifo-size = <16>; 435 fsl,tx-fifo-size = <16>;
436 clocks = <&clks MPC512x_CLK_PSC7>,
437 <&clks MPC512x_CLK_PSC7_MCLK>;
438 clock-names = "ipg", "mclk";
344 }; 439 };
345 440
346 /* PSC8 */ 441 /* PSC8 */
@@ -350,6 +445,9 @@
350 interrupts = <40 0x8>; 445 interrupts = <40 0x8>;
351 fsl,rx-fifo-size = <16>; 446 fsl,rx-fifo-size = <16>;
352 fsl,tx-fifo-size = <16>; 447 fsl,tx-fifo-size = <16>;
448 clocks = <&clks MPC512x_CLK_PSC8>,
449 <&clks MPC512x_CLK_PSC8_MCLK>;
450 clock-names = "ipg", "mclk";
353 }; 451 };
354 452
355 /* PSC9 */ 453 /* PSC9 */
@@ -359,6 +457,9 @@
359 interrupts = <40 0x8>; 457 interrupts = <40 0x8>;
360 fsl,rx-fifo-size = <16>; 458 fsl,rx-fifo-size = <16>;
361 fsl,tx-fifo-size = <16>; 459 fsl,tx-fifo-size = <16>;
460 clocks = <&clks MPC512x_CLK_PSC9>,
461 <&clks MPC512x_CLK_PSC9_MCLK>;
462 clock-names = "ipg", "mclk";
362 }; 463 };
363 464
364 /* PSC10 */ 465 /* PSC10 */
@@ -368,6 +469,9 @@
368 interrupts = <40 0x8>; 469 interrupts = <40 0x8>;
369 fsl,rx-fifo-size = <16>; 470 fsl,rx-fifo-size = <16>;
370 fsl,tx-fifo-size = <16>; 471 fsl,tx-fifo-size = <16>;
472 clocks = <&clks MPC512x_CLK_PSC10>,
473 <&clks MPC512x_CLK_PSC10_MCLK>;
474 clock-names = "ipg", "mclk";
371 }; 475 };
372 476
373 /* PSC11 */ 477 /* PSC11 */
@@ -377,12 +481,17 @@
377 interrupts = <40 0x8>; 481 interrupts = <40 0x8>;
378 fsl,rx-fifo-size = <16>; 482 fsl,rx-fifo-size = <16>;
379 fsl,tx-fifo-size = <16>; 483 fsl,tx-fifo-size = <16>;
484 clocks = <&clks MPC512x_CLK_PSC11>,
485 <&clks MPC512x_CLK_PSC11_MCLK>;
486 clock-names = "ipg", "mclk";
380 }; 487 };
381 488
382 pscfifo@11f00 { 489 pscfifo@11f00 {
383 compatible = "fsl,mpc5121-psc-fifo"; 490 compatible = "fsl,mpc5121-psc-fifo";
384 reg = <0x11f00 0x100>; 491 reg = <0x11f00 0x100>;
385 interrupts = <40 0x8>; 492 interrupts = <40 0x8>;
493 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
494 clock-names = "ipg";
386 }; 495 };
387 496
388 dma0: dma@14000 { 497 dma0: dma@14000 {
@@ -400,6 +509,8 @@
400 #address-cells = <3>; 509 #address-cells = <3>;
401 #size-cells = <2>; 510 #size-cells = <2>;
402 #interrupt-cells = <1>; 511 #interrupt-cells = <1>;
512 clocks = <&clks MPC512x_CLK_PCI>;
513 clock-names = "ipg";
403 514
404 reg = <0x80008500 0x100 /* internal registers */ 515 reg = <0x80008500 0x100 /* internal registers */
405 0x80008300 0x8>; /* config space access registers */ 516 0x80008300 0x8>; /* config space access registers */
diff --git a/arch/powerpc/boot/dts/mpc5125twr.dts b/arch/powerpc/boot/dts/mpc5125twr.dts
index a618dfc13e4c..e4f297471748 100644
--- a/arch/powerpc/boot/dts/mpc5125twr.dts
+++ b/arch/powerpc/boot/dts/mpc5125twr.dts
@@ -12,6 +12,8 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15#include <dt-bindings/clock/mpc512x-clock.h>
16
15/dts-v1/; 17/dts-v1/;
16 18
17/ { 19/ {
@@ -54,6 +56,17 @@
54 reg = <0x30000000 0x08000>; // 32K at 0x30000000 56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
55 }; 57 };
56 58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 osc: osc {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <33000000>;
67 };
68 };
69
57 soc@80000000 { 70 soc@80000000 {
58 compatible = "fsl,mpc5121-immr"; 71 compatible = "fsl,mpc5121-immr";
59 #address-cells = <1>; 72 #address-cells = <1>;
@@ -87,9 +100,12 @@
87 reg = <0xe00 0x100>; 100 reg = <0xe00 0x100>;
88 }; 101 };
89 102
90 clock@f00 { // Clock control 103 clks: clock@f00 { // Clock control
91 compatible = "fsl,mpc5121-clock"; 104 compatible = "fsl,mpc5121-clock";
92 reg = <0xf00 0x100>; 105 reg = <0xf00 0x100>;
106 #clock-cells = <1>;
107 clocks = <&osc>;
108 clock-names = "osc";
93 }; 109 };
94 110
95 pmc@1000{ // Power Management Controller 111 pmc@1000{ // Power Management Controller
@@ -114,18 +130,33 @@
114 compatible = "fsl,mpc5121-mscan"; 130 compatible = "fsl,mpc5121-mscan";
115 interrupts = <12 0x8>; 131 interrupts = <12 0x8>;
116 reg = <0x1300 0x80>; 132 reg = <0x1300 0x80>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
138 clock-names = "ipg", "ips", "sys", "ref", "mclk";
117 }; 139 };
118 140
119 can@1380 { 141 can@1380 {
120 compatible = "fsl,mpc5121-mscan"; 142 compatible = "fsl,mpc5121-mscan";
121 interrupts = <13 0x8>; 143 interrupts = <13 0x8>;
122 reg = <0x1380 0x80>; 144 reg = <0x1380 0x80>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
149 <&clks MPC512x_CLK_MSCAN1_MCLK>;
150 clock-names = "ipg", "ips", "sys", "ref", "mclk";
123 }; 151 };
124 152
125 sdhc@1500 { 153 sdhc@1500 {
126 compatible = "fsl,mpc5121-sdhc"; 154 compatible = "fsl,mpc5121-sdhc";
127 interrupts = <8 0x8>; 155 interrupts = <8 0x8>;
128 reg = <0x1500 0x100>; 156 reg = <0x1500 0x100>;
157 clocks = <&clks MPC512x_CLK_IPS>,
158 <&clks MPC512x_CLK_SDHC>;
159 clock-names = "ipg", "per";
129 }; 160 };
130 161
131 i2c@1700 { 162 i2c@1700 {
@@ -134,6 +165,8 @@
134 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 165 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
135 reg = <0x1700 0x20>; 166 reg = <0x1700 0x20>;
136 interrupts = <0x9 0x8>; 167 interrupts = <0x9 0x8>;
168 clocks = <&clks MPC512x_CLK_I2C>;
169 clock-names = "ipg";
137 }; 170 };
138 171
139 i2c@1720 { 172 i2c@1720 {
@@ -142,6 +175,8 @@
142 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 175 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
143 reg = <0x1720 0x20>; 176 reg = <0x1720 0x20>;
144 interrupts = <0xa 0x8>; 177 interrupts = <0xa 0x8>;
178 clocks = <&clks MPC512x_CLK_I2C>;
179 clock-names = "ipg";
145 }; 180 };
146 181
147 i2c@1740 { 182 i2c@1740 {
@@ -150,6 +185,8 @@
150 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 185 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
151 reg = <0x1740 0x20>; 186 reg = <0x1740 0x20>;
152 interrupts = <0xb 0x8>; 187 interrupts = <0xb 0x8>;
188 clocks = <&clks MPC512x_CLK_I2C>;
189 clock-names = "ipg";
153 }; 190 };
154 191
155 i2ccontrol@1760 { 192 i2ccontrol@1760 {
@@ -161,6 +198,8 @@
161 compatible = "fsl,mpc5121-diu"; 198 compatible = "fsl,mpc5121-diu";
162 reg = <0x2100 0x100>; 199 reg = <0x2100 0x100>;
163 interrupts = <64 0x8>; 200 interrupts = <64 0x8>;
201 clocks = <&clks MPC512x_CLK_DIU>;
202 clock-names = "ipg";
164 }; 203 };
165 204
166 mdio@2800 { 205 mdio@2800 {
@@ -180,6 +219,8 @@
180 interrupts = <4 0x8>; 219 interrupts = <4 0x8>;
181 phy-handle = < &phy0 >; 220 phy-handle = < &phy0 >;
182 phy-connection-type = "rmii"; 221 phy-connection-type = "rmii";
222 clocks = <&clks MPC512x_CLK_FEC>;
223 clock-names = "per";
183 }; 224 };
184 225
185 // IO control 226 // IO control
@@ -200,6 +241,8 @@
200 interrupts = <43 0x8>; 241 interrupts = <43 0x8>;
201 dr_mode = "host"; 242 dr_mode = "host";
202 phy_type = "ulpi"; 243 phy_type = "ulpi";
244 clocks = <&clks MPC512x_CLK_USB1>;
245 clock-names = "ipg";
203 status = "disabled"; 246 status = "disabled";
204 }; 247 };
205 248
@@ -211,6 +254,9 @@
211 interrupts = <40 0x8>; 254 interrupts = <40 0x8>;
212 fsl,rx-fifo-size = <16>; 255 fsl,rx-fifo-size = <16>;
213 fsl,tx-fifo-size = <16>; 256 fsl,tx-fifo-size = <16>;
257 clocks = <&clks MPC512x_CLK_PSC1>,
258 <&clks MPC512x_CLK_PSC1_MCLK>;
259 clock-names = "ipg", "mclk";
214 }; 260 };
215 261
216 // PSC9 uart1 aka ttyPSC1 262 // PSC9 uart1 aka ttyPSC1
@@ -220,12 +266,17 @@
220 interrupts = <40 0x8>; 266 interrupts = <40 0x8>;
221 fsl,rx-fifo-size = <16>; 267 fsl,rx-fifo-size = <16>;
222 fsl,tx-fifo-size = <16>; 268 fsl,tx-fifo-size = <16>;
269 clocks = <&clks MPC512x_CLK_PSC9>,
270 <&clks MPC512x_CLK_PSC9_MCLK>;
271 clock-names = "ipg", "mclk";
223 }; 272 };
224 273
225 pscfifo@11f00 { 274 pscfifo@11f00 {
226 compatible = "fsl,mpc5121-psc-fifo"; 275 compatible = "fsl,mpc5121-psc-fifo";
227 reg = <0x11f00 0x100>; 276 reg = <0x11f00 0x100>;
228 interrupts = <40 0x8>; 277 interrupts = <40 0x8>;
278 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
279 clock-names = "ipg";
229 }; 280 };
230 281
231 dma@14000 { 282 dma@14000 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 17:20:54 -0500