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authorJeremy McNicoll <jeremy.mcnicoll@windriver.com>2008-05-05 18:17:24 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-05-13 09:53:48 -0400
commitbfd123bf91704b88093673e615cc93329f820ab4 (patch)
treeec9080bdaaa6668fe294f1752400c73d00f55646 /arch/powerpc/boot
parent73f5b8f942d6a2f178061dbbf9bcc54ca68ddf39 (diff)
[POWERPC] 85xx: SBC8548 - Add flash support and HW Rev reporting
The following adds local bus, flash and MTD partition nodes for sbc8548. As well, a compatible field for the soc node, so that of_platform_bus_probe() will pick it up. Something that is provided through this newly added epld node is the Hardware Revision which is now being utilized. Signed-off-by: Jeremy McNicoll <jeremy.mcnicoll@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts94
1 files changed, 94 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index b86e65d926c1..22d967178fe9 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -52,6 +52,99 @@
52 reg = <0x00000000 0x10000000>; 52 reg = <0x00000000 0x10000000>;
53 }; 53 };
54 54
55 localbus@e0000000 {
56 #address-cells = <2>;
57 #size-cells = <1>;
58 compatible = "simple-bus";
59 reg = <0xe0000000 0x5000>;
60 interrupt-parent = <&mpic>;
61
62 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
63 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
64 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
65 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
66 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/
67
68
69 flash@0,0 {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 compatible = "cfi-flash";
73 reg = <0x0 0x0 0x800000>;
74 bank-width = <1>;
75 device-width = <1>;
76 partition@0x0 {
77 label = "space";
78 reg = <0x00000000 0x00100000>;
79 };
80 partition@0x100000 {
81 label = "bootloader";
82 reg = <0x00100000 0x00700000>;
83 read-only;
84 };
85 };
86
87 epld@5,0 {
88 compatible = "wrs,epld-localbus";
89 #address-cells = <2>;
90 #size-cells = <1>;
91 reg = <0x5 0x0 0x00b10000>;
92 ranges = <
93 0x0 0x0 0x5 0x000000 0x1fff /* LED */
94 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
95 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
96 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
97 >;
98
99 led@0,0 {
100 compatible = "led";
101 reg = <0x0 0x0 0x1fff>;
102 };
103
104 switches@1,0 {
105 compatible = "switches";
106 reg = <0x1 0x0 0x1fff>;
107 };
108
109 hw-rev@3,0 {
110 compatible = "hw-rev";
111 reg = <0x3 0x0 0x1fff>;
112 };
113
114 eeprom@b,0 {
115 compatible = "eeprom";
116 reg = <0xb 0 0x1fff>;
117 };
118
119 };
120
121 alt-flash@6,0 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 reg = <0x6 0x0 0x04000000>;
125 compatible = "cfi-flash";
126 bank-width = <4>;
127 device-width = <1>;
128 partition@0x0 {
129 label = "bootloader";
130 reg = <0x00000000 0x00100000>;
131 read-only;
132 };
133 partition@0x00100000 {
134 label = "file-system";
135 reg = <0x00100000 0x01f00000>;
136 };
137 partition@0x02000000 {
138 label = "boot-config";
139 reg = <0x02000000 0x00100000>;
140 };
141 partition@0x02100000 {
142 label = "space";
143 reg = <0x02100000 0x01f00000>;
144 };
145 };
146 };
147
55 soc8548@e0000000 { 148 soc8548@e0000000 {
56 #address-cells = <1>; 149 #address-cells = <1>;
57 #size-cells = <1>; 150 #size-cells = <1>;
@@ -59,6 +152,7 @@
59 ranges = <0x00000000 0xe0000000 0x00100000>; 152 ranges = <0x00000000 0xe0000000 0x00100000>;
60 reg = <0xe0000000 0x00001000>; // CCSRBAR 153 reg = <0xe0000000 0x00001000>; // CCSRBAR
61 bus-frequency = <0>; 154 bus-frequency = <0>;
155 compatible = "simple-bus";
62 156
63 memory-controller@2000 { 157 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller"; 158 compatible = "fsl,8548-memory-controller";