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authors.hauer@pengutronix.de <s.hauer@pengutronix.de>2008-04-25 09:48:05 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-04-29 09:17:12 -0400
commit106757b38fffbe1f015b10a6d4a4f92e8a3881b9 (patch)
tree4d4321ba1c6e43edd7d2f7474d7bfe90040918c2 /arch/powerpc/boot
parent3cd2550c736688c7f2651134e08bd5b5db5bed70 (diff)
[POWERPC] mpc5200: add Phytec pcm030 board support
Add board support for the Phytec pcm030 mpc5200b based board. It does not need any platform specific fixups and as such is handled as a mpc5200 simple platform. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts363
1 files changed, 363 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
new file mode 100644
index 000000000000..7c1bb952360c
--- /dev/null
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -0,0 +1,363 @@
1/*
2 * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
3 *
4 * Copyright 2006 Pengutronix
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Copyright 2007 Pengutronix
7 * Juergen Beisert <j.beisert@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18 model = "phytec,pcm030";
19 compatible = "phytec,pcm030";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */
33 i-cache-size = <0x4000>; /* L1, 16K */
34 timebase-frequency = <0>; /* From Bootloader */
35 bus-frequency = <0>; /* From Bootloader */
36 clock-frequency = <0>; /* From Bootloader */
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */
51 system-frequency = <0>; /* From bootloader */
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { /* General Purpose Timer */
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt;
74 };
75
76 timer@610 { /* General Purpose Timer */
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>;
81 interrupt-parent = <&mpc5200_pic>;
82 };
83
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller;
91 #gpio-cells = <2>;
92 };
93
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller;
101 #gpio-cells = <2>;
102 };
103
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller;
111 #gpio-cells = <2>;
112 };
113
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller;
131 #gpio-cells = <2>;
132 };
133
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller;
141 #gpio-cells = <2>;
142 };
143
144 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 device_type = "rtc";
147 reg = <0x800 0x100>;
148 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
149 interrupt-parent = <&mpc5200_pic>;
150 };
151
152 can@900 {
153 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
154 cell-index = <0>;
155 interrupts = <0x2 0x11 0x0>;
156 interrupt-parent = <&mpc5200_pic>;
157 reg = <0x900 0x80>;
158 };
159
160 can@980 {
161 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
162 cell-index = <1>;
163 interrupts = <0x2 0x12 0x0>;
164 interrupt-parent = <&mpc5200_pic>;
165 reg = <0x980 0x80>;
166 };
167
168 gpio_simple: gpio@b00 {
169 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
170 reg = <0xb00 0x40>;
171 interrupts = <0x1 0x7 0x0>;
172 interrupt-parent = <&mpc5200_pic>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 };
176
177 gpio_wkup: gpio-wkup@c00 {
178 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
179 reg = <0xc00 0x40>;
180 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
181 interrupt-parent = <&mpc5200_pic>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 };
185
186 spi@f00 {
187 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
188 reg = <0xf00 0x20>;
189 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
190 interrupt-parent = <&mpc5200_pic>;
191 };
192
193 usb@1000 {
194 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
195 reg = <0x1000 0xff>;
196 interrupts = <0x2 0x6 0x0>;
197 interrupt-parent = <&mpc5200_pic>;
198 };
199
200 dma-controller@1200 {
201 device_type = "dma-controller";
202 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
203 reg = <0x1200 0x80>;
204 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
205 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
206 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
207 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
208 interrupt-parent = <&mpc5200_pic>;
209 };
210
211 xlb@1f00 {
212 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
213 reg = <0x1f00 0x100>;
214 };
215
216 ac97@2000 { /* PSC1 in ac97 mode */
217 device_type = "sound";
218 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
219 cell-index = <0>;
220 reg = <0x2000 0x100>;
221 interrupts = <0x2 0x2 0x0>;
222 interrupt-parent = <&mpc5200_pic>;
223 };
224
225 /* PSC2 port is used by CAN1/2 */
226
227 serial@2400 { /* PSC3 in UART mode */
228 device_type = "serial";
229 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
230 port-number = <0>;
231 cell-index = <2>;
232 reg = <0x2400 0x100>;
233 interrupts = <0x2 0x3 0x0>;
234 interrupt-parent = <&mpc5200_pic>;
235 };
236
237 /* PSC4 is ??? */
238
239 /* PSC5 is ??? */
240
241 serial@2c00 { /* PSC6 in UART mode */
242 device_type = "serial";
243 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
244 port-number = <1>;
245 cell-index = <5>;
246 reg = <0x2c00 0x100>;
247 interrupts = <0x2 0x4 0x0>;
248 interrupt-parent = <&mpc5200_pic>;
249 };
250
251 ethernet@3000 {
252 device_type = "network";
253 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
254 reg = <0x3000 0x400>;
255 local-mac-address = [00 00 00 00 00 00];
256 interrupts = <0x2 0x5 0x0>;
257 interrupt-parent = <&mpc5200_pic>;
258 phy-handle = <&phy0>;
259 };
260
261 mdio@3000 {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
265 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
266 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
267 interrupt-parent = <&mpc5200_pic>;
268
269 phy0:ethernet-phy@0 {
270 device_type = "ethernet-phy";
271 reg = <0x0>;
272 };
273 };
274
275 ata@3a00 {
276 device_type = "ata";
277 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
278 reg = <0x3a00 0x100>;
279 interrupts = <0x2 0x7 0x0>;
280 interrupt-parent = <&mpc5200_pic>;
281 };
282
283 i2c@3d00 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
287 cell-index = <0>;
288 reg = <0x3d00 0x40>;
289 interrupts = <0x2 0xf 0x0>;
290 interrupt-parent = <&mpc5200_pic>;
291 fsl5200-clocking;
292 };
293
294 i2c@3d40 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
298 cell-index = <1>;
299 reg = <0x3d40 0x40>;
300 interrupts = <0x2 0x10 0x0>;
301 interrupt-parent = <&mpc5200_pic>;
302 fsl5200-clocking;
303 rtc@51 {
304 device_type = "rtc";
305 compatible = "nxp,pcf8563";
306 reg = <0x51>;
307 };
308 /* FIXME: EEPROM */
309 };
310
311 sram@8000 {
312 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
313 reg = <0x8000 0x4000>;
314 };
315
316 /* This is only an example device to show the usage of gpios. It maps all available
317 * gpios to the "gpio-provider" device.
318 */
319 gpio {
320 compatible = "gpio-provider";
321
322 /* mpc52xx exp.con patchfield */
323 gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
324 &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
325 &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
326 &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
327 &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
328 &gpt2 0 0 /* timer2 12d x4-4 */
329 &gpt3 0 0 /* timer3 13d x6-4 */
330 &gpt4 0 0 /* timer4 61c x2-16 */
331 &gpt5 0 0 /* timer5 44c x7-11 */
332 &gpt6 0 0 /* timer6 60c x8-15 */
333 &gpt7 0 0 /* timer7 36a x17-9 */
334 >;
335 };
336 };
337
338 pci@f0000d00 {
339 #interrupt-cells = <1>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 device_type = "pci";
343 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
344 reg = <0xf0000d00 0x100>;
345 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
346 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
347 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
348 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
349 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
350
351 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
352 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
353 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
354 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
355 clock-frequency = <0>; // From boot loader
356 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
357 interrupt-parent = <&mpc5200_pic>;
358 bus-range = <0 0>;
359 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
360 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
361 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;
362 };
363};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 12:26:25 -0500