diff options
author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-07-30 22:59:07 -0400 |
---|---|---|
committer | Scott Wood <scottwood@freescale.com> | 2013-10-28 22:11:14 -0400 |
commit | 0e3d4373b8a7757a8f5187f5cabafb6aceff469b (patch) | |
tree | 74108e69667ae0866e066fc63f86f9d10b039793 /arch/powerpc/boot | |
parent | 682775b8de995d97956447730c04d2ff978d4e13 (diff) |
powerpc/dts: fix sRIO error interrupt for b4860
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r-- | arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index e5cf6c81dd66..981397518fc6 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | &rio { | 42 | &rio { |
43 | compatible = "fsl,srio"; | 43 | compatible = "fsl,srio"; |
44 | interrupts = <16 2 1 11>; | 44 | interrupts = <16 2 1 20>; |
45 | #address-cells = <2>; | 45 | #address-cells = <2>; |
46 | #size-cells = <2>; | 46 | #size-cells = <2>; |
47 | fsl,iommu-parent = <&pamu0>; | 47 | fsl,iommu-parent = <&pamu0>; |