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authorNate Case <ncase@xes-inc.com>2009-06-11 15:42:59 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-06-15 23:15:16 -0400
commit317bf653a6700b0ae34cef5028b287d5205bdaf1 (patch)
tree936415635f461b6065c13806f876e134c2a90127 /arch/powerpc/boot/dts
parent3038acf9091ff265609af3524ed94cce797d8485 (diff)
powerpc/85xx: Add dts files for X-ES MPC85xx boards
Add device tree source files for various MPC85xx boards from Extreme Engineering Solutions. Supported boards include XPedite5370, XPedite5200, XPedite5301, XPedite5330, and XCalibur1501. Signed-off-by: Nate Case <ncase@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/xcalibur1501.dts696
-rw-r--r--arch/powerpc/boot/dts/xpedite5200.dts466
-rw-r--r--arch/powerpc/boot/dts/xpedite5200_xmon.dts506
-rw-r--r--arch/powerpc/boot/dts/xpedite5301.dts640
-rw-r--r--arch/powerpc/boot/dts/xpedite5330.dts707
-rw-r--r--arch/powerpc/boot/dts/xpedite5370.dts638
6 files changed, 3653 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
new file mode 100644
index 000000000000..ac0a617b4299
--- /dev/null
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -0,0 +1,696 @@
1/*
2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4 *
5 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13/ {
14 model = "xes,xcalibur1501";
15 compatible = "xes,xcalibur1501", "xes,MPC8572";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8572@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
44 };
45
46 PowerPC,8572@1 {
47 device_type = "cpu";
48 reg = <0x1>;
49 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
55 clock-frequency = <0>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 memory {
61 device_type = "memory";
62 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
63 };
64
65 localbus@ef005000 {
66 #address-cells = <2>;
67 #size-cells = <1>;
68 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
69 reg = <0 0xef005000 0 0x1000>;
70 interrupts = <19 2>;
71 interrupt-parent = <&mpic>;
72 /* Local bus region mappings */
73 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
74 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
75 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
76 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
77 4 0 0 0xe9000000 0x100000>; /* CS4: USB */
78
79 nor-boot@0,0 {
80 compatible = "amd,s29gl01gp", "cfi-flash";
81 bank-width = <2>;
82 reg = <0 0 0x8000000>; /* 128MB */
83 #address-cells = <1>;
84 #size-cells = <1>;
85 partition@0 {
86 label = "Primary user space";
87 reg = <0x00000000 0x6f00000>; /* 111 MB */
88 };
89 partition@6f00000 {
90 label = "Primary kernel";
91 reg = <0x6f00000 0x1000000>; /* 16 MB */
92 };
93 partition@7f00000 {
94 label = "Primary DTB";
95 reg = <0x7f00000 0x40000>; /* 256 KB */
96 };
97 partition@7f40000 {
98 label = "Primary U-Boot environment";
99 reg = <0x7f40000 0x40000>; /* 256 KB */
100 };
101 partition@7f80000 {
102 label = "Primary U-Boot";
103 reg = <0x7f80000 0x80000>; /* 512 KB */
104 read-only;
105 };
106 };
107
108 nor-alternate@1,0 {
109 compatible = "amd,s29gl01gp", "cfi-flash";
110 bank-width = <2>;
111 //reg = <0xf0000000 0x08000000>; /* 128MB */
112 reg = <1 0 0x8000000>; /* 128MB */
113 #address-cells = <1>;
114 #size-cells = <1>;
115 partition@0 {
116 label = "Secondary user space";
117 reg = <0x00000000 0x6f00000>; /* 111 MB */
118 };
119 partition@6f00000 {
120 label = "Secondary kernel";
121 reg = <0x6f00000 0x1000000>; /* 16 MB */
122 };
123 partition@7f00000 {
124 label = "Secondary DTB";
125 reg = <0x7f00000 0x40000>; /* 256 KB */
126 };
127 partition@7f40000 {
128 label = "Secondary U-Boot environment";
129 reg = <0x7f40000 0x40000>; /* 256 KB */
130 };
131 partition@7f80000 {
132 label = "Secondary U-Boot";
133 reg = <0x7f80000 0x80000>; /* 512 KB */
134 read-only;
135 };
136 };
137
138 nand@2,0 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 /*
142 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
143 * Micron MT29F8G08DAA (2x 512 MB), or Micron
144 * MT29F16G08FAA (2x 1 GB), depending on the build
145 * configuration
146 */
147 compatible = "fsl,mpc8572-fcm-nand",
148 "fsl,elbc-fcm-nand";
149 reg = <2 0 0x40000>;
150 /* U-Boot should fix this up if chip size > 1 GB */
151 partition@0 {
152 label = "NAND Filesystem";
153 reg = <0 0x40000000>;
154 };
155 };
156
157 usb@4,0 {
158 compatible = "nxp,usb-isp1761";
159 reg = <4 0 0x100000>;
160 bus-width = <32>;
161 interrupt-parent = <&mpic>;
162 interrupts = <10 1>;
163 };
164 };
165
166 soc8572@ef000000 {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 device_type = "soc";
170 compatible = "fsl,mpc8572-immr", "simple-bus";
171 ranges = <0x0 0 0xef000000 0x100000>;
172 bus-frequency = <0>; // Filled out by uboot.
173
174 ecm-law@0 {
175 compatible = "fsl,ecm-law";
176 reg = <0x0 0x1000>;
177 fsl,num-laws = <12>;
178 };
179
180 ecm@1000 {
181 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
182 reg = <0x1000 0x1000>;
183 interrupts = <17 2>;
184 interrupt-parent = <&mpic>;
185 };
186
187 memory-controller@2000 {
188 compatible = "fsl,mpc8572-memory-controller";
189 reg = <0x2000 0x1000>;
190 interrupt-parent = <&mpic>;
191 interrupts = <18 2>;
192 };
193
194 memory-controller@6000 {
195 compatible = "fsl,mpc8572-memory-controller";
196 reg = <0x6000 0x1000>;
197 interrupt-parent = <&mpic>;
198 interrupts = <18 2>;
199 };
200
201 L2: l2-cache-controller@20000 {
202 compatible = "fsl,mpc8572-l2-cache-controller";
203 reg = <0x20000 0x1000>;
204 cache-line-size = <32>; // 32 bytes
205 cache-size = <0x100000>; // L2, 1M
206 interrupt-parent = <&mpic>;
207 interrupts = <16 2>;
208 };
209
210 i2c@3000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <0>;
214 compatible = "fsl-i2c";
215 reg = <0x3000 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219
220 temp-sensor@48 {
221 compatible = "dallas,ds1631", "dallas,ds1621";
222 reg = <0x48>;
223 };
224
225 temp-sensor@4c {
226 compatible = "adi,adt7461";
227 reg = <0x4c>;
228 };
229
230 cpu-supervisor@51 {
231 compatible = "dallas,ds4510";
232 reg = <0x51>;
233 };
234
235 eeprom@54 {
236 compatible = "atmel,at24c128b";
237 reg = <0x54>;
238 };
239
240 rtc@68 {
241 compatible = "stm,m41t00",
242 "dallas,ds1338";
243 reg = <0x68>;
244 };
245
246 pcie-switch@6a {
247 compatible = "plx,pex8648";
248 reg = <0x6a>;
249 };
250
251 /* On-board signals for VID, flash, serial */
252 gpio1: gpio@18 {
253 compatible = "nxp,pca9557";
254 reg = <0x18>;
255 #gpio-cells = <2>;
256 gpio-controller;
257 polarity = <0x00>;
258 };
259
260 /* PMC0/XMC0 signals */
261 gpio2: gpio@1c {
262 compatible = "nxp,pca9557";
263 reg = <0x1c>;
264 #gpio-cells = <2>;
265 gpio-controller;
266 polarity = <0x00>;
267 };
268
269 /* PMC1/XMC1 signals */
270 gpio3: gpio@1d {
271 compatible = "nxp,pca9557";
272 reg = <0x1d>;
273 #gpio-cells = <2>;
274 gpio-controller;
275 polarity = <0x00>;
276 };
277
278 /* CompactPCI signals (sysen, GA[4:0]) */
279 gpio4: gpio@1e {
280 compatible = "nxp,pca9557";
281 reg = <0x1e>;
282 #gpio-cells = <2>;
283 gpio-controller;
284 polarity = <0x00>;
285 };
286
287 /* CompactPCI J5 GPIO and FAL/DEG/PRST */
288 gpio5: gpio@1f {
289 compatible = "nxp,pca9557";
290 reg = <0x1f>;
291 #gpio-cells = <2>;
292 gpio-controller;
293 polarity = <0x00>;
294 };
295 };
296
297 i2c@3100 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 cell-index = <1>;
301 compatible = "fsl-i2c";
302 reg = <0x3100 0x100>;
303 interrupts = <43 2>;
304 interrupt-parent = <&mpic>;
305 dfsrr;
306 };
307
308 dma@c300 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
312 reg = <0xc300 0x4>;
313 ranges = <0x0 0xc100 0x200>;
314 cell-index = <1>;
315 dma-channel@0 {
316 compatible = "fsl,mpc8572-dma-channel",
317 "fsl,eloplus-dma-channel";
318 reg = <0x0 0x80>;
319 cell-index = <0>;
320 interrupt-parent = <&mpic>;
321 interrupts = <76 2>;
322 };
323 dma-channel@80 {
324 compatible = "fsl,mpc8572-dma-channel",
325 "fsl,eloplus-dma-channel";
326 reg = <0x80 0x80>;
327 cell-index = <1>;
328 interrupt-parent = <&mpic>;
329 interrupts = <77 2>;
330 };
331 dma-channel@100 {
332 compatible = "fsl,mpc8572-dma-channel",
333 "fsl,eloplus-dma-channel";
334 reg = <0x100 0x80>;
335 cell-index = <2>;
336 interrupt-parent = <&mpic>;
337 interrupts = <78 2>;
338 };
339 dma-channel@180 {
340 compatible = "fsl,mpc8572-dma-channel",
341 "fsl,eloplus-dma-channel";
342 reg = <0x180 0x80>;
343 cell-index = <3>;
344 interrupt-parent = <&mpic>;
345 interrupts = <79 2>;
346 };
347 };
348
349 dma@21300 {
350 #address-cells = <1>;
351 #size-cells = <1>;
352 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
353 reg = <0x21300 0x4>;
354 ranges = <0x0 0x21100 0x200>;
355 cell-index = <0>;
356 dma-channel@0 {
357 compatible = "fsl,mpc8572-dma-channel",
358 "fsl,eloplus-dma-channel";
359 reg = <0x0 0x80>;
360 cell-index = <0>;
361 interrupt-parent = <&mpic>;
362 interrupts = <20 2>;
363 };
364 dma-channel@80 {
365 compatible = "fsl,mpc8572-dma-channel",
366 "fsl,eloplus-dma-channel";
367 reg = <0x80 0x80>;
368 cell-index = <1>;
369 interrupt-parent = <&mpic>;
370 interrupts = <21 2>;
371 };
372 dma-channel@100 {
373 compatible = "fsl,mpc8572-dma-channel",
374 "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,mpc8572-dma-channel",
382 "fsl,eloplus-dma-channel";
383 reg = <0x180 0x80>;
384 cell-index = <3>;
385 interrupt-parent = <&mpic>;
386 interrupts = <23 2>;
387 };
388 };
389
390 /* eTSEC 1 front panel 0 */
391 enet0: ethernet@24000 {
392 #address-cells = <1>;
393 #size-cells = <1>;
394 cell-index = <0>;
395 device_type = "network";
396 model = "eTSEC";
397 compatible = "gianfar";
398 reg = <0x24000 0x1000>;
399 ranges = <0x0 0x24000 0x1000>;
400 local-mac-address = [ 00 00 00 00 00 00 ];
401 interrupts = <29 2 30 2 34 2>;
402 interrupt-parent = <&mpic>;
403 tbi-handle = <&tbi0>;
404 phy-handle = <&phy0>;
405 phy-connection-type = "sgmii";
406
407 mdio@520 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "fsl,gianfar-mdio";
411 reg = <0x520 0x20>;
412
413 phy0: ethernet-phy@1 {
414 interrupt-parent = <&mpic>;
415 interrupts = <4 1>;
416 reg = <0x1>;
417 };
418 phy1: ethernet-phy@2 {
419 interrupt-parent = <&mpic>;
420 interrupts = <4 1>;
421 reg = <0x2>;
422 };
423 phy2: ethernet-phy@3 {
424 interrupt-parent = <&mpic>;
425 interrupts = <5 1>;
426 reg = <0x3>;
427 };
428 phy3: ethernet-phy@4 {
429 interrupt-parent = <&mpic>;
430 interrupts = <5 1>;
431 reg = <0x4>;
432 };
433 tbi0: tbi-phy@11 {
434 reg = <0x11>;
435 device_type = "tbi-phy";
436 };
437 };
438 };
439
440 /* eTSEC 2 front panel 1 */
441 enet1: ethernet@25000 {
442 #address-cells = <1>;
443 #size-cells = <1>;
444 cell-index = <1>;
445 device_type = "network";
446 model = "eTSEC";
447 compatible = "gianfar";
448 reg = <0x25000 0x1000>;
449 ranges = <0x0 0x25000 0x1000>;
450 local-mac-address = [ 00 00 00 00 00 00 ];
451 interrupts = <35 2 36 2 40 2>;
452 interrupt-parent = <&mpic>;
453 tbi-handle = <&tbi1>;
454 phy-handle = <&phy1>;
455 phy-connection-type = "sgmii";
456
457 mdio@520 {
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "fsl,gianfar-tbi";
461 reg = <0x520 0x20>;
462
463 tbi1: tbi-phy@11 {
464 reg = <0x11>;
465 device_type = "tbi-phy";
466 };
467 };
468 };
469
470 /* eTSEC 3 PICMG2.16 backplane port 0 */
471 enet2: ethernet@26000 {
472 #address-cells = <1>;
473 #size-cells = <1>;
474 cell-index = <2>;
475 device_type = "network";
476 model = "eTSEC";
477 compatible = "gianfar";
478 reg = <0x26000 0x1000>;
479 ranges = <0x0 0x26000 0x1000>;
480 local-mac-address = [ 00 00 00 00 00 00 ];
481 interrupts = <31 2 32 2 33 2>;
482 interrupt-parent = <&mpic>;
483 tbi-handle = <&tbi2>;
484 phy-handle = <&phy2>;
485 phy-connection-type = "sgmii";
486
487 mdio@520 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "fsl,gianfar-tbi";
491 reg = <0x520 0x20>;
492
493 tbi2: tbi-phy@11 {
494 reg = <0x11>;
495 device_type = "tbi-phy";
496 };
497 };
498 };
499
500 /* eTSEC 4 PICMG2.16 backplane port 1 */
501 enet3: ethernet@27000 {
502 #address-cells = <1>;
503 #size-cells = <1>;
504 cell-index = <3>;
505 device_type = "network";
506 model = "eTSEC";
507 compatible = "gianfar";
508 reg = <0x27000 0x1000>;
509 ranges = <0x0 0x27000 0x1000>;
510 local-mac-address = [ 00 00 00 00 00 00 ];
511 interrupts = <37 2 38 2 39 2>;
512 interrupt-parent = <&mpic>;
513 tbi-handle = <&tbi3>;
514 phy-handle = <&phy3>;
515 phy-connection-type = "sgmii";
516
517 mdio@520 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 compatible = "fsl,gianfar-tbi";
521 reg = <0x520 0x20>;
522
523 tbi3: tbi-phy@11 {
524 reg = <0x11>;
525 device_type = "tbi-phy";
526 };
527 };
528 };
529
530 /* UART0 */
531 serial0: serial@4500 {
532 cell-index = <0>;
533 device_type = "serial";
534 compatible = "ns16550";
535 reg = <0x4500 0x100>;
536 clock-frequency = <0>;
537 interrupts = <42 2>;
538 interrupt-parent = <&mpic>;
539 };
540
541 /* UART1 */
542 serial1: serial@4600 {
543 cell-index = <1>;
544 device_type = "serial";
545 compatible = "ns16550";
546 reg = <0x4600 0x100>;
547 clock-frequency = <0>;
548 interrupts = <42 2>;
549 interrupt-parent = <&mpic>;
550 };
551
552 global-utilities@e0000 { //global utilities block
553 compatible = "fsl,mpc8572-guts";
554 reg = <0xe0000 0x1000>;
555 fsl,has-rstcr;
556 };
557
558 msi@41600 {
559 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
560 reg = <0x41600 0x80>;
561 msi-available-ranges = <0 0x100>;
562 interrupts = <
563 0xe0 0
564 0xe1 0
565 0xe2 0
566 0xe3 0
567 0xe4 0
568 0xe5 0
569 0xe6 0
570 0xe7 0>;
571 interrupt-parent = <&mpic>;
572 };
573
574 crypto@30000 {
575 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
576 "fsl,sec2.1", "fsl,sec2.0";
577 reg = <0x30000 0x10000>;
578 interrupts = <45 2 58 2>;
579 interrupt-parent = <&mpic>;
580 fsl,num-channels = <4>;
581 fsl,channel-fifo-len = <24>;
582 fsl,exec-units-mask = <0x9fe>;
583 fsl,descriptor-types-mask = <0x3ab0ebf>;
584 };
585
586 mpic: pic@40000 {
587 interrupt-controller;
588 #address-cells = <0>;
589 #interrupt-cells = <2>;
590 reg = <0x40000 0x40000>;
591 compatible = "chrp,open-pic";
592 device_type = "open-pic";
593 };
594
595 gpio0: gpio@f000 {
596 compatible = "fsl,mpc8572-gpio";
597 reg = <0xf000 0x1000>;
598 interrupts = <47 2>;
599 interrupt-parent = <&mpic>;
600 #gpio-cells = <2>;
601 gpio-controller;
602 };
603
604 gpio-leds {
605 compatible = "gpio-leds";
606
607 heartbeat {
608 label = "Heartbeat";
609 gpios = <&gpio0 4 1>;
610 linux,default-trigger = "heartbeat";
611 };
612
613 yellow {
614 label = "Yellow";
615 gpios = <&gpio0 5 1>;
616 };
617
618 red {
619 label = "Red";
620 gpios = <&gpio0 6 1>;
621 };
622
623 green {
624 label = "Green";
625 gpios = <&gpio0 7 1>;
626 };
627 };
628
629 /* PME (pattern-matcher) */
630 pme@10000 {
631 compatible = "fsl,mpc8572-pme", "pme8572";
632 reg = <0x10000 0x5000>;
633 interrupts = <57 2 64 2 65 2 66 2 67 2>;
634 interrupt-parent = <&mpic>;
635 };
636
637 tlu@2f000 {
638 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
639 reg = <0x2f000 0x1000>;
640 interupts = <61 2 >;
641 interrupt-parent = <&mpic>;
642 };
643
644 tlu@15000 {
645 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
646 reg = <0x15000 0x1000>;
647 interupts = <75 2>;
648 interrupt-parent = <&mpic>;
649 };
650 };
651
652 /*
653 * PCI Express controller 3 @ ef008000 is not used.
654 * This would have been pci0 on other mpc85xx platforms.
655 *
656 * PCI Express controller 2 @ ef009000 is not used.
657 * This would have been pci1 on other mpc85xx platforms.
658 */
659
660 /* PCI Express controller 1, wired to PEX8648 PCIe switch */
661 pci2: pcie@ef00a000 {
662 compatible = "fsl,mpc8548-pcie";
663 device_type = "pci";
664 #interrupt-cells = <1>;
665 #size-cells = <2>;
666 #address-cells = <3>;
667 reg = <0 0xef00a000 0 0x1000>;
668 bus-range = <0 255>;
669 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
670 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
671 clock-frequency = <33333333>;
672 interrupt-parent = <&mpic>;
673 interrupts = <26 2>;
674 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
675 interrupt-map = <
676 /* IDSEL 0x0 */
677 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
678 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
679 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
680 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
681 >;
682 pcie@0 {
683 reg = <0x0 0x0 0x0 0x0 0x0>;
684 #size-cells = <2>;
685 #address-cells = <3>;
686 device_type = "pci";
687 ranges = <0x2000000 0x0 0x80000000
688 0x2000000 0x0 0x80000000
689 0x0 0x40000000
690
691 0x1000000 0x0 0x0
692 0x1000000 0x0 0x0
693 0x0 0x100000>;
694 };
695 };
696};
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
new file mode 100644
index 000000000000..a0cf53fbd55c
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -0,0 +1,466 @@
1/*
2 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
3 * Based on TQM8548 device tree
4 *
5 * XPedite5200 PrPMC/XMC module based on MPC8548E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "xes,xpedite5200";
16 compatible = "xes,xpedite5200", "xes,MPC8548";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8548@0 {
36 device_type = "cpu";
37 reg = <0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x0 0x0>; // Filled in by U-Boot
49 };
50
51 soc@ef000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xef000000 0x100000>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8548-immr", "simple-bus";
58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <12>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
72 memory-controller@2000 {
73 compatible = "fsl,mpc8548-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>;
77 };
78
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8548-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>; // 32 bytes
83 cache-size = <0x80000>; // L2, 512K
84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>;
86 };
87
88 /* On-card I2C */
89 i2c@3000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <0>;
93 compatible = "fsl-i2c";
94 reg = <0x3000 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98
99 /*
100 * Board GPIO:
101 * 0: BRD_CFG0 (1: P14 IO present)
102 * 1: BRD_CFG1 (1: FP ethernet present)
103 * 2: BRD_CFG2 (1: XMC IO present)
104 * 3: XMC root complex indicator
105 * 4: Flash boot device indicator
106 * 5: Flash write protect enable
107 * 6: PMC monarch indicator
108 * 7: PMC EREADY
109 */
110 gpio1: gpio@18 {
111 compatible = "nxp,pca9556";
112 reg = <0x18>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 polarity = <0x00>;
116 };
117
118 /* P14 GPIO */
119 gpio2: gpio@19 {
120 compatible = "nxp,pca9556";
121 reg = <0x19>;
122 #gpio-cells = <2>;
123 gpio-controller;
124 polarity = <0x00>;
125 };
126
127 eeprom@50 {
128 compatible = "atmel,at24c16";
129 reg = <0x50>;
130 };
131
132 rtc@68 {
133 compatible = "stm,m41t00",
134 "dallas,ds1338";
135 reg = <0x68>;
136 };
137
138 dtt@48 {
139 compatible = "maxim,max1237";
140 reg = <0x34>;
141 };
142 };
143
144 /* Off-card I2C */
145 i2c@3100 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 cell-index = <1>;
149 compatible = "fsl-i2c";
150 reg = <0x3100 0x100>;
151 interrupts = <43 2>;
152 interrupt-parent = <&mpic>;
153 dfsrr;
154 };
155
156 dma@21300 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
160 reg = <0x21300 0x4>;
161 ranges = <0x0 0x21100 0x200>;
162 cell-index = <0>;
163 dma-channel@0 {
164 compatible = "fsl,mpc8548-dma-channel",
165 "fsl,eloplus-dma-channel";
166 reg = <0x0 0x80>;
167 cell-index = <0>;
168 interrupt-parent = <&mpic>;
169 interrupts = <20 2>;
170 };
171 dma-channel@80 {
172 compatible = "fsl,mpc8548-dma-channel",
173 "fsl,eloplus-dma-channel";
174 reg = <0x80 0x80>;
175 cell-index = <1>;
176 interrupt-parent = <&mpic>;
177 interrupts = <21 2>;
178 };
179 dma-channel@100 {
180 compatible = "fsl,mpc8548-dma-channel",
181 "fsl,eloplus-dma-channel";
182 reg = <0x100 0x80>;
183 cell-index = <2>;
184 interrupt-parent = <&mpic>;
185 interrupts = <22 2>;
186 };
187 dma-channel@180 {
188 compatible = "fsl,mpc8548-dma-channel",
189 "fsl,eloplus-dma-channel";
190 reg = <0x180 0x80>;
191 cell-index = <3>;
192 interrupt-parent = <&mpic>;
193 interrupts = <23 2>;
194 };
195 };
196
197 /* eTSEC1: Front panel port 0 */
198 enet0: ethernet@24000 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 cell-index = <0>;
202 device_type = "network";
203 model = "eTSEC";
204 compatible = "gianfar";
205 reg = <0x24000 0x1000>;
206 ranges = <0x0 0x24000 0x1000>;
207 local-mac-address = [ 00 00 00 00 00 00 ];
208 interrupts = <29 2 30 2 34 2>;
209 interrupt-parent = <&mpic>;
210 tbi-handle = <&tbi0>;
211 phy-handle = <&phy0>;
212
213 mdio@520 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,gianfar-mdio";
217 reg = <0x520 0x20>;
218
219 phy0: ethernet-phy@1 {
220 interrupt-parent = <&mpic>;
221 interrupts = <8 1>;
222 reg = <0x1>;
223 };
224 phy1: ethernet-phy@2 {
225 interrupt-parent = <&mpic>;
226 interrupts = <8 1>;
227 reg = <0x2>;
228 };
229 phy2: ethernet-phy@3 {
230 interrupt-parent = <&mpic>;
231 interrupts = <8 1>;
232 reg = <0x3>;
233 };
234 phy3: ethernet-phy@4 {
235 interrupt-parent = <&mpic>;
236 interrupts = <8 1>;
237 reg = <0x4>;
238 };
239 tbi0: tbi-phy@11 {
240 reg = <0x11>;
241 device_type = "tbi-phy";
242 };
243 };
244 };
245
246 /* eTSEC2: Front panel port 1 */
247 enet1: ethernet@25000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <1>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x25000 0x1000>;
255 ranges = <0x0 0x25000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <35 2 36 2 40 2>;
258 interrupt-parent = <&mpic>;
259 tbi-handle = <&tbi1>;
260 phy-handle = <&phy1>;
261
262 mdio@520 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "fsl,gianfar-tbi";
266 reg = <0x520 0x20>;
267
268 tbi1: tbi-phy@11 {
269 reg = <0x11>;
270 device_type = "tbi-phy";
271 };
272 };
273 };
274
275 /* eTSEC3: Rear panel port 2 */
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288 tbi-handle = <&tbi2>;
289 phy-handle = <&phy2>;
290
291 mdio@520 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "fsl,gianfar-tbi";
295 reg = <0x520 0x20>;
296
297 tbi2: tbi-phy@11 {
298 reg = <0x11>;
299 device_type = "tbi-phy";
300 };
301 };
302 };
303
304 /* eTSEC4: Rear panel port 3 */
305 enet3: ethernet@27000 {
306 #address-cells = <1>;
307 #size-cells = <1>;
308 cell-index = <3>;
309 device_type = "network";
310 model = "eTSEC";
311 compatible = "gianfar";
312 reg = <0x27000 0x1000>;
313 ranges = <0x0 0x27000 0x1000>;
314 local-mac-address = [ 00 00 00 00 00 00 ];
315 interrupts = <37 2 38 2 39 2>;
316 interrupt-parent = <&mpic>;
317 tbi-handle = <&tbi3>;
318 phy-handle = <&phy3>;
319
320 mdio@520 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "fsl,gianfar-tbi";
324 reg = <0x520 0x20>;
325
326 tbi3: tbi-phy@11 {
327 reg = <0x11>;
328 device_type = "tbi-phy";
329 };
330 };
331 };
332
333 serial0: serial@4500 {
334 cell-index = <0>;
335 device_type = "serial";
336 compatible = "ns16550";
337 reg = <0x4500 0x100>;
338 clock-frequency = <0>;
339 current-speed = <115200>;
340 interrupts = <42 2>;
341 interrupt-parent = <&mpic>;
342 };
343
344 serial1: serial@4600 {
345 cell-index = <1>;
346 device_type = "serial";
347 compatible = "ns16550";
348 reg = <0x4600 0x100>;
349 clock-frequency = <0>;
350 current-speed = <115200>;
351 interrupts = <42 2>;
352 interrupt-parent = <&mpic>;
353 };
354
355 global-utilities@e0000 { // global utilities reg
356 compatible = "fsl,mpc8548-guts";
357 reg = <0xe0000 0x1000>;
358 fsl,has-rstcr;
359 };
360
361 mpic: pic@40000 {
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x40000 0x40000>;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 };
369 };
370
371 localbus@ef005000 {
372 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
373 "simple-bus";
374 #address-cells = <2>;
375 #size-cells = <1>;
376 reg = <0xef005000 0x100>; // BRx, ORx, etc.
377
378 ranges = <
379 0 0x0 0xfc000000 0x04000000 // NOR boot flash
380 1 0x0 0xf8000000 0x04000000 // NOR expansion flash
381 2 0x0 0xef800000 0x00010000 // NAND CE1
382 3 0x0 0xef840000 0x00010000 // NAND CE2
383 >;
384
385 nor-boot@0,0 {
386 #address-cells = <1>;
387 #size-cells = <1>;
388 compatible = "cfi-flash";
389 reg = <0 0x0 0x4000000>;
390 bank-width = <2>;
391
392 partition@0 {
393 label = "Primary OS";
394 reg = <0x00000000 0x180000>;
395 };
396 partition@180000 {
397 label = "Secondary OS";
398 reg = <0x00180000 0x180000>;
399 };
400 partition@300000 {
401 label = "User";
402 reg = <0x00300000 0x3c80000>;
403 };
404 partition@3f80000 {
405 label = "Boot firmware";
406 reg = <0x03f80000 0x80000>;
407 };
408 };
409
410 nor-alternate@1,0 {
411 #address-cells = <1>;
412 #size-cells = <1>;
413 compatible = "cfi-flash";
414 reg = <1 0x0 0x4000000>;
415 bank-width = <2>;
416
417 partition@0 {
418 label = "Filesystem";
419 reg = <0x00000000 0x3f80000>;
420 };
421 partition@3f80000 {
422 label = "Alternate boot firmware";
423 reg = <0x03f80000 0x80000>;
424 };
425 };
426
427 nand@2,0 {
428 #address-cells = <1>;
429 #size-cells = <1>;
430 compatible = "xes,address-ctl-nand";
431 reg = <2 0x0 0x10000>;
432 cle-line = <0x8>; /* CLE tied to A3 */
433 ale-line = <0x10>; /* ALE tied to A4 */
434
435 /* U-Boot should fix this up */
436 partition@0 {
437 label = "NAND Filesystem";
438 reg = <0 0x40000000>;
439 };
440 };
441 };
442
443 /* PMC interface */
444 pci0: pci@ef008000 {
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
449 device_type = "pci";
450 reg = <0xef008000 0x1000>;
451 clock-frequency = <33333333>;
452 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
453 interrupt-map = <
454 /* IDSEL */
455 0xe000 0 0 1 &mpic 2 1
456 0xe000 0 0 2 &mpic 3 1>;
457
458 interrupt-parent = <&mpic>;
459 interrupts = <24 2>;
460 bus-range = <0 0>;
461 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
462 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
463 };
464
465 /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
466};
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
new file mode 100644
index 000000000000..c5b29752651a
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -0,0 +1,506 @@
1/*
2 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
3 * Based on TQM8548 device tree
4 *
5 * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
6 * xMon boot loader memory map which differs from U-Boot's.
7 *
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "xes,xpedite5200";
17 compatible = "xes,xpedite5200", "xes,MPC8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 form-factor = "PMC/XMC";
21 boot-bank = <0x0>;
22
23 aliases {
24 ethernet0 = &enet0;
25 ethernet1 = &enet1;
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28
29 serial0 = &serial0;
30 serial1 = &serial1;
31 pci0 = &pci0;
32 pci1 = &pci1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 PowerPC,8548@0 {
40 device_type = "cpu";
41 reg = <0>;
42 d-cache-line-size = <32>; // 32 bytes
43 i-cache-line-size = <32>; // 32 bytes
44 d-cache-size = <0x8000>; // L1, 32K
45 i-cache-size = <0x8000>; // L1, 32K
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x0 0x0>; // Filled in by boot loader
53 };
54
55 soc@ef000000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 ranges = <0x0 0xef000000 0x100000>;
60 bus-frequency = <0>;
61 compatible = "fsl,mpc8548-immr", "simple-bus";
62
63 ecm-law@0 {
64 compatible = "fsl,ecm-law";
65 reg = <0x0 0x1000>;
66 fsl,num-laws = <12>;
67 };
68
69 ecm@1000 {
70 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
71 reg = <0x1000 0x1000>;
72 interrupts = <17 2>;
73 interrupt-parent = <&mpic>;
74 };
75
76 memory-controller@2000 {
77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>;
81 };
82
83 L2: l2-cache-controller@20000 {
84 compatible = "fsl,mpc8548-l2-cache-controller";
85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K
88 interrupt-parent = <&mpic>;
89 interrupts = <16 2>;
90 };
91
92 /* On-card I2C */
93 i2c@3000 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 cell-index = <0>;
97 compatible = "fsl-i2c";
98 reg = <0x3000 0x100>;
99 interrupts = <43 2>;
100 interrupt-parent = <&mpic>;
101 dfsrr;
102
103 /*
104 * Board GPIO:
105 * 0: BRD_CFG0 (1: P14 IO present)
106 * 1: BRD_CFG1 (1: FP ethernet present)
107 * 2: BRD_CFG2 (1: XMC IO present)
108 * 3: XMC root complex indicator
109 * 4: Flash boot device indicator
110 * 5: Flash write protect enable
111 * 6: PMC monarch indicator
112 * 7: PMC EREADY
113 */
114 gpio1: gpio@18 {
115 compatible = "nxp,pca9556";
116 reg = <0x18>;
117 #gpio-cells = <2>;
118 gpio-controller;
119 polarity = <0x00>;
120 };
121
122 /* P14 GPIO */
123 gpio2: gpio@19 {
124 compatible = "nxp,pca9556";
125 reg = <0x19>;
126 #gpio-cells = <2>;
127 gpio-controller;
128 polarity = <0x00>;
129 };
130
131 eeprom@50 {
132 compatible = "atmel,at24c16";
133 reg = <0x50>;
134 };
135
136 rtc@68 {
137 compatible = "stm,m41t00",
138 "dallas,ds1338";
139 reg = <0x68>;
140 };
141
142 dtt@48 {
143 compatible = "maxim,max1237";
144 reg = <0x34>;
145 };
146 };
147
148 /* Off-card I2C */
149 i2c@3100 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 cell-index = <1>;
153 compatible = "fsl-i2c";
154 reg = <0x3100 0x100>;
155 interrupts = <43 2>;
156 interrupt-parent = <&mpic>;
157 dfsrr;
158 };
159
160 dma@21300 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
164 reg = <0x21300 0x4>;
165 ranges = <0x0 0x21100 0x200>;
166 cell-index = <0>;
167 dma-channel@0 {
168 compatible = "fsl,mpc8548-dma-channel",
169 "fsl,eloplus-dma-channel";
170 reg = <0x0 0x80>;
171 cell-index = <0>;
172 interrupt-parent = <&mpic>;
173 interrupts = <20 2>;
174 };
175 dma-channel@80 {
176 compatible = "fsl,mpc8548-dma-channel",
177 "fsl,eloplus-dma-channel";
178 reg = <0x80 0x80>;
179 cell-index = <1>;
180 interrupt-parent = <&mpic>;
181 interrupts = <21 2>;
182 };
183 dma-channel@100 {
184 compatible = "fsl,mpc8548-dma-channel",
185 "fsl,eloplus-dma-channel";
186 reg = <0x100 0x80>;
187 cell-index = <2>;
188 interrupt-parent = <&mpic>;
189 interrupts = <22 2>;
190 };
191 dma-channel@180 {
192 compatible = "fsl,mpc8548-dma-channel",
193 "fsl,eloplus-dma-channel";
194 reg = <0x180 0x80>;
195 cell-index = <3>;
196 interrupt-parent = <&mpic>;
197 interrupts = <23 2>;
198 };
199 };
200
201 /* eTSEC1: Front panel port 0 */
202 enet0: ethernet@24000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 cell-index = <0>;
206 device_type = "network";
207 model = "eTSEC";
208 compatible = "gianfar";
209 reg = <0x24000 0x1000>;
210 ranges = <0x0 0x24000 0x1000>;
211 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <29 2 30 2 34 2>;
213 interrupt-parent = <&mpic>;
214 tbi-handle = <&tbi0>;
215 phy-handle = <&phy0>;
216
217 mdio@520 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,gianfar-mdio";
221 reg = <0x520 0x20>;
222
223 phy0: ethernet-phy@1 {
224 interrupt-parent = <&mpic>;
225 interrupts = <8 1>;
226 reg = <0x1>;
227 };
228 phy1: ethernet-phy@2 {
229 interrupt-parent = <&mpic>;
230 interrupts = <8 1>;
231 reg = <0x2>;
232 };
233 phy2: ethernet-phy@3 {
234 interrupt-parent = <&mpic>;
235 interrupts = <8 1>;
236 reg = <0x3>;
237 };
238 phy3: ethernet-phy@4 {
239 interrupt-parent = <&mpic>;
240 interrupts = <8 1>;
241 reg = <0x4>;
242 };
243 tbi0: tbi-phy@11 {
244 reg = <0x11>;
245 device_type = "tbi-phy";
246 };
247 };
248 };
249
250 /* eTSEC2: Front panel port 1 */
251 enet1: ethernet@25000 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 cell-index = <1>;
255 device_type = "network";
256 model = "eTSEC";
257 compatible = "gianfar";
258 reg = <0x25000 0x1000>;
259 ranges = <0x0 0x25000 0x1000>;
260 local-mac-address = [ 00 00 00 00 00 00 ];
261 interrupts = <35 2 36 2 40 2>;
262 interrupt-parent = <&mpic>;
263 tbi-handle = <&tbi1>;
264 phy-handle = <&phy1>;
265
266 mdio@520 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "fsl,gianfar-tbi";
270 reg = <0x520 0x20>;
271
272 tbi1: tbi-phy@11 {
273 reg = <0x11>;
274 device_type = "tbi-phy";
275 };
276 };
277 };
278
279 /* eTSEC3: Rear panel port 2 */
280 enet2: ethernet@26000 {
281 #address-cells = <1>;
282 #size-cells = <1>;
283 cell-index = <2>;
284 device_type = "network";
285 model = "eTSEC";
286 compatible = "gianfar";
287 reg = <0x26000 0x1000>;
288 ranges = <0x0 0x26000 0x1000>;
289 local-mac-address = [ 00 00 00 00 00 00 ];
290 interrupts = <31 2 32 2 33 2>;
291 interrupt-parent = <&mpic>;
292 tbi-handle = <&tbi2>;
293 phy-handle = <&phy2>;
294
295 mdio@520 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 compatible = "fsl,gianfar-tbi";
299 reg = <0x520 0x20>;
300
301 tbi2: tbi-phy@11 {
302 reg = <0x11>;
303 device_type = "tbi-phy";
304 };
305 };
306 };
307
308 /* eTSEC4: Rear panel port 3 */
309 enet3: ethernet@27000 {
310 #address-cells = <1>;
311 #size-cells = <1>;
312 cell-index = <3>;
313 device_type = "network";
314 model = "eTSEC";
315 compatible = "gianfar";
316 reg = <0x27000 0x1000>;
317 ranges = <0x0 0x27000 0x1000>;
318 local-mac-address = [ 00 00 00 00 00 00 ];
319 interrupts = <37 2 38 2 39 2>;
320 interrupt-parent = <&mpic>;
321 tbi-handle = <&tbi3>;
322 phy-handle = <&phy3>;
323
324 mdio@520 {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,gianfar-tbi";
328 reg = <0x520 0x20>;
329
330 tbi3: tbi-phy@11 {
331 reg = <0x11>;
332 device_type = "tbi-phy";
333 };
334 };
335 };
336
337 serial0: serial@4500 {
338 cell-index = <0>;
339 device_type = "serial";
340 compatible = "ns16550";
341 reg = <0x4500 0x100>;
342 clock-frequency = <0>;
343 current-speed = <9600>;
344 interrupts = <42 2>;
345 interrupt-parent = <&mpic>;
346 };
347
348 serial1: serial@4600 {
349 cell-index = <1>;
350 device_type = "serial";
351 compatible = "ns16550";
352 reg = <0x4600 0x100>;
353 clock-frequency = <0>;
354 current-speed = <9600>;
355 interrupts = <42 2>;
356 interrupt-parent = <&mpic>;
357 };
358
359 global-utilities@e0000 { // global utilities reg
360 compatible = "fsl,mpc8548-guts";
361 reg = <0xe0000 0x1000>;
362 fsl,has-rstcr;
363 };
364
365 mpic: pic@40000 {
366 interrupt-controller;
367 #address-cells = <0>;
368 #interrupt-cells = <2>;
369 reg = <0x40000 0x40000>;
370 compatible = "chrp,open-pic";
371 device_type = "open-pic";
372 };
373 };
374
375 localbus@ef005000 {
376 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
377 "simple-bus";
378 #address-cells = <2>;
379 #size-cells = <1>;
380 reg = <0xef005000 0x100>; // BRx, ORx, etc.
381
382 ranges = <
383 0 0x0 0xf8000000 0x08000000 // NOR boot flash
384 1 0x0 0xf0000000 0x08000000 // NOR expansion flash
385 2 0x0 0xe8000000 0x00010000 // NAND CE1
386 3 0x0 0xe8010000 0x00010000 // NAND CE2
387 >;
388
389 nor-boot@0,0 {
390 #address-cells = <1>;
391 #size-cells = <1>;
392 compatible = "cfi-flash";
393 reg = <0 0x0 0x4000000>;
394 bank-width = <2>;
395
396 partition@0 {
397 label = "Primary OS";
398 reg = <0x00000000 0x180000>;
399 };
400 partition@180000 {
401 label = "Secondary OS";
402 reg = <0x00180000 0x180000>;
403 };
404 partition@300000 {
405 label = "User";
406 reg = <0x00300000 0x3c80000>;
407 };
408 partition@3f80000 {
409 label = "Boot firmware";
410 reg = <0x03f80000 0x80000>;
411 };
412 };
413
414 nor-alternate@1,0 {
415 #address-cells = <1>;
416 #size-cells = <1>;
417 compatible = "cfi-flash";
418 reg = <1 0x0 0x4000000>;
419 bank-width = <2>;
420
421 partition@0 {
422 label = "Filesystem";
423 reg = <0x00000000 0x3f80000>;
424 };
425 partition@3f80000 {
426 label = "Alternate boot firmware";
427 reg = <0x03f80000 0x80000>;
428 };
429 };
430
431 nand@2,0 {
432 #address-cells = <1>;
433 #size-cells = <1>;
434 compatible = "xes,address-ctl-nand";
435 reg = <2 0x0 0x10000>;
436 cle-line = <0x8>; /* CLE tied to A3 */
437 ale-line = <0x10>; /* ALE tied to A4 */
438
439 partition@0 {
440 label = "NAND Filesystem";
441 reg = <0 0x40000000>;
442 };
443 };
444 };
445
446 /* PMC interface */
447 pci0: pci@ef008000 {
448 #interrupt-cells = <1>;
449 #size-cells = <2>;
450 #address-cells = <3>;
451 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
452 device_type = "pci";
453 reg = <0xef008000 0x1000>;
454 clock-frequency = <33333333>;
455 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
456 interrupt-map = <
457 /* IDSEL */
458 0xe000 0 0 1 &mpic 2 1
459 0xe000 0 0 2 &mpic 3 1>;
460
461 interrupt-parent = <&mpic>;
462 interrupts = <24 2>;
463 bus-range = <0 0>;
464 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
465 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
466 };
467
468 /* XMC PCIe */
469 pci1: pcie@ef00a000 {
470 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
471 interrupt-map = <
472 /* IDSEL 0x0 */
473 0x00000 0 0 1 &mpic 0 1
474 0x00000 0 0 2 &mpic 1 1
475 0x00000 0 0 3 &mpic 2 1
476 0x00000 0 0 4 &mpic 3 1>;
477
478 interrupt-parent = <&mpic>;
479 interrupts = <26 2>;
480 bus-range = <0 0xff>;
481 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
482 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
483 clock-frequency = <33333333>;
484 #interrupt-cells = <1>;
485 #size-cells = <2>;
486 #address-cells = <3>;
487 reg = <0xef00a000 0x1000>;
488 compatible = "fsl,mpc8548-pcie";
489 device_type = "pci";
490 pcie@0 {
491 reg = <0 0 0 0 0>;
492 #size-cells = <2>;
493 #address-cells = <3>;
494 device_type = "pci";
495 ranges = <0x02000000 0 0xc0000000 0x02000000 0
496 0xc0000000 0 0x20000000
497 0x01000000 0 0x00000000 0x01000000 0
498 0x00000000 0 0x08000000>;
499 };
500 };
501
502 /* Needed for dtbImage boot wrapper compatibility */
503 chosen {
504 linux,stdout-path = &serial0;
505 };
506};
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
new file mode 100644
index 000000000000..db7faf5ebb39
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -0,0 +1,640 @@
1/*
2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4 *
5 * XPedite5301 PMC/XMC module based on MPC8572E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13/ {
14 model = "xes,xpedite5301";
15 compatible = "xes,xpedite5301", "xes,MPC8572";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "PMC/XMC";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8572@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46
47 PowerPC,8572@1 {
48 device_type = "cpu";
49 reg = <0x1>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
54 timebase-frequency = <0>;
55 bus-frequency = <0>;
56 clock-frequency = <0>;
57 next-level-cache = <&L2>;
58 };
59 };
60
61 memory {
62 device_type = "memory";
63 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
64 };
65
66 localbus@ef005000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0 0xef005000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73 /* Local bus region mappings */
74 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
75 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
76 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
77 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
78
79 nor-boot@0,0 {
80 compatible = "amd,s29gl01gp", "cfi-flash";
81 bank-width = <2>;
82 reg = <0 0 0x8000000>; /* 128MB */
83 #address-cells = <1>;
84 #size-cells = <1>;
85 partition@0 {
86 label = "Primary user space";
87 reg = <0x00000000 0x6f00000>; /* 111 MB */
88 };
89 partition@6f00000 {
90 label = "Primary kernel";
91 reg = <0x6f00000 0x1000000>; /* 16 MB */
92 };
93 partition@7f00000 {
94 label = "Primary DTB";
95 reg = <0x7f00000 0x40000>; /* 256 KB */
96 };
97 partition@7f40000 {
98 label = "Primary U-Boot environment";
99 reg = <0x7f40000 0x40000>; /* 256 KB */
100 };
101 partition@7f80000 {
102 label = "Primary U-Boot";
103 reg = <0x7f80000 0x80000>; /* 512 KB */
104 read-only;
105 };
106 };
107
108 nor-alternate@1,0 {
109 compatible = "amd,s29gl01gp", "cfi-flash";
110 bank-width = <2>;
111 //reg = <0xf0000000 0x08000000>; /* 128MB */
112 reg = <1 0 0x8000000>; /* 128MB */
113 #address-cells = <1>;
114 #size-cells = <1>;
115 partition@0 {
116 label = "Secondary user space";
117 reg = <0x00000000 0x6f00000>; /* 111 MB */
118 };
119 partition@6f00000 {
120 label = "Secondary kernel";
121 reg = <0x6f00000 0x1000000>; /* 16 MB */
122 };
123 partition@7f00000 {
124 label = "Secondary DTB";
125 reg = <0x7f00000 0x40000>; /* 256 KB */
126 };
127 partition@7f40000 {
128 label = "Secondary U-Boot environment";
129 reg = <0x7f40000 0x40000>; /* 256 KB */
130 };
131 partition@7f80000 {
132 label = "Secondary U-Boot";
133 reg = <0x7f80000 0x80000>; /* 512 KB */
134 read-only;
135 };
136 };
137
138 nand@2,0 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 /*
142 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
143 * Micron MT29F8G08DAA (2x 512 MB), or Micron
144 * MT29F16G08FAA (2x 1 GB), depending on the build
145 * configuration
146 */
147 compatible = "fsl,mpc8572-fcm-nand",
148 "fsl,elbc-fcm-nand";
149 reg = <2 0 0x40000>;
150 /* U-Boot should fix this up if chip size > 1 GB */
151 partition@0 {
152 label = "NAND Filesystem";
153 reg = <0 0x40000000>;
154 };
155 };
156
157 };
158
159 soc8572@ef000000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 device_type = "soc";
163 compatible = "fsl,mpc8572-immr", "simple-bus";
164 ranges = <0x0 0 0xef000000 0x100000>;
165 bus-frequency = <0>; // Filled out by uboot.
166
167 ecm-law@0 {
168 compatible = "fsl,ecm-law";
169 reg = <0x0 0x1000>;
170 fsl,num-laws = <12>;
171 };
172
173 ecm@1000 {
174 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
175 reg = <0x1000 0x1000>;
176 interrupts = <17 2>;
177 interrupt-parent = <&mpic>;
178 };
179
180 memory-controller@2000 {
181 compatible = "fsl,mpc8572-memory-controller";
182 reg = <0x2000 0x1000>;
183 interrupt-parent = <&mpic>;
184 interrupts = <18 2>;
185 };
186
187 memory-controller@6000 {
188 compatible = "fsl,mpc8572-memory-controller";
189 reg = <0x6000 0x1000>;
190 interrupt-parent = <&mpic>;
191 interrupts = <18 2>;
192 };
193
194 L2: l2-cache-controller@20000 {
195 compatible = "fsl,mpc8572-l2-cache-controller";
196 reg = <0x20000 0x1000>;
197 cache-line-size = <32>; // 32 bytes
198 cache-size = <0x100000>; // L2, 1M
199 interrupt-parent = <&mpic>;
200 interrupts = <16 2>;
201 };
202
203 i2c@3000 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 cell-index = <0>;
207 compatible = "fsl-i2c";
208 reg = <0x3000 0x100>;
209 interrupts = <43 2>;
210 interrupt-parent = <&mpic>;
211 dfsrr;
212
213 temp-sensor@48 {
214 compatible = "dallas,ds1631", "dallas,ds1621";
215 reg = <0x48>;
216 };
217
218 temp-sensor@4c {
219 compatible = "adi,adt7461";
220 reg = <0x4c>;
221 };
222
223 cpu-supervisor@51 {
224 compatible = "dallas,ds4510";
225 reg = <0x51>;
226 };
227
228 eeprom@54 {
229 compatible = "atmel,at24c128b";
230 reg = <0x54>;
231 };
232
233 rtc@68 {
234 compatible = "stm,m41t00",
235 "dallas,ds1338";
236 reg = <0x68>;
237 };
238
239 pcie-switch@70 {
240 compatible = "plx,pex8518";
241 reg = <0x70>;
242 };
243
244 gpio1: gpio@18 {
245 compatible = "nxp,pca9557";
246 reg = <0x18>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 polarity = <0x00>;
250 };
251
252 gpio2: gpio@1c {
253 compatible = "nxp,pca9557";
254 reg = <0x1c>;
255 #gpio-cells = <2>;
256 gpio-controller;
257 polarity = <0x00>;
258 };
259
260 gpio3: gpio@1e {
261 compatible = "nxp,pca9557";
262 reg = <0x1e>;
263 #gpio-cells = <2>;
264 gpio-controller;
265 polarity = <0x00>;
266 };
267
268 gpio4: gpio@1f {
269 compatible = "nxp,pca9557";
270 reg = <0x1f>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 polarity = <0x00>;
274 };
275 };
276
277 i2c@3100 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 cell-index = <1>;
281 compatible = "fsl-i2c";
282 reg = <0x3100 0x100>;
283 interrupts = <43 2>;
284 interrupt-parent = <&mpic>;
285 dfsrr;
286 };
287
288 dma@c300 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
292 reg = <0xc300 0x4>;
293 ranges = <0x0 0xc100 0x200>;
294 cell-index = <1>;
295 dma-channel@0 {
296 compatible = "fsl,mpc8572-dma-channel",
297 "fsl,eloplus-dma-channel";
298 reg = <0x0 0x80>;
299 cell-index = <0>;
300 interrupt-parent = <&mpic>;
301 interrupts = <76 2>;
302 };
303 dma-channel@80 {
304 compatible = "fsl,mpc8572-dma-channel",
305 "fsl,eloplus-dma-channel";
306 reg = <0x80 0x80>;
307 cell-index = <1>;
308 interrupt-parent = <&mpic>;
309 interrupts = <77 2>;
310 };
311 dma-channel@100 {
312 compatible = "fsl,mpc8572-dma-channel",
313 "fsl,eloplus-dma-channel";
314 reg = <0x100 0x80>;
315 cell-index = <2>;
316 interrupt-parent = <&mpic>;
317 interrupts = <78 2>;
318 };
319 dma-channel@180 {
320 compatible = "fsl,mpc8572-dma-channel",
321 "fsl,eloplus-dma-channel";
322 reg = <0x180 0x80>;
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
325 interrupts = <79 2>;
326 };
327 };
328
329 dma@21300 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
333 reg = <0x21300 0x4>;
334 ranges = <0x0 0x21100 0x200>;
335 cell-index = <0>;
336 dma-channel@0 {
337 compatible = "fsl,mpc8572-dma-channel",
338 "fsl,eloplus-dma-channel";
339 reg = <0x0 0x80>;
340 cell-index = <0>;
341 interrupt-parent = <&mpic>;
342 interrupts = <20 2>;
343 };
344 dma-channel@80 {
345 compatible = "fsl,mpc8572-dma-channel",
346 "fsl,eloplus-dma-channel";
347 reg = <0x80 0x80>;
348 cell-index = <1>;
349 interrupt-parent = <&mpic>;
350 interrupts = <21 2>;
351 };
352 dma-channel@100 {
353 compatible = "fsl,mpc8572-dma-channel",
354 "fsl,eloplus-dma-channel";
355 reg = <0x100 0x80>;
356 cell-index = <2>;
357 interrupt-parent = <&mpic>;
358 interrupts = <22 2>;
359 };
360 dma-channel@180 {
361 compatible = "fsl,mpc8572-dma-channel",
362 "fsl,eloplus-dma-channel";
363 reg = <0x180 0x80>;
364 cell-index = <3>;
365 interrupt-parent = <&mpic>;
366 interrupts = <23 2>;
367 };
368 };
369
370 /* eTSEC 1 */
371 enet0: ethernet@24000 {
372 #address-cells = <1>;
373 #size-cells = <1>;
374 cell-index = <0>;
375 device_type = "network";
376 model = "eTSEC";
377 compatible = "gianfar";
378 reg = <0x24000 0x1000>;
379 ranges = <0x0 0x24000 0x1000>;
380 local-mac-address = [ 00 00 00 00 00 00 ];
381 interrupts = <29 2 30 2 34 2>;
382 interrupt-parent = <&mpic>;
383 tbi-handle = <&tbi0>;
384 phy-handle = <&phy0>;
385 phy-connection-type = "sgmii";
386
387 mdio@520 {
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "fsl,gianfar-mdio";
391 reg = <0x520 0x20>;
392
393 phy0: ethernet-phy@1 {
394 interrupt-parent = <&mpic>;
395 interrupts = <8 1>;
396 reg = <0x1>;
397 };
398 phy1: ethernet-phy@2 {
399 interrupt-parent = <&mpic>;
400 interrupts = <8 1>;
401 reg = <0x2>;
402 };
403 tbi0: tbi-phy@11 {
404 reg = <0x11>;
405 device_type = "tbi-phy";
406 };
407 };
408 };
409
410 /* eTSEC 2 */
411 enet1: ethernet@25000 {
412 #address-cells = <1>;
413 #size-cells = <1>;
414 cell-index = <1>;
415 device_type = "network";
416 model = "eTSEC";
417 compatible = "gianfar";
418 reg = <0x25000 0x1000>;
419 ranges = <0x0 0x25000 0x1000>;
420 local-mac-address = [ 00 00 00 00 00 00 ];
421 interrupts = <35 2 36 2 40 2>;
422 interrupt-parent = <&mpic>;
423 tbi-handle = <&tbi1>;
424 phy-handle = <&phy1>;
425 phy-connection-type = "sgmii";
426
427 mdio@520 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "fsl,gianfar-tbi";
431 reg = <0x520 0x20>;
432
433 tbi1: tbi-phy@11 {
434 reg = <0x11>;
435 device_type = "tbi-phy";
436 };
437 };
438 };
439
440 /* UART0 */
441 serial0: serial@4500 {
442 cell-index = <0>;
443 device_type = "serial";
444 compatible = "ns16550";
445 reg = <0x4500 0x100>;
446 clock-frequency = <0>;
447 interrupts = <42 2>;
448 interrupt-parent = <&mpic>;
449 };
450
451 /* UART1 */
452 serial1: serial@4600 {
453 cell-index = <1>;
454 device_type = "serial";
455 compatible = "ns16550";
456 reg = <0x4600 0x100>;
457 clock-frequency = <0>;
458 interrupts = <42 2>;
459 interrupt-parent = <&mpic>;
460 };
461
462 global-utilities@e0000 { //global utilities block
463 compatible = "fsl,mpc8572-guts";
464 reg = <0xe0000 0x1000>;
465 fsl,has-rstcr;
466 };
467
468 msi@41600 {
469 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
470 reg = <0x41600 0x80>;
471 msi-available-ranges = <0 0x100>;
472 interrupts = <
473 0xe0 0
474 0xe1 0
475 0xe2 0
476 0xe3 0
477 0xe4 0
478 0xe5 0
479 0xe6 0
480 0xe7 0>;
481 interrupt-parent = <&mpic>;
482 };
483
484 crypto@30000 {
485 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
486 "fsl,sec2.1", "fsl,sec2.0";
487 reg = <0x30000 0x10000>;
488 interrupts = <45 2 58 2>;
489 interrupt-parent = <&mpic>;
490 fsl,num-channels = <4>;
491 fsl,channel-fifo-len = <24>;
492 fsl,exec-units-mask = <0x9fe>;
493 fsl,descriptor-types-mask = <0x3ab0ebf>;
494 };
495
496 mpic: pic@40000 {
497 interrupt-controller;
498 #address-cells = <0>;
499 #interrupt-cells = <2>;
500 reg = <0x40000 0x40000>;
501 compatible = "chrp,open-pic";
502 device_type = "open-pic";
503 };
504
505 gpio0: gpio@f000 {
506 compatible = "fsl,mpc8572-gpio";
507 reg = <0xf000 0x1000>;
508 interrupts = <47 2>;
509 interrupt-parent = <&mpic>;
510 #gpio-cells = <2>;
511 gpio-controller;
512 };
513
514 gpio-leds {
515 compatible = "gpio-leds";
516
517 heartbeat {
518 label = "Heartbeat";
519 gpios = <&gpio0 4 1>;
520 linux,default-trigger = "heartbeat";
521 };
522
523 yellow {
524 label = "Yellow";
525 gpios = <&gpio0 5 1>;
526 };
527
528 red {
529 label = "Red";
530 gpios = <&gpio0 6 1>;
531 };
532
533 green {
534 label = "Green";
535 gpios = <&gpio0 7 1>;
536 };
537 };
538
539 /* PME (pattern-matcher) */
540 pme@10000 {
541 compatible = "fsl,mpc8572-pme", "pme8572";
542 reg = <0x10000 0x5000>;
543 interrupts = <57 2 64 2 65 2 66 2 67 2>;
544 interrupt-parent = <&mpic>;
545 };
546
547 tlu@2f000 {
548 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
549 reg = <0x2f000 0x1000>;
550 interupts = <61 2 >;
551 interrupt-parent = <&mpic>;
552 };
553
554 tlu@15000 {
555 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
556 reg = <0x15000 0x1000>;
557 interupts = <75 2>;
558 interrupt-parent = <&mpic>;
559 };
560 };
561
562 /*
563 * PCI Express controller 3 @ ef008000 is not used.
564 * This would have been pci0 on other mpc85xx platforms.
565 */
566
567 /* PCI Express controller 2, wired to XMC P15 connector */
568 pci1: pcie@ef009000 {
569 compatible = "fsl,mpc8548-pcie";
570 device_type = "pci";
571 #interrupt-cells = <1>;
572 #size-cells = <2>;
573 #address-cells = <3>;
574 reg = <0 0xef009000 0 0x1000>;
575 bus-range = <0 255>;
576 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
577 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
578 clock-frequency = <33333333>;
579 interrupt-parent = <&mpic>;
580 interrupts = <25 2>;
581 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
582 interrupt-map = <
583 /* IDSEL 0x0 */
584 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
585 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
586 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
587 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
588 >;
589 pcie@0 {
590 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
591 #size-cells = <2>;
592 #address-cells = <3>;
593 device_type = "pci";
594 ranges = <0x2000000 0x0 0xc0000000
595 0x2000000 0x0 0xc0000000
596 0x0 0x10000000
597
598 0x1000000 0x0 0x0
599 0x1000000 0x0 0x0
600 0x0 0x100000>;
601 };
602 };
603
604 /* PCI Express controller 1, wired to PEX8112 for PMC interface */
605 pci2: pcie@ef00a000 {
606 compatible = "fsl,mpc8548-pcie";
607 device_type = "pci";
608 #interrupt-cells = <1>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 reg = <0 0xef00a000 0 0x1000>;
612 bus-range = <0 255>;
613 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
614 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
615 clock-frequency = <33333333>;
616 interrupt-parent = <&mpic>;
617 interrupts = <26 2>;
618 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
619 interrupt-map = <
620 /* IDSEL 0x0 */
621 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
622 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
623 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
624 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
625 >;
626 pcie@0 {
627 reg = <0x0 0x0 0x0 0x0 0x0>;
628 #size-cells = <2>;
629 #address-cells = <3>;
630 device_type = "pci";
631 ranges = <0x2000000 0x0 0x80000000
632 0x2000000 0x0 0x80000000
633 0x0 0x40000000
634
635 0x1000000 0x0 0x0
636 0x1000000 0x0 0x0
637 0x0 0x100000>;
638 };
639 };
640};
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
new file mode 100644
index 000000000000..c364ca6ff7d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -0,0 +1,707 @@
1/*
2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4 *
5 * XPedite5330 3U CompactPCI module based on MPC8572E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13/ {
14 model = "xes,xpedite5330";
15 compatible = "xes,xpedite5330", "xes,MPC8572";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "3U CompactPCI";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 pmcslots {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 pmcslot@0 {
36 cell-index = <0>;
37 /*
38 * boolean properties (true if defined):
39 * monarch;
40 * module-present;
41 */
42 };
43 };
44
45 xmcslots {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 xmcslot@0 {
50 cell-index = <0>;
51 /*
52 * boolean properties (true if defined):
53 * module-present;
54 */
55 };
56 };
57
58 cpci {
59 /*
60 * boolean properties (true if defined):
61 * system-controller;
62 */
63 system-controller;
64 };
65
66 cpus {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 PowerPC,8572@0 {
71 device_type = "cpu";
72 reg = <0x0>;
73 d-cache-line-size = <32>; // 32 bytes
74 i-cache-line-size = <32>; // 32 bytes
75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
77 timebase-frequency = <0>;
78 bus-frequency = <0>;
79 clock-frequency = <0>;
80 next-level-cache = <&L2>;
81 };
82
83 PowerPC,8572@1 {
84 device_type = "cpu";
85 reg = <0x1>;
86 d-cache-line-size = <32>; // 32 bytes
87 i-cache-line-size = <32>; // 32 bytes
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
90 timebase-frequency = <0>;
91 bus-frequency = <0>;
92 clock-frequency = <0>;
93 next-level-cache = <&L2>;
94 };
95 };
96
97 memory {
98 device_type = "memory";
99 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
100 };
101
102 localbus@ef005000 {
103 #address-cells = <2>;
104 #size-cells = <1>;
105 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
106 reg = <0 0xef005000 0 0x1000>;
107 interrupts = <19 2>;
108 interrupt-parent = <&mpic>;
109 /* Local bus region mappings */
110 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
111 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
112 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
113 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
114
115 nor-boot@0,0 {
116 compatible = "amd,s29gl01gp", "cfi-flash";
117 bank-width = <2>;
118 reg = <0 0 0x8000000>; /* 128MB */
119 #address-cells = <1>;
120 #size-cells = <1>;
121 partition@0 {
122 label = "Primary user space";
123 reg = <0x00000000 0x6f00000>; /* 111 MB */
124 };
125 partition@6f00000 {
126 label = "Primary kernel";
127 reg = <0x6f00000 0x1000000>; /* 16 MB */
128 };
129 partition@7f00000 {
130 label = "Primary DTB";
131 reg = <0x7f00000 0x40000>; /* 256 KB */
132 };
133 partition@7f40000 {
134 label = "Primary U-Boot environment";
135 reg = <0x7f40000 0x40000>; /* 256 KB */
136 };
137 partition@7f80000 {
138 label = "Primary U-Boot";
139 reg = <0x7f80000 0x80000>; /* 512 KB */
140 read-only;
141 };
142 };
143
144 nor-alternate@1,0 {
145 compatible = "amd,s29gl01gp", "cfi-flash";
146 bank-width = <2>;
147 //reg = <0xf0000000 0x08000000>; /* 128MB */
148 reg = <1 0 0x8000000>; /* 128MB */
149 #address-cells = <1>;
150 #size-cells = <1>;
151 partition@0 {
152 label = "Secondary user space";
153 reg = <0x00000000 0x6f00000>; /* 111 MB */
154 };
155 partition@6f00000 {
156 label = "Secondary kernel";
157 reg = <0x6f00000 0x1000000>; /* 16 MB */
158 };
159 partition@7f00000 {
160 label = "Secondary DTB";
161 reg = <0x7f00000 0x40000>; /* 256 KB */
162 };
163 partition@7f40000 {
164 label = "Secondary U-Boot environment";
165 reg = <0x7f40000 0x40000>; /* 256 KB */
166 };
167 partition@7f80000 {
168 label = "Secondary U-Boot";
169 reg = <0x7f80000 0x80000>; /* 512 KB */
170 read-only;
171 };
172 };
173
174 nand@2,0 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 /*
178 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
179 * Micron MT29F8G08DAA (2x 512 MB), or Micron
180 * MT29F16G08FAA (2x 1 GB), depending on the build
181 * configuration
182 */
183 compatible = "fsl,mpc8572-fcm-nand",
184 "fsl,elbc-fcm-nand";
185 reg = <2 0 0x40000>;
186 /* U-Boot should fix this up if chip size > 1 GB */
187 partition@0 {
188 label = "NAND Filesystem";
189 reg = <0 0x40000000>;
190 };
191 };
192
193 };
194
195 soc8572@ef000000 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 device_type = "soc";
199 compatible = "fsl,mpc8572-immr", "simple-bus";
200 ranges = <0x0 0 0xef000000 0x100000>;
201 bus-frequency = <0>; // Filled out by uboot.
202
203 ecm-law@0 {
204 compatible = "fsl,ecm-law";
205 reg = <0x0 0x1000>;
206 fsl,num-laws = <12>;
207 };
208
209 ecm@1000 {
210 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
211 reg = <0x1000 0x1000>;
212 interrupts = <17 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 memory-controller@2000 {
217 compatible = "fsl,mpc8572-memory-controller";
218 reg = <0x2000 0x1000>;
219 interrupt-parent = <&mpic>;
220 interrupts = <18 2>;
221 };
222
223 memory-controller@6000 {
224 compatible = "fsl,mpc8572-memory-controller";
225 reg = <0x6000 0x1000>;
226 interrupt-parent = <&mpic>;
227 interrupts = <18 2>;
228 };
229
230 L2: l2-cache-controller@20000 {
231 compatible = "fsl,mpc8572-l2-cache-controller";
232 reg = <0x20000 0x1000>;
233 cache-line-size = <32>; // 32 bytes
234 cache-size = <0x100000>; // L2, 1M
235 interrupt-parent = <&mpic>;
236 interrupts = <16 2>;
237 };
238
239 i2c@3000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 cell-index = <0>;
243 compatible = "fsl-i2c";
244 reg = <0x3000 0x100>;
245 interrupts = <43 2>;
246 interrupt-parent = <&mpic>;
247 dfsrr;
248
249 temp-sensor@48 {
250 compatible = "dallas,ds1631", "dallas,ds1621";
251 reg = <0x48>;
252 };
253
254 temp-sensor@4c {
255 compatible = "adi,adt7461";
256 reg = <0x4c>;
257 };
258
259 cpu-supervisor@51 {
260 compatible = "dallas,ds4510";
261 reg = <0x51>;
262 };
263
264 eeprom@54 {
265 compatible = "atmel,at24c128b";
266 reg = <0x54>;
267 };
268
269 rtc@68 {
270 compatible = "stm,m41t00",
271 "dallas,ds1338";
272 reg = <0x68>;
273 };
274
275 pcie-switch@70 {
276 compatible = "plx,pex8518";
277 reg = <0x70>;
278 };
279
280 gpio1: gpio@18 {
281 compatible = "nxp,pca9557";
282 reg = <0x18>;
283 #gpio-cells = <2>;
284 gpio-controller;
285 polarity = <0x00>;
286 };
287
288 gpio2: gpio@1c {
289 compatible = "nxp,pca9557";
290 reg = <0x1c>;
291 #gpio-cells = <2>;
292 gpio-controller;
293 polarity = <0x00>;
294 };
295
296 gpio3: gpio@1e {
297 compatible = "nxp,pca9557";
298 reg = <0x1e>;
299 #gpio-cells = <2>;
300 gpio-controller;
301 polarity = <0x00>;
302 };
303
304 gpio4: gpio@1f {
305 compatible = "nxp,pca9557";
306 reg = <0x1f>;
307 #gpio-cells = <2>;
308 gpio-controller;
309 polarity = <0x00>;
310 };
311 };
312
313 i2c@3100 {
314 #address-cells = <1>;
315 #size-cells = <0>;
316 cell-index = <1>;
317 compatible = "fsl-i2c";
318 reg = <0x3100 0x100>;
319 interrupts = <43 2>;
320 interrupt-parent = <&mpic>;
321 dfsrr;
322 };
323
324 dma@c300 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
328 reg = <0xc300 0x4>;
329 ranges = <0x0 0xc100 0x200>;
330 cell-index = <1>;
331 dma-channel@0 {
332 compatible = "fsl,mpc8572-dma-channel",
333 "fsl,eloplus-dma-channel";
334 reg = <0x0 0x80>;
335 cell-index = <0>;
336 interrupt-parent = <&mpic>;
337 interrupts = <76 2>;
338 };
339 dma-channel@80 {
340 compatible = "fsl,mpc8572-dma-channel",
341 "fsl,eloplus-dma-channel";
342 reg = <0x80 0x80>;
343 cell-index = <1>;
344 interrupt-parent = <&mpic>;
345 interrupts = <77 2>;
346 };
347 dma-channel@100 {
348 compatible = "fsl,mpc8572-dma-channel",
349 "fsl,eloplus-dma-channel";
350 reg = <0x100 0x80>;
351 cell-index = <2>;
352 interrupt-parent = <&mpic>;
353 interrupts = <78 2>;
354 };
355 dma-channel@180 {
356 compatible = "fsl,mpc8572-dma-channel",
357 "fsl,eloplus-dma-channel";
358 reg = <0x180 0x80>;
359 cell-index = <3>;
360 interrupt-parent = <&mpic>;
361 interrupts = <79 2>;
362 };
363 };
364
365 dma@21300 {
366 #address-cells = <1>;
367 #size-cells = <1>;
368 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
369 reg = <0x21300 0x4>;
370 ranges = <0x0 0x21100 0x200>;
371 cell-index = <0>;
372 dma-channel@0 {
373 compatible = "fsl,mpc8572-dma-channel",
374 "fsl,eloplus-dma-channel";
375 reg = <0x0 0x80>;
376 cell-index = <0>;
377 interrupt-parent = <&mpic>;
378 interrupts = <20 2>;
379 };
380 dma-channel@80 {
381 compatible = "fsl,mpc8572-dma-channel",
382 "fsl,eloplus-dma-channel";
383 reg = <0x80 0x80>;
384 cell-index = <1>;
385 interrupt-parent = <&mpic>;
386 interrupts = <21 2>;
387 };
388 dma-channel@100 {
389 compatible = "fsl,mpc8572-dma-channel",
390 "fsl,eloplus-dma-channel";
391 reg = <0x100 0x80>;
392 cell-index = <2>;
393 interrupt-parent = <&mpic>;
394 interrupts = <22 2>;
395 };
396 dma-channel@180 {
397 compatible = "fsl,mpc8572-dma-channel",
398 "fsl,eloplus-dma-channel";
399 reg = <0x180 0x80>;
400 cell-index = <3>;
401 interrupt-parent = <&mpic>;
402 interrupts = <23 2>;
403 };
404 };
405
406 /* eTSEC 1 */
407 enet0: ethernet@24000 {
408 #address-cells = <1>;
409 #size-cells = <1>;
410 cell-index = <0>;
411 device_type = "network";
412 model = "eTSEC";
413 compatible = "gianfar";
414 reg = <0x24000 0x1000>;
415 ranges = <0x0 0x24000 0x1000>;
416 local-mac-address = [ 00 00 00 00 00 00 ];
417 interrupts = <29 2 30 2 34 2>;
418 interrupt-parent = <&mpic>;
419 tbi-handle = <&tbi0>;
420 phy-handle = <&phy0>;
421 phy-connection-type = "sgmii";
422
423 mdio@520 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "fsl,gianfar-mdio";
427 reg = <0x520 0x20>;
428
429 phy0: ethernet-phy@1 {
430 interrupt-parent = <&mpic>;
431 interrupts = <8 1>;
432 reg = <0x1>;
433 };
434 phy1: ethernet-phy@2 {
435 interrupt-parent = <&mpic>;
436 interrupts = <8 1>;
437 reg = <0x2>;
438 };
439 tbi0: tbi-phy@11 {
440 reg = <0x11>;
441 device_type = "tbi-phy";
442 };
443 };
444 };
445
446 /* eTSEC 2 */
447 enet1: ethernet@25000 {
448 #address-cells = <1>;
449 #size-cells = <1>;
450 cell-index = <1>;
451 device_type = "network";
452 model = "eTSEC";
453 compatible = "gianfar";
454 reg = <0x25000 0x1000>;
455 ranges = <0x0 0x25000 0x1000>;
456 local-mac-address = [ 00 00 00 00 00 00 ];
457 interrupts = <35 2 36 2 40 2>;
458 interrupt-parent = <&mpic>;
459 tbi-handle = <&tbi1>;
460 phy-handle = <&phy1>;
461 phy-connection-type = "sgmii";
462
463 mdio@520 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "fsl,gianfar-tbi";
467 reg = <0x520 0x20>;
468
469 tbi1: tbi-phy@11 {
470 reg = <0x11>;
471 device_type = "tbi-phy";
472 };
473 };
474 };
475
476 /* UART0 */
477 serial0: serial@4500 {
478 cell-index = <0>;
479 device_type = "serial";
480 compatible = "ns16550";
481 reg = <0x4500 0x100>;
482 clock-frequency = <0>;
483 interrupts = <42 2>;
484 interrupt-parent = <&mpic>;
485 };
486
487 /* UART1 */
488 serial1: serial@4600 {
489 cell-index = <1>;
490 device_type = "serial";
491 compatible = "ns16550";
492 reg = <0x4600 0x100>;
493 clock-frequency = <0>;
494 interrupts = <42 2>;
495 interrupt-parent = <&mpic>;
496 };
497
498 global-utilities@e0000 { //global utilities block
499 compatible = "fsl,mpc8572-guts";
500 reg = <0xe0000 0x1000>;
501 fsl,has-rstcr;
502 };
503
504 msi@41600 {
505 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
506 reg = <0x41600 0x80>;
507 msi-available-ranges = <0 0x100>;
508 interrupts = <
509 0xe0 0
510 0xe1 0
511 0xe2 0
512 0xe3 0
513 0xe4 0
514 0xe5 0
515 0xe6 0
516 0xe7 0>;
517 interrupt-parent = <&mpic>;
518 };
519
520 crypto@30000 {
521 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
522 "fsl,sec2.1", "fsl,sec2.0";
523 reg = <0x30000 0x10000>;
524 interrupts = <45 2 58 2>;
525 interrupt-parent = <&mpic>;
526 fsl,num-channels = <4>;
527 fsl,channel-fifo-len = <24>;
528 fsl,exec-units-mask = <0x9fe>;
529 fsl,descriptor-types-mask = <0x3ab0ebf>;
530 };
531
532 mpic: pic@40000 {
533 interrupt-controller;
534 #address-cells = <0>;
535 #interrupt-cells = <2>;
536 reg = <0x40000 0x40000>;
537 compatible = "chrp,open-pic";
538 device_type = "open-pic";
539 };
540
541 gpio0: gpio@f000 {
542 compatible = "fsl,mpc8572-gpio";
543 reg = <0xf000 0x1000>;
544 interrupts = <47 2>;
545 interrupt-parent = <&mpic>;
546 #gpio-cells = <2>;
547 gpio-controller;
548 };
549
550 gpio-leds {
551 compatible = "gpio-leds";
552
553 heartbeat {
554 label = "Heartbeat";
555 gpios = <&gpio0 4 1>;
556 linux,default-trigger = "heartbeat";
557 };
558
559 yellow {
560 label = "Yellow";
561 gpios = <&gpio0 5 1>;
562 };
563
564 red {
565 label = "Red";
566 gpios = <&gpio0 6 1>;
567 };
568
569 green {
570 label = "Green";
571 gpios = <&gpio0 7 1>;
572 };
573 };
574
575 /* PME (pattern-matcher) */
576 pme@10000 {
577 compatible = "fsl,mpc8572-pme", "pme8572";
578 reg = <0x10000 0x5000>;
579 interrupts = <57 2 64 2 65 2 66 2 67 2>;
580 interrupt-parent = <&mpic>;
581 };
582
583 tlu@2f000 {
584 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
585 reg = <0x2f000 0x1000>;
586 interupts = <61 2 >;
587 interrupt-parent = <&mpic>;
588 };
589
590 tlu@15000 {
591 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
592 reg = <0x15000 0x1000>;
593 interupts = <75 2>;
594 interrupt-parent = <&mpic>;
595 };
596 };
597
598 /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
599 pci0: pcie@ef008000 {
600 compatible = "fsl,mpc8548-pcie";
601 device_type = "pci";
602 #interrupt-cells = <1>;
603 #size-cells = <2>;
604 #address-cells = <3>;
605 reg = <0 0xef008000 0 0x1000>;
606 bus-range = <0 255>;
607 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
608 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
609 clock-frequency = <33333333>;
610 interrupt-parent = <&mpic>;
611 interrupts = <24 2>;
612 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
613 interrupt-map = <
614 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
615 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
616 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
617 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
618 >;
619 pcie@0 {
620 reg = <0x0 0x0 0x0 0x0 0x0>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 device_type = "pci";
624 ranges = <0x02000000 0x0 0xe0000000
625 0x02000000 0x0 0xe0000000
626 0x0 0x10000000
627
628 0x01000000 0x0 0x0
629 0x01000000 0x0 0x0
630 0x0 0x100000>;
631 };
632 };
633
634 /* PCI Express controller 2, PMC module via PEX8112 bridge */
635 pci1: pcie@ef009000 {
636 compatible = "fsl,mpc8548-pcie";
637 device_type = "pci";
638 #interrupt-cells = <1>;
639 #size-cells = <2>;
640 #address-cells = <3>;
641 reg = <0 0xef009000 0 0x1000>;
642 bus-range = <0 255>;
643 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
644 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
645 clock-frequency = <33333333>;
646 interrupt-parent = <&mpic>;
647 interrupts = <25 2>;
648 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
649 interrupt-map = <
650 /* IDSEL 0x0 */
651 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
652 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
653 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
654 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
655 >;
656 pcie@0 {
657 reg = <0x0 0x0 0x0 0x0 0x0>;
658 #size-cells = <2>;
659 #address-cells = <3>;
660 device_type = "pci";
661 ranges = <0x2000000 0x0 0xc0000000
662 0x2000000 0x0 0xc0000000
663 0x0 0x10000000
664
665 0x1000000 0x0 0x0
666 0x1000000 0x0 0x0
667 0x0 0x100000>;
668 };
669 };
670
671 /* PCI Express controller 1, XMC P15 */
672 pci2: pcie@ef00a000 {
673 compatible = "fsl,mpc8548-pcie";
674 device_type = "pci";
675 #interrupt-cells = <1>;
676 #size-cells = <2>;
677 #address-cells = <3>;
678 reg = <0 0xef00a000 0 0x1000>;
679 bus-range = <0 255>;
680 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
681 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
682 clock-frequency = <33333333>;
683 interrupt-parent = <&mpic>;
684 interrupts = <26 2>;
685 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
686 interrupt-map = <
687 /* IDSEL 0x0 */
688 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
689 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
690 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
691 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
692 >;
693 pcie@0 {
694 reg = <0x0 0x0 0x0 0x0 0x0>;
695 #size-cells = <2>;
696 #address-cells = <3>;
697 device_type = "pci";
698 ranges = <0x2000000 0x0 0x80000000
699 0x2000000 0x0 0x80000000
700 0x0 0x40000000
701
702 0x1000000 0x0 0x0
703 0x1000000 0x0 0x0
704 0x0 0x100000>;
705 };
706 };
707};
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
new file mode 100644
index 000000000000..7a8a4afd56cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -0,0 +1,638 @@
1/*
2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4 *
5 * XPedite5370 3U VPX single-board computer based on MPC8572E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13/ {
14 model = "xes,xpedite5370";
15 compatible = "xes,xpedite5370", "xes,MPC8572";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci1 = &pci1;
25 pci2 = &pci2;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8572@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
43 };
44
45 PowerPC,8572@1 {
46 device_type = "cpu";
47 reg = <0x1>;
48 d-cache-line-size = <32>; // 32 bytes
49 i-cache-line-size = <32>; // 32 bytes
50 d-cache-size = <0x8000>; // L1, 32K
51 i-cache-size = <0x8000>; // L1, 32K
52 timebase-frequency = <0>;
53 bus-frequency = <0>;
54 clock-frequency = <0>;
55 next-level-cache = <&L2>;
56 };
57 };
58
59 memory {
60 device_type = "memory";
61 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
62 };
63
64 localbus@ef005000 {
65 #address-cells = <2>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
68 reg = <0 0xef005000 0 0x1000>;
69 interrupts = <19 2>;
70 interrupt-parent = <&mpic>;
71 /* Local bus region mappings */
72 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
73 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
74 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
75 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
76
77 nor-boot@0,0 {
78 compatible = "amd,s29gl01gp", "cfi-flash";
79 bank-width = <2>;
80 reg = <0 0 0x8000000>; /* 128MB */
81 #address-cells = <1>;
82 #size-cells = <1>;
83 partition@0 {
84 label = "Primary user space";
85 reg = <0x00000000 0x6f00000>; /* 111 MB */
86 };
87 partition@6f00000 {
88 label = "Primary kernel";
89 reg = <0x6f00000 0x1000000>; /* 16 MB */
90 };
91 partition@7f00000 {
92 label = "Primary DTB";
93 reg = <0x7f00000 0x40000>; /* 256 KB */
94 };
95 partition@7f40000 {
96 label = "Primary U-Boot environment";
97 reg = <0x7f40000 0x40000>; /* 256 KB */
98 };
99 partition@7f80000 {
100 label = "Primary U-Boot";
101 reg = <0x7f80000 0x80000>; /* 512 KB */
102 read-only;
103 };
104 };
105
106 nor-alternate@1,0 {
107 compatible = "amd,s29gl01gp", "cfi-flash";
108 bank-width = <2>;
109 //reg = <0xf0000000 0x08000000>; /* 128MB */
110 reg = <1 0 0x8000000>; /* 128MB */
111 #address-cells = <1>;
112 #size-cells = <1>;
113 partition@0 {
114 label = "Secondary user space";
115 reg = <0x00000000 0x6f00000>; /* 111 MB */
116 };
117 partition@6f00000 {
118 label = "Secondary kernel";
119 reg = <0x6f00000 0x1000000>; /* 16 MB */
120 };
121 partition@7f00000 {
122 label = "Secondary DTB";
123 reg = <0x7f00000 0x40000>; /* 256 KB */
124 };
125 partition@7f40000 {
126 label = "Secondary U-Boot environment";
127 reg = <0x7f40000 0x40000>; /* 256 KB */
128 };
129 partition@7f80000 {
130 label = "Secondary U-Boot";
131 reg = <0x7f80000 0x80000>; /* 512 KB */
132 read-only;
133 };
134 };
135
136 nand@2,0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 /*
140 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
141 * Micron MT29F8G08DAA (2x 512 MB), or Micron
142 * MT29F16G08FAA (2x 1 GB), depending on the build
143 * configuration
144 */
145 compatible = "fsl,mpc8572-fcm-nand",
146 "fsl,elbc-fcm-nand";
147 reg = <2 0 0x40000>;
148 /* U-Boot should fix this up if chip size > 1 GB */
149 partition@0 {
150 label = "NAND Filesystem";
151 reg = <0 0x40000000>;
152 };
153 };
154
155 };
156
157 soc8572@ef000000 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 device_type = "soc";
161 compatible = "fsl,mpc8572-immr", "simple-bus";
162 ranges = <0x0 0 0xef000000 0x100000>;
163 bus-frequency = <0>; // Filled out by uboot.
164
165 ecm-law@0 {
166 compatible = "fsl,ecm-law";
167 reg = <0x0 0x1000>;
168 fsl,num-laws = <12>;
169 };
170
171 ecm@1000 {
172 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
173 reg = <0x1000 0x1000>;
174 interrupts = <17 2>;
175 interrupt-parent = <&mpic>;
176 };
177
178 memory-controller@2000 {
179 compatible = "fsl,mpc8572-memory-controller";
180 reg = <0x2000 0x1000>;
181 interrupt-parent = <&mpic>;
182 interrupts = <18 2>;
183 };
184
185 memory-controller@6000 {
186 compatible = "fsl,mpc8572-memory-controller";
187 reg = <0x6000 0x1000>;
188 interrupt-parent = <&mpic>;
189 interrupts = <18 2>;
190 };
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8572-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x100000>; // L2, 1M
197 interrupt-parent = <&mpic>;
198 interrupts = <16 2>;
199 };
200
201 i2c@3000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 cell-index = <0>;
205 compatible = "fsl-i2c";
206 reg = <0x3000 0x100>;
207 interrupts = <43 2>;
208 interrupt-parent = <&mpic>;
209 dfsrr;
210
211 temp-sensor@48 {
212 compatible = "dallas,ds1631", "dallas,ds1621";
213 reg = <0x48>;
214 };
215
216 temp-sensor@4c {
217 compatible = "adi,adt7461";
218 reg = <0x4c>;
219 };
220
221 cpu-supervisor@51 {
222 compatible = "dallas,ds4510";
223 reg = <0x51>;
224 };
225
226 eeprom@54 {
227 compatible = "atmel,at24c128b";
228 reg = <0x54>;
229 };
230
231 rtc@68 {
232 compatible = "stm,m41t00",
233 "dallas,ds1338";
234 reg = <0x68>;
235 };
236
237 pcie-switch@70 {
238 compatible = "plx,pex8518";
239 reg = <0x70>;
240 };
241
242 gpio1: gpio@18 {
243 compatible = "nxp,pca9557";
244 reg = <0x18>;
245 #gpio-cells = <2>;
246 gpio-controller;
247 polarity = <0x00>;
248 };
249
250 gpio2: gpio@1c {
251 compatible = "nxp,pca9557";
252 reg = <0x1c>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 polarity = <0x00>;
256 };
257
258 gpio3: gpio@1e {
259 compatible = "nxp,pca9557";
260 reg = <0x1e>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 polarity = <0x00>;
264 };
265
266 gpio4: gpio@1f {
267 compatible = "nxp,pca9557";
268 reg = <0x1f>;
269 #gpio-cells = <2>;
270 gpio-controller;
271 polarity = <0x00>;
272 };
273 };
274
275 i2c@3100 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 cell-index = <1>;
279 compatible = "fsl-i2c";
280 reg = <0x3100 0x100>;
281 interrupts = <43 2>;
282 interrupt-parent = <&mpic>;
283 dfsrr;
284 };
285
286 dma@c300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0xc300 0x4>;
291 ranges = <0x0 0xc100 0x200>;
292 cell-index = <1>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <76 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <77 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <78 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <79 2>;
324 };
325 };
326
327 dma@21300 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
331 reg = <0x21300 0x4>;
332 ranges = <0x0 0x21100 0x200>;
333 cell-index = <0>;
334 dma-channel@0 {
335 compatible = "fsl,mpc8572-dma-channel",
336 "fsl,eloplus-dma-channel";
337 reg = <0x0 0x80>;
338 cell-index = <0>;
339 interrupt-parent = <&mpic>;
340 interrupts = <20 2>;
341 };
342 dma-channel@80 {
343 compatible = "fsl,mpc8572-dma-channel",
344 "fsl,eloplus-dma-channel";
345 reg = <0x80 0x80>;
346 cell-index = <1>;
347 interrupt-parent = <&mpic>;
348 interrupts = <21 2>;
349 };
350 dma-channel@100 {
351 compatible = "fsl,mpc8572-dma-channel",
352 "fsl,eloplus-dma-channel";
353 reg = <0x100 0x80>;
354 cell-index = <2>;
355 interrupt-parent = <&mpic>;
356 interrupts = <22 2>;
357 };
358 dma-channel@180 {
359 compatible = "fsl,mpc8572-dma-channel",
360 "fsl,eloplus-dma-channel";
361 reg = <0x180 0x80>;
362 cell-index = <3>;
363 interrupt-parent = <&mpic>;
364 interrupts = <23 2>;
365 };
366 };
367
368 /* eTSEC 1 */
369 enet0: ethernet@24000 {
370 #address-cells = <1>;
371 #size-cells = <1>;
372 cell-index = <0>;
373 device_type = "network";
374 model = "eTSEC";
375 compatible = "gianfar";
376 reg = <0x24000 0x1000>;
377 ranges = <0x0 0x24000 0x1000>;
378 local-mac-address = [ 00 00 00 00 00 00 ];
379 interrupts = <29 2 30 2 34 2>;
380 interrupt-parent = <&mpic>;
381 tbi-handle = <&tbi0>;
382 phy-handle = <&phy0>;
383 phy-connection-type = "sgmii";
384
385 mdio@520 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "fsl,gianfar-mdio";
389 reg = <0x520 0x20>;
390
391 phy0: ethernet-phy@1 {
392 interrupt-parent = <&mpic>;
393 interrupts = <8 1>;
394 reg = <0x1>;
395 };
396 phy1: ethernet-phy@2 {
397 interrupt-parent = <&mpic>;
398 interrupts = <8 1>;
399 reg = <0x2>;
400 };
401 tbi0: tbi-phy@11 {
402 reg = <0x11>;
403 device_type = "tbi-phy";
404 };
405 };
406 };
407
408 /* eTSEC 2 */
409 enet1: ethernet@25000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <1>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "gianfar";
416 reg = <0x25000 0x1000>;
417 ranges = <0x0 0x25000 0x1000>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupts = <35 2 36 2 40 2>;
420 interrupt-parent = <&mpic>;
421 tbi-handle = <&tbi1>;
422 phy-handle = <&phy1>;
423 phy-connection-type = "sgmii";
424
425 mdio@520 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "fsl,gianfar-tbi";
429 reg = <0x520 0x20>;
430
431 tbi1: tbi-phy@11 {
432 reg = <0x11>;
433 device_type = "tbi-phy";
434 };
435 };
436 };
437
438 /* UART0 */
439 serial0: serial@4500 {
440 cell-index = <0>;
441 device_type = "serial";
442 compatible = "ns16550";
443 reg = <0x4500 0x100>;
444 clock-frequency = <0>;
445 interrupts = <42 2>;
446 interrupt-parent = <&mpic>;
447 };
448
449 /* UART1 */
450 serial1: serial@4600 {
451 cell-index = <1>;
452 device_type = "serial";
453 compatible = "ns16550";
454 reg = <0x4600 0x100>;
455 clock-frequency = <0>;
456 interrupts = <42 2>;
457 interrupt-parent = <&mpic>;
458 };
459
460 global-utilities@e0000 { //global utilities block
461 compatible = "fsl,mpc8572-guts";
462 reg = <0xe0000 0x1000>;
463 fsl,has-rstcr;
464 };
465
466 msi@41600 {
467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
468 reg = <0x41600 0x80>;
469 msi-available-ranges = <0 0x100>;
470 interrupts = <
471 0xe0 0
472 0xe1 0
473 0xe2 0
474 0xe3 0
475 0xe4 0
476 0xe5 0
477 0xe6 0
478 0xe7 0>;
479 interrupt-parent = <&mpic>;
480 };
481
482 crypto@30000 {
483 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
484 "fsl,sec2.1", "fsl,sec2.0";
485 reg = <0x30000 0x10000>;
486 interrupts = <45 2 58 2>;
487 interrupt-parent = <&mpic>;
488 fsl,num-channels = <4>;
489 fsl,channel-fifo-len = <24>;
490 fsl,exec-units-mask = <0x9fe>;
491 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 };
493
494 mpic: pic@40000 {
495 interrupt-controller;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
498 reg = <0x40000 0x40000>;
499 compatible = "chrp,open-pic";
500 device_type = "open-pic";
501 };
502
503 gpio0: gpio@f000 {
504 compatible = "fsl,mpc8572-gpio";
505 reg = <0xf000 0x1000>;
506 interrupts = <47 2>;
507 interrupt-parent = <&mpic>;
508 #gpio-cells = <2>;
509 gpio-controller;
510 };
511
512 gpio-leds {
513 compatible = "gpio-leds";
514
515 heartbeat {
516 label = "Heartbeat";
517 gpios = <&gpio0 4 1>;
518 linux,default-trigger = "heartbeat";
519 };
520
521 yellow {
522 label = "Yellow";
523 gpios = <&gpio0 5 1>;
524 };
525
526 red {
527 label = "Red";
528 gpios = <&gpio0 6 1>;
529 };
530
531 green {
532 label = "Green";
533 gpios = <&gpio0 7 1>;
534 };
535 };
536
537 /* PME (pattern-matcher) */
538 pme@10000 {
539 compatible = "fsl,mpc8572-pme", "pme8572";
540 reg = <0x10000 0x5000>;
541 interrupts = <57 2 64 2 65 2 66 2 67 2>;
542 interrupt-parent = <&mpic>;
543 };
544
545 tlu@2f000 {
546 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
547 reg = <0x2f000 0x1000>;
548 interupts = <61 2 >;
549 interrupt-parent = <&mpic>;
550 };
551
552 tlu@15000 {
553 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
554 reg = <0x15000 0x1000>;
555 interupts = <75 2>;
556 interrupt-parent = <&mpic>;
557 };
558 };
559
560 /*
561 * PCI Express controller 3 @ ef008000 is not used.
562 * This would have been pci0 on other mpc85xx platforms.
563 */
564
565 /* PCI Express controller 2, wired to VPX P1,P2 backplane */
566 pci1: pcie@ef009000 {
567 compatible = "fsl,mpc8548-pcie";
568 device_type = "pci";
569 #interrupt-cells = <1>;
570 #size-cells = <2>;
571 #address-cells = <3>;
572 reg = <0 0xef009000 0 0x1000>;
573 bus-range = <0 255>;
574 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
575 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
576 clock-frequency = <33333333>;
577 interrupt-parent = <&mpic>;
578 interrupts = <25 2>;
579 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
580 interrupt-map = <
581 /* IDSEL 0x0 */
582 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
583 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
584 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
585 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
586 >;
587 pcie@0 {
588 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
589 #size-cells = <2>;
590 #address-cells = <3>;
591 device_type = "pci";
592 ranges = <0x2000000 0x0 0xc0000000
593 0x2000000 0x0 0xc0000000
594 0x0 0x10000000
595
596 0x1000000 0x0 0x0
597 0x1000000 0x0 0x0
598 0x0 0x100000>;
599 };
600 };
601
602 /* PCI Express controller 1, wired to PEX8518 PCIe switch */
603 pci2: pcie@ef00a000 {
604 compatible = "fsl,mpc8548-pcie";
605 device_type = "pci";
606 #interrupt-cells = <1>;
607 #size-cells = <2>;
608 #address-cells = <3>;
609 reg = <0 0xef00a000 0 0x1000>;
610 bus-range = <0 255>;
611 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
612 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
613 clock-frequency = <33333333>;
614 interrupt-parent = <&mpic>;
615 interrupts = <26 2>;
616 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
617 interrupt-map = <
618 /* IDSEL 0x0 */
619 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
620 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
621 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
622 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
623 >;
624 pcie@0 {
625 reg = <0x0 0x0 0x0 0x0 0x0>;
626 #size-cells = <2>;
627 #address-cells = <3>;
628 device_type = "pci";
629 ranges = <0x2000000 0x0 0x80000000
630 0x2000000 0x0 0x80000000
631 0x0 0x40000000
632
633 0x1000000 0x0 0x0
634 0x1000000 0x0 0x0
635 0x0 0x100000>;
636 };
637 };
638};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 07:46:13 -0400