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authorKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
commit32f960e9439bbe72c45f8cd854049254122fc198 (patch)
tree7773600dbe67df8bd07b35e865a7a7c1b7a863fd /arch/powerpc/boot/dts/mpc8568mds.dts
parenta5dc66e2ab2e2cf641346b056a69a67cfcf9458c (diff)
[POWERPC] 85xx: Convert dts to v1 syntax
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8568mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts283
1 files changed, 142 insertions, 141 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index df4b5e89d7e4..3e6739fc0aa2 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8568E MDS Device Tree Source 2 * MPC8568E MDS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/* 14/*
14/memreserve/ 00000000 1000000; 15/memreserve/ 00000000 1000000;
@@ -37,11 +38,11 @@
37 38
38 PowerPC,8568@0 { 39 PowerPC,8568@0 {
39 device_type = "cpu"; 40 device_type = "cpu";
40 reg = <0>; 41 reg = <0x0>;
41 d-cache-line-size = <20>; // 32 bytes 42 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes 43 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K 44 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K 45 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; 46 timebase-frequency = <0>;
46 bus-frequency = <0>; 47 bus-frequency = <0>;
47 clock-frequency = <0>; 48 clock-frequency = <0>;
@@ -50,36 +51,36 @@
50 51
51 memory { 52 memory {
52 device_type = "memory"; 53 device_type = "memory";
53 reg = <00000000 10000000>; 54 reg = <0x0 0x10000000>;
54 }; 55 };
55 56
56 bcsr@f8000000 { 57 bcsr@f8000000 {
57 device_type = "board-control"; 58 device_type = "board-control";
58 reg = <f8000000 8000>; 59 reg = <0xf8000000 0x8000>;
59 }; 60 };
60 61
61 soc8568@e0000000 { 62 soc8568@e0000000 {
62 #address-cells = <1>; 63 #address-cells = <1>;
63 #size-cells = <1>; 64 #size-cells = <1>;
64 device_type = "soc"; 65 device_type = "soc";
65 ranges = <0 e0000000 00100000>; 66 ranges = <0x0 0xe0000000 0x100000>;
66 reg = <e0000000 00001000>; 67 reg = <0xe0000000 0x1000>;
67 bus-frequency = <0>; 68 bus-frequency = <0>;
68 69
69 memory-controller@2000 { 70 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller"; 71 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>; 72 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>;
73 interrupts = <12 2>; 74 interrupts = <18 2>;
74 }; 75 };
75 76
76 l2-cache-controller@20000 { 77 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller"; 78 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>; 79 reg = <0x20000 0x1000>;
79 cache-line-size = <20>; // 32 bytes 80 cache-line-size = <32>; // 32 bytes
80 cache-size = <80000>; // L2, 512K 81 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 interrupts = <10 2>; 83 interrupts = <16 2>;
83 }; 84 };
84 85
85 i2c@3000 { 86 i2c@3000 {
@@ -87,14 +88,14 @@
87 #size-cells = <0>; 88 #size-cells = <0>;
88 cell-index = <0>; 89 cell-index = <0>;
89 compatible = "fsl-i2c"; 90 compatible = "fsl-i2c";
90 reg = <3000 100>; 91 reg = <0x3000 0x100>;
91 interrupts = <2b 2>; 92 interrupts = <43 2>;
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 dfsrr; 94 dfsrr;
94 95
95 rtc@68 { 96 rtc@68 {
96 compatible = "dallas,ds1374"; 97 compatible = "dallas,ds1374";
97 reg = <68>; 98 reg = <0x68>;
98 }; 99 };
99 }; 100 };
100 101
@@ -103,8 +104,8 @@
103 #size-cells = <0>; 104 #size-cells = <0>;
104 cell-index = <1>; 105 cell-index = <1>;
105 compatible = "fsl-i2c"; 106 compatible = "fsl-i2c";
106 reg = <3100 100>; 107 reg = <0x3100 0x100>;
107 interrupts = <2b 2>; 108 interrupts = <43 2>;
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 dfsrr; 110 dfsrr;
110 }; 111 };
@@ -113,30 +114,30 @@
113 #address-cells = <1>; 114 #address-cells = <1>;
114 #size-cells = <0>; 115 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio"; 116 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>; 117 reg = <0x24520 0x20>;
117 118
118 phy0: ethernet-phy@7 { 119 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 interrupts = <1 1>; 121 interrupts = <1 1>;
121 reg = <7>; 122 reg = <0x7>;
122 device_type = "ethernet-phy"; 123 device_type = "ethernet-phy";
123 }; 124 };
124 phy1: ethernet-phy@1 { 125 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 interrupts = <2 1>; 127 interrupts = <2 1>;
127 reg = <1>; 128 reg = <0x1>;
128 device_type = "ethernet-phy"; 129 device_type = "ethernet-phy";
129 }; 130 };
130 phy2: ethernet-phy@2 { 131 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 interrupts = <1 1>; 133 interrupts = <1 1>;
133 reg = <2>; 134 reg = <0x2>;
134 device_type = "ethernet-phy"; 135 device_type = "ethernet-phy";
135 }; 136 };
136 phy3: ethernet-phy@3 { 137 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
138 interrupts = <2 1>; 139 interrupts = <2 1>;
139 reg = <3>; 140 reg = <0x3>;
140 device_type = "ethernet-phy"; 141 device_type = "ethernet-phy";
141 }; 142 };
142 }; 143 };
@@ -146,9 +147,9 @@
146 device_type = "network"; 147 device_type = "network";
147 model = "eTSEC"; 148 model = "eTSEC";
148 compatible = "gianfar"; 149 compatible = "gianfar";
149 reg = <24000 1000>; 150 reg = <0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ]; 151 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>; 152 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>; 153 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>; 154 phy-handle = <&phy2>;
154 }; 155 };
@@ -158,9 +159,9 @@
158 device_type = "network"; 159 device_type = "network";
159 model = "eTSEC"; 160 model = "eTSEC";
160 compatible = "gianfar"; 161 compatible = "gianfar";
161 reg = <25000 1000>; 162 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 163 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>; 164 interrupts = <35 2 36 2 40 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>; 166 phy-handle = <&phy3>;
166 }; 167 };
@@ -169,15 +170,15 @@
169 cell-index = <0>; 170 cell-index = <0>;
170 device_type = "serial"; 171 device_type = "serial";
171 compatible = "ns16550"; 172 compatible = "ns16550";
172 reg = <4500 100>; 173 reg = <0x4500 0x100>;
173 clock-frequency = <0>; 174 clock-frequency = <0>;
174 interrupts = <2a 2>; 175 interrupts = <42 2>;
175 interrupt-parent = <&mpic>; 176 interrupt-parent = <&mpic>;
176 }; 177 };
177 178
178 global-utilities@e0000 { //global utilities block 179 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts"; 180 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>; 181 reg = <0xe0000 0x1000>;
181 fsl,has-rstcr; 182 fsl,has-rstcr;
182 }; 183 };
183 184
@@ -185,9 +186,9 @@
185 cell-index = <1>; 186 cell-index = <1>;
186 device_type = "serial"; 187 device_type = "serial";
187 compatible = "ns16550"; 188 compatible = "ns16550";
188 reg = <4600 100>; 189 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 190 clock-frequency = <0>;
190 interrupts = <2a 2>; 191 interrupts = <42 2>;
191 interrupt-parent = <&mpic>; 192 interrupt-parent = <&mpic>;
192 }; 193 };
193 194
@@ -195,13 +196,13 @@
195 device_type = "crypto"; 196 device_type = "crypto";
196 model = "SEC2"; 197 model = "SEC2";
197 compatible = "talitos"; 198 compatible = "talitos";
198 reg = <30000 f000>; 199 reg = <0x30000 0xf000>;
199 interrupts = <2d 2>; 200 interrupts = <45 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 num-channels = <4>; 202 num-channels = <4>;
202 channel-fifo-len = <18>; 203 channel-fifo-len = <24>;
203 exec-units-mask = <000000fe>; 204 exec-units-mask = <0xfe>;
204 descriptor-types-mask = <012b0ebf>; 205 descriptor-types-mask = <0x12b0ebf>;
205 }; 206 };
206 207
207 mpic: pic@40000 { 208 mpic: pic@40000 {
@@ -209,73 +210,73 @@
209 interrupt-controller; 210 interrupt-controller;
210 #address-cells = <0>; 211 #address-cells = <0>;
211 #interrupt-cells = <2>; 212 #interrupt-cells = <2>;
212 reg = <40000 40000>; 213 reg = <0x40000 0x40000>;
213 compatible = "chrp,open-pic"; 214 compatible = "chrp,open-pic";
214 device_type = "open-pic"; 215 device_type = "open-pic";
215 big-endian; 216 big-endian;
216 }; 217 };
217 218
218 par_io@e0100 { 219 par_io@e0100 {
219 reg = <e0100 100>; 220 reg = <0xe0100 0x100>;
220 device_type = "par_io"; 221 device_type = "par_io";
221 num-ports = <7>; 222 num-ports = <7>;
222 223
223 pio1: ucc_pin@01 { 224 pio1: ucc_pin@01 {
224 pio-map = < 225 pio-map = <
225 /* port pin dir open_drain assignment has_irq */ 226 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */ 227 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */ 228 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */ 229 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */ 230 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */ 231 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */ 232 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */ 233 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */ 234 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */ 235 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */ 236 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */ 237 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */ 238 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */ 239 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */ 240 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */ 241 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */ 242 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */ 243 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */ 244 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */ 245 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */ 246 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */ 247 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */ 248 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */ 249 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
249 }; 250 };
250 251
251 pio2: ucc_pin@02 { 252 pio2: ucc_pin@02 {
252 pio-map = < 253 pio-map = <
253 /* port pin dir open_drain assignment has_irq */ 254 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */ 255 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */ 256 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */ 257 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */ 258 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */ 259 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */ 260 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */ 261 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */ 262 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */ 263 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */ 264 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */ 265 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */ 266 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */ 267 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */ 268 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */ 269 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */ 270 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */ 271 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */ 272 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */ 273 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */ 274 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */ 275 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */ 276 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */ 277 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */ 278 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */ 279 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
279 }; 280 };
280 }; 281 };
281 }; 282 };
@@ -285,28 +286,28 @@
285 #size-cells = <1>; 286 #size-cells = <1>;
286 device_type = "qe"; 287 device_type = "qe";
287 compatible = "fsl,qe"; 288 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>; 289 ranges = <0x0 0xe0080000 0x40000>;
289 reg = <e0080000 480>; 290 reg = <0xe0080000 0x480>;
290 brg-frequency = <0>; 291 brg-frequency = <0>;
291 bus-frequency = <179A7B00>; 292 bus-frequency = <396000000>;
292 293
293 muram@10000 { 294 muram@10000 {
294 #address-cells = <1>; 295 #address-cells = <1>;
295 #size-cells = <1>; 296 #size-cells = <1>;
296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 297 compatible = "fsl,qe-muram", "fsl,cpm-muram";
297 ranges = <0 00010000 0000c000>; 298 ranges = <0x0 0x10000 0xc000>;
298 299
299 data-only@0 { 300 data-only@0 {
300 compatible = "fsl,qe-muram-data", 301 compatible = "fsl,qe-muram-data",
301 "fsl,cpm-muram-data"; 302 "fsl,cpm-muram-data";
302 reg = <0 c000>; 303 reg = <0x0 0xc000>;
303 }; 304 };
304 }; 305 };
305 306
306 spi@4c0 { 307 spi@4c0 {
307 cell-index = <0>; 308 cell-index = <0>;
308 compatible = "fsl,spi"; 309 compatible = "fsl,spi";
309 reg = <4c0 40>; 310 reg = <0x4c0 0x40>;
310 interrupts = <2>; 311 interrupts = <2>;
311 interrupt-parent = <&qeic>; 312 interrupt-parent = <&qeic>;
312 mode = "cpu"; 313 mode = "cpu";
@@ -315,7 +316,7 @@
315 spi@500 { 316 spi@500 {
316 cell-index = <1>; 317 cell-index = <1>;
317 compatible = "fsl,spi"; 318 compatible = "fsl,spi";
318 reg = <500 40>; 319 reg = <0x500 0x40>;
319 interrupts = <1>; 320 interrupts = <1>;
320 interrupt-parent = <&qeic>; 321 interrupt-parent = <&qeic>;
321 mode = "cpu"; 322 mode = "cpu";
@@ -325,8 +326,8 @@
325 device_type = "network"; 326 device_type = "network";
326 compatible = "ucc_geth"; 327 compatible = "ucc_geth";
327 cell-index = <1>; 328 cell-index = <1>;
328 reg = <2000 200>; 329 reg = <0x2000 0x200>;
329 interrupts = <20>; 330 interrupts = <32>;
330 interrupt-parent = <&qeic>; 331 interrupt-parent = <&qeic>;
331 local-mac-address = [ 00 00 00 00 00 00 ]; 332 local-mac-address = [ 00 00 00 00 00 00 ];
332 rx-clock-name = "none"; 333 rx-clock-name = "none";
@@ -340,8 +341,8 @@
340 device_type = "network"; 341 device_type = "network";
341 compatible = "ucc_geth"; 342 compatible = "ucc_geth";
342 cell-index = <2>; 343 cell-index = <2>;
343 reg = <3000 200>; 344 reg = <0x3000 0x200>;
344 interrupts = <21>; 345 interrupts = <33>;
345 interrupt-parent = <&qeic>; 346 interrupt-parent = <&qeic>;
346 local-mac-address = [ 00 00 00 00 00 00 ]; 347 local-mac-address = [ 00 00 00 00 00 00 ];
347 rx-clock-name = "none"; 348 rx-clock-name = "none";
@@ -354,7 +355,7 @@
354 mdio@2120 { 355 mdio@2120 {
355 #address-cells = <1>; 356 #address-cells = <1>;
356 #size-cells = <0>; 357 #size-cells = <0>;
357 reg = <2120 18>; 358 reg = <0x2120 0x18>;
358 compatible = "fsl,ucc-mdio"; 359 compatible = "fsl,ucc-mdio";
359 360
360 /* These are the same PHYs as on 361 /* These are the same PHYs as on
@@ -362,25 +363,25 @@
362 qe_phy0: ethernet-phy@07 { 363 qe_phy0: ethernet-phy@07 {
363 interrupt-parent = <&mpic>; 364 interrupt-parent = <&mpic>;
364 interrupts = <1 1>; 365 interrupts = <1 1>;
365 reg = <7>; 366 reg = <0x7>;
366 device_type = "ethernet-phy"; 367 device_type = "ethernet-phy";
367 }; 368 };
368 qe_phy1: ethernet-phy@01 { 369 qe_phy1: ethernet-phy@01 {
369 interrupt-parent = <&mpic>; 370 interrupt-parent = <&mpic>;
370 interrupts = <2 1>; 371 interrupts = <2 1>;
371 reg = <1>; 372 reg = <0x1>;
372 device_type = "ethernet-phy"; 373 device_type = "ethernet-phy";
373 }; 374 };
374 qe_phy2: ethernet-phy@02 { 375 qe_phy2: ethernet-phy@02 {
375 interrupt-parent = <&mpic>; 376 interrupt-parent = <&mpic>;
376 interrupts = <1 1>; 377 interrupts = <1 1>;
377 reg = <2>; 378 reg = <0x2>;
378 device_type = "ethernet-phy"; 379 device_type = "ethernet-phy";
379 }; 380 };
380 qe_phy3: ethernet-phy@03 { 381 qe_phy3: ethernet-phy@03 {
381 interrupt-parent = <&mpic>; 382 interrupt-parent = <&mpic>;
382 interrupts = <2 1>; 383 interrupts = <2 1>;
383 reg = <3>; 384 reg = <0x3>;
384 device_type = "ethernet-phy"; 385 device_type = "ethernet-phy";
385 }; 386 };
386 }; 387 };
@@ -390,9 +391,9 @@
390 compatible = "fsl,qe-ic"; 391 compatible = "fsl,qe-ic";
391 #address-cells = <0>; 392 #address-cells = <0>;
392 #interrupt-cells = <1>; 393 #interrupt-cells = <1>;
393 reg = <80 80>; 394 reg = <0x80 0x80>;
394 big-endian; 395 big-endian;
395 interrupts = <2e 2 2e 2>; //high:30 low:30 396 interrupts = <46 2 46 2>; //high:30 low:30
396 interrupt-parent = <&mpic>; 397 interrupt-parent = <&mpic>;
397 }; 398 };
398 399
@@ -400,30 +401,30 @@
400 401
401 pci0: pci@e0008000 { 402 pci0: pci@e0008000 {
402 cell-index = <0>; 403 cell-index = <0>;
403 interrupt-map-mask = <f800 0 0 7>; 404 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
404 interrupt-map = < 405 interrupt-map = <
405 /* IDSEL 0x12 AD18 */ 406 /* IDSEL 0x12 AD18 */
406 9000 0 0 1 &mpic 5 1 407 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
407 9000 0 0 2 &mpic 6 1 408 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
408 9000 0 0 3 &mpic 7 1 409 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
409 9000 0 0 4 &mpic 4 1 410 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
410 411
411 /* IDSEL 0x13 AD19 */ 412 /* IDSEL 0x13 AD19 */
412 9800 0 0 1 &mpic 6 1 413 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
413 9800 0 0 2 &mpic 7 1 414 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
414 9800 0 0 3 &mpic 4 1 415 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
415 9800 0 0 4 &mpic 5 1>; 416 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
416 417
417 interrupt-parent = <&mpic>; 418 interrupt-parent = <&mpic>;
418 interrupts = <18 2>; 419 interrupts = <24 2>;
419 bus-range = <0 ff>; 420 bus-range = <0 255>;
420 ranges = <02000000 0 80000000 80000000 0 20000000 421 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
421 01000000 0 00000000 e2000000 0 00800000>; 422 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
422 clock-frequency = <3f940aa>; 423 clock-frequency = <66666666>;
423 #interrupt-cells = <1>; 424 #interrupt-cells = <1>;
424 #size-cells = <2>; 425 #size-cells = <2>;
425 #address-cells = <3>; 426 #address-cells = <3>;
426 reg = <e0008000 1000>; 427 reg = <0xe0008000 0x1000>;
427 compatible = "fsl,mpc8540-pci"; 428 compatible = "fsl,mpc8540-pci";
428 device_type = "pci"; 429 device_type = "pci";
429 }; 430 };
@@ -431,39 +432,39 @@
431 /* PCI Express */ 432 /* PCI Express */
432 pci1: pcie@e000a000 { 433 pci1: pcie@e000a000 {
433 cell-index = <2>; 434 cell-index = <2>;
434 interrupt-map-mask = <f800 0 0 7>; 435 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
435 interrupt-map = < 436 interrupt-map = <
436 437
437 /* IDSEL 0x0 (PEX) */ 438 /* IDSEL 0x0 (PEX) */
438 00000 0 0 1 &mpic 0 1 439 00000 0x0 0x0 0x1 &mpic 0x0 0x1
439 00000 0 0 2 &mpic 1 1 440 00000 0x0 0x0 0x2 &mpic 0x1 0x1
440 00000 0 0 3 &mpic 2 1 441 00000 0x0 0x0 0x3 &mpic 0x2 0x1
441 00000 0 0 4 &mpic 3 1>; 442 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
442 443
443 interrupt-parent = <&mpic>; 444 interrupt-parent = <&mpic>;
444 interrupts = <1a 2>; 445 interrupts = <26 2>;
445 bus-range = <0 ff>; 446 bus-range = <0 255>;
446 ranges = <02000000 0 a0000000 a0000000 0 10000000 447 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
447 01000000 0 00000000 e2800000 0 00800000>; 448 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
448 clock-frequency = <1fca055>; 449 clock-frequency = <33333333>;
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <e000a000 1000>; 453 reg = <0xe000a000 0x1000>;
453 compatible = "fsl,mpc8548-pcie"; 454 compatible = "fsl,mpc8548-pcie";
454 device_type = "pci"; 455 device_type = "pci";
455 pcie@0 { 456 pcie@0 {
456 reg = <0 0 0 0 0>; 457 reg = <0x0 0x0 0x0 0x0 0x0>;
457 #size-cells = <2>; 458 #size-cells = <2>;
458 #address-cells = <3>; 459 #address-cells = <3>;
459 device_type = "pci"; 460 device_type = "pci";
460 ranges = <02000000 0 a0000000 461 ranges = <0x2000000 0x0 0xa0000000
461 02000000 0 a0000000 462 0x2000000 0x0 0xa0000000
462 0 10000000 463 0x0 0x10000000
463 464
464 01000000 0 00000000 465 0x1000000 0x0 0x0
465 01000000 0 00000000 466 0x1000000 0x0 0x0
466 0 00800000>; 467 0x0 0x800000>;
467 }; 468 };
468 }; 469 };
469}; 470};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 02:32:05 -0400