powerpc/85xx: Refactor mpc8548cds device tree

* Create mpc8548cds.dtsi
* Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi
* Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b
* Rename mpc8548cds.dts to mpc8548cds_32b.dts

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 86 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/mpc8548cds_32b.dts b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
new file mode 100644
index 000000000000..6fd63163fc6b
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
@@ -0,0 +1,86 @@
+/*
+ * MPC8548 CDS Device Tree Source (32-bit address map)
+ *
+ * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/mpc8548si-pre.dtsi"
+
+/ {
+        model = "MPC8548CDS";
+        compatible = "MPC8548CDS", "MPC85xxCDS";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
+        };
+
+        board_lbc: lbc: localbus@e0005000 {
+                reg = <0 0xe0005000 0 0x1000>;
+
+                ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+                          0x1 0x0 0x0 0xf8004000 0x00001000>;
+
+        };
+
+        board_soc: soc: soc8548@e0000000 {
+                ranges = <0 0x0 0xe0000000 0x100000>;
+        };
+
+        board_pci0: pci0: pci@e0008000 {
+                reg = <0 0xe0008000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+        };
+
+        pci1: pci@e0009000 {
+                reg = <0 0xe0009000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x15 */
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
+                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+        };
+
+        pci2: pcie@e000a000 {
+                reg = <0 0xe000a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        rio: rapidio@e00c0000 {
+                reg = <0x0 0xe00c0000 0x0 0x20000>;
+                port1 {
+                        ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
+                };
+        };
+};
+
+/*
+ * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask.
+ */
+
+/include/ "fsl/mpc8548si-post.dtsi"
+/include/ "mpc8548cds.dtsi"