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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-15 22:04:58 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-15 22:04:58 -0400 |
commit | 45158894d4d6704afbb4cefe55e5f6ca279fe12a (patch) | |
tree | d57e745e2d0848d75cd4a46ca04178b16f186b50 /arch/powerpc/boot/dts/mpc8541cds.dts | |
parent | 89a93f2f4834f8c126e8d9dd6b368d0b9e21ec3d (diff) | |
parent | 84c3d4aaec3338201b449034beac41635866bddf (diff) |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (249 commits)
powerpc: Fix pte_update for CONFIG_PTE_64BIT and !PTE_ATOMIC_UPDATES
powerpc: Fix a build problem on ppc32 with new DMA_ATTRs
ibm_newemac: Add MII mode support to the EMAC RGMII bridge.
powerpc: Don't spin on sync instruction at boot time
powerpc: Add VSX load/store alignment exception handler
powerpc: fix giveup_vsx to save registers correctly
powerpc: support for latencytop
powerpc: Remove unnecessary condition when sanity-checking WIMG bits
powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT
powerpc: Add driver for Barrier Synchronization Register
powerpc: mman.h export fixups
powerpc/fsl: update crypto node definition and device tree instances
powerpc/fsl: Refactor device bindings
powerpc/85xx: Minor fixes for 85xxds and 8536ds board.
powerpc: Add 82xx/83xx/86xx to 6xx Multiplatform
powerpc/85xx: publish of device for cds platforms
powerpc/booke: don't reinitialize time base
powerpc/86xx: Refactor pic init
powerpc/CPM: Add i2c pins to dts and board setup
cpm_uart: Support uart_wait_until_sent()
...
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8541cds.dts')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8541cds.dts | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 663c7c50ca45..c4469f19ff82 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts | |||
@@ -40,6 +40,7 @@ | |||
40 | timebase-frequency = <0>; // 33 MHz, from uboot | 40 | timebase-frequency = <0>; // 33 MHz, from uboot |
41 | bus-frequency = <0>; // 166 MHz | 41 | bus-frequency = <0>; // 166 MHz |
42 | clock-frequency = <0>; // 825 MHz, from uboot | 42 | clock-frequency = <0>; // 825 MHz, from uboot |
43 | next-level-cache = <&L2>; | ||
43 | }; | 44 | }; |
44 | }; | 45 | }; |
45 | 46 | ||
@@ -63,7 +64,7 @@ | |||
63 | interrupts = <18 2>; | 64 | interrupts = <18 2>; |
64 | }; | 65 | }; |
65 | 66 | ||
66 | l2-cache-controller@20000 { | 67 | L2: l2-cache-controller@20000 { |
67 | compatible = "fsl,8541-l2-cache-controller"; | 68 | compatible = "fsl,8541-l2-cache-controller"; |
68 | reg = <0x20000 0x1000>; | 69 | reg = <0x20000 0x1000>; |
69 | cache-line-size = <32>; // 32 bytes | 70 | cache-line-size = <32>; // 32 bytes |
@@ -83,6 +84,47 @@ | |||
83 | dfsrr; | 84 | dfsrr; |
84 | }; | 85 | }; |
85 | 86 | ||
87 | dma@21300 { | ||
88 | #address-cells = <1>; | ||
89 | #size-cells = <1>; | ||
90 | compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; | ||
91 | reg = <0x21300 0x4>; | ||
92 | ranges = <0x0 0x21100 0x200>; | ||
93 | cell-index = <0>; | ||
94 | dma-channel@0 { | ||
95 | compatible = "fsl,mpc8541-dma-channel", | ||
96 | "fsl,eloplus-dma-channel"; | ||
97 | reg = <0x0 0x80>; | ||
98 | cell-index = <0>; | ||
99 | interrupt-parent = <&mpic>; | ||
100 | interrupts = <20 2>; | ||
101 | }; | ||
102 | dma-channel@80 { | ||
103 | compatible = "fsl,mpc8541-dma-channel", | ||
104 | "fsl,eloplus-dma-channel"; | ||
105 | reg = <0x80 0x80>; | ||
106 | cell-index = <1>; | ||
107 | interrupt-parent = <&mpic>; | ||
108 | interrupts = <21 2>; | ||
109 | }; | ||
110 | dma-channel@100 { | ||
111 | compatible = "fsl,mpc8541-dma-channel", | ||
112 | "fsl,eloplus-dma-channel"; | ||
113 | reg = <0x100 0x80>; | ||
114 | cell-index = <2>; | ||
115 | interrupt-parent = <&mpic>; | ||
116 | interrupts = <22 2>; | ||
117 | }; | ||
118 | dma-channel@180 { | ||
119 | compatible = "fsl,mpc8541-dma-channel", | ||
120 | "fsl,eloplus-dma-channel"; | ||
121 | reg = <0x180 0x80>; | ||
122 | cell-index = <3>; | ||
123 | interrupt-parent = <&mpic>; | ||
124 | interrupts = <23 2>; | ||
125 | }; | ||
126 | }; | ||
127 | |||
86 | mdio@24520 { | 128 | mdio@24520 { |
87 | #address-cells = <1>; | 129 | #address-cells = <1>; |
88 | #size-cells = <0>; | 130 | #size-cells = <0>; |
@@ -147,15 +189,24 @@ | |||
147 | interrupt-parent = <&mpic>; | 189 | interrupt-parent = <&mpic>; |
148 | }; | 190 | }; |
149 | 191 | ||
192 | crypto@30000 { | ||
193 | compatible = "fsl,sec2.0"; | ||
194 | reg = <0x30000 0x10000>; | ||
195 | interrupts = <45 2>; | ||
196 | interrupt-parent = <&mpic>; | ||
197 | fsl,num-channels = <4>; | ||
198 | fsl,channel-fifo-len = <24>; | ||
199 | fsl,exec-units-mask = <0x7e>; | ||
200 | fsl,descriptor-types-mask = <0x01010ebf>; | ||
201 | }; | ||
202 | |||
150 | mpic: pic@40000 { | 203 | mpic: pic@40000 { |
151 | clock-frequency = <0>; | ||
152 | interrupt-controller; | 204 | interrupt-controller; |
153 | #address-cells = <0>; | 205 | #address-cells = <0>; |
154 | #interrupt-cells = <2>; | 206 | #interrupt-cells = <2>; |
155 | reg = <0x40000 0x40000>; | 207 | reg = <0x40000 0x40000>; |
156 | compatible = "chrp,open-pic"; | 208 | compatible = "chrp,open-pic"; |
157 | device_type = "open-pic"; | 209 | device_type = "open-pic"; |
158 | big-endian; | ||
159 | }; | 210 | }; |
160 | 211 | ||
161 | cpm@919c0 { | 212 | cpm@919c0 { |