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authorKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 02:28:15 -0400
commit32f960e9439bbe72c45f8cd854049254122fc198 (patch)
tree7773600dbe67df8bd07b35e865a7a7c1b7a863fd /arch/powerpc/boot/dts/mpc8540ads.dts
parenta5dc66e2ab2e2cf641346b056a69a67cfcf9458c (diff)
[POWERPC] 85xx: Convert dts to v1 syntax
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8540ads.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts173
1 files changed, 87 insertions, 86 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 975248491b7b..18033ed0b535 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8540 ADS Device Tree Source 2 * MPC8540 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8540ADS"; 15 model = "MPC8540ADS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8540@0 { 33 PowerPC,8540@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8540@e0000000 { 51 soc8540@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00100000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,8540-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,24 +87,24 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 phy3: ethernet-phy@3 { 104 phy3: ethernet-phy@3 {
104 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
105 interrupts = <7 1>; 106 interrupts = <7 1>;
106 reg = <3>; 107 reg = <0x3>;
107 device_type = "ethernet-phy"; 108 device_type = "ethernet-phy";
108 }; 109 };
109 }; 110 };
@@ -113,9 +114,9 @@
113 device_type = "network"; 114 device_type = "network";
114 model = "TSEC"; 115 model = "TSEC";
115 compatible = "gianfar"; 116 compatible = "gianfar";
116 reg = <24000 1000>; 117 reg = <0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ]; 118 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <1d 2 1e 2 22 2>; 119 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 phy-handle = <&phy0>; 121 phy-handle = <&phy0>;
121 }; 122 };
@@ -125,9 +126,9 @@
125 device_type = "network"; 126 device_type = "network";
126 model = "TSEC"; 127 model = "TSEC";
127 compatible = "gianfar"; 128 compatible = "gianfar";
128 reg = <25000 1000>; 129 reg = <0x25000 0x1000>;
129 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <23 2 24 2 28 2>; 131 interrupts = <35 2 36 2 40 2>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 phy-handle = <&phy1>; 133 phy-handle = <&phy1>;
133 }; 134 };
@@ -137,9 +138,9 @@
137 device_type = "network"; 138 device_type = "network";
138 model = "FEC"; 139 model = "FEC";
139 compatible = "gianfar"; 140 compatible = "gianfar";
140 reg = <26000 1000>; 141 reg = <0x26000 0x1000>;
141 local-mac-address = [ 00 00 00 00 00 00 ]; 142 local-mac-address = [ 00 00 00 00 00 00 ];
142 interrupts = <29 2>; 143 interrupts = <41 2>;
143 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>;
144 phy-handle = <&phy3>; 145 phy-handle = <&phy3>;
145 }; 146 };
@@ -148,9 +149,9 @@
148 cell-index = <0>; 149 cell-index = <0>;
149 device_type = "serial"; 150 device_type = "serial";
150 compatible = "ns16550"; 151 compatible = "ns16550";
151 reg = <4500 100>; // reg base, size 152 reg = <0x4500 0x100>; // reg base, size
152 clock-frequency = <0>; // should we fill in in uboot? 153 clock-frequency = <0>; // should we fill in in uboot?
153 interrupts = <2a 2>; 154 interrupts = <42 2>;
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 }; 156 };
156 157
@@ -158,9 +159,9 @@
158 cell-index = <1>; 159 cell-index = <1>;
159 device_type = "serial"; 160 device_type = "serial";
160 compatible = "ns16550"; 161 compatible = "ns16550";
161 reg = <4600 100>; // reg base, size 162 reg = <0x4600 0x100>; // reg base, size
162 clock-frequency = <0>; // should we fill in in uboot? 163 clock-frequency = <0>; // should we fill in in uboot?
163 interrupts = <2a 2>; 164 interrupts = <42 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 }; 166 };
166 mpic: pic@40000 { 167 mpic: pic@40000 {
@@ -168,7 +169,7 @@
168 interrupt-controller; 169 interrupt-controller;
169 #address-cells = <0>; 170 #address-cells = <0>;
170 #interrupt-cells = <2>; 171 #interrupt-cells = <2>;
171 reg = <40000 40000>; 172 reg = <0x40000 0x40000>;
172 compatible = "chrp,open-pic"; 173 compatible = "chrp,open-pic";
173 device_type = "open-pic"; 174 device_type = "open-pic";
174 big-endian; 175 big-endian;
@@ -177,90 +178,90 @@
177 178
178 pci0: pci@e0008000 { 179 pci0: pci@e0008000 {
179 cell-index = <0>; 180 cell-index = <0>;
180 interrupt-map-mask = <f800 0 0 7>; 181 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
181 interrupt-map = < 182 interrupt-map = <
182 183
183 /* IDSEL 0x02 */ 184 /* IDSEL 0x02 */
184 1000 0 0 1 &mpic 1 1 185 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
185 1000 0 0 2 &mpic 2 1 186 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
186 1000 0 0 3 &mpic 3 1 187 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
187 1000 0 0 4 &mpic 4 1 188 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
188 189
189 /* IDSEL 0x03 */ 190 /* IDSEL 0x03 */
190 1800 0 0 1 &mpic 4 1 191 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
191 1800 0 0 2 &mpic 1 1 192 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
192 1800 0 0 3 &mpic 2 1 193 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
193 1800 0 0 4 &mpic 3 1 194 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
194 195
195 /* IDSEL 0x04 */ 196 /* IDSEL 0x04 */
196 2000 0 0 1 &mpic 3 1 197 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
197 2000 0 0 2 &mpic 4 1 198 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
198 2000 0 0 3 &mpic 1 1 199 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
199 2000 0 0 4 &mpic 2 1 200 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
200 201
201 /* IDSEL 0x05 */ 202 /* IDSEL 0x05 */
202 2800 0 0 1 &mpic 2 1 203 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
203 2800 0 0 2 &mpic 3 1 204 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
204 2800 0 0 3 &mpic 4 1 205 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
205 2800 0 0 4 &mpic 1 1 206 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
206 207
207 /* IDSEL 0x0c */ 208 /* IDSEL 0x0c */
208 6000 0 0 1 &mpic 1 1 209 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
209 6000 0 0 2 &mpic 2 1 210 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
210 6000 0 0 3 &mpic 3 1 211 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
211 6000 0 0 4 &mpic 4 1 212 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
212 213
213 /* IDSEL 0x0d */ 214 /* IDSEL 0x0d */
214 6800 0 0 1 &mpic 4 1 215 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
215 6800 0 0 2 &mpic 1 1 216 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
216 6800 0 0 3 &mpic 2 1 217 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
217 6800 0 0 4 &mpic 3 1 218 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
218 219
219 /* IDSEL 0x0e */ 220 /* IDSEL 0x0e */
220 7000 0 0 1 &mpic 3 1 221 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
221 7000 0 0 2 &mpic 4 1 222 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
222 7000 0 0 3 &mpic 1 1 223 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
223 7000 0 0 4 &mpic 2 1 224 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
224 225
225 /* IDSEL 0x0f */ 226 /* IDSEL 0x0f */
226 7800 0 0 1 &mpic 2 1 227 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
227 7800 0 0 2 &mpic 3 1 228 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
228 7800 0 0 3 &mpic 4 1 229 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
229 7800 0 0 4 &mpic 1 1 230 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
230 231
231 /* IDSEL 0x12 */ 232 /* IDSEL 0x12 */
232 9000 0 0 1 &mpic 1 1 233 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
233 9000 0 0 2 &mpic 2 1 234 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
234 9000 0 0 3 &mpic 3 1 235 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
235 9000 0 0 4 &mpic 4 1 236 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
236 237
237 /* IDSEL 0x13 */ 238 /* IDSEL 0x13 */
238 9800 0 0 1 &mpic 4 1 239 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
239 9800 0 0 2 &mpic 1 1 240 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
240 9800 0 0 3 &mpic 2 1 241 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
241 9800 0 0 4 &mpic 3 1 242 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
242 243
243 /* IDSEL 0x14 */ 244 /* IDSEL 0x14 */
244 a000 0 0 1 &mpic 3 1 245 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
245 a000 0 0 2 &mpic 4 1 246 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
246 a000 0 0 3 &mpic 1 1 247 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
247 a000 0 0 4 &mpic 2 1 248 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
248 249
249 /* IDSEL 0x15 */ 250 /* IDSEL 0x15 */
250 a800 0 0 1 &mpic 2 1 251 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
251 a800 0 0 2 &mpic 3 1 252 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
252 a800 0 0 3 &mpic 4 1 253 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
253 a800 0 0 4 &mpic 1 1>; 254 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
254 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
255 interrupts = <18 2>; 256 interrupts = <24 2>;
256 bus-range = <0 0>; 257 bus-range = <0 0>;
257 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
258 01000000 0 00000000 e2000000 0 00100000>; 259 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
259 clock-frequency = <3f940aa>; 260 clock-frequency = <66666666>;
260 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
261 #size-cells = <2>; 262 #size-cells = <2>;
262 #address-cells = <3>; 263 #address-cells = <3>;
263 reg = <e0008000 1000>; 264 reg = <0xe0008000 0x1000>;
264 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
265 device_type = "pci"; 266 device_type = "pci";
266 }; 267 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 05:46:00 -0400