aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/mpc836x_mds.dts
diff options
context:
space:
mode:
authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-28 16:09:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 17:16:38 -0500
commitcda13dd164f91df79ba797ab84848352b03de115 (patch)
treef366a541f2358c4b74b3e4c8b7ec04994c23d3e8 /arch/powerpc/boot/dts/mpc836x_mds.dts
parenta6f71745969d495d697d1ccd96385d2f7a963375 (diff)
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
This patch converts the remaining 83xx boards to the dts-v1 format. This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx, mpc8349emitxgp and the mpc836x_mds. The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already dts-v1 and only undergo minor changes for the sake of formatting consistency across the whole group of boards; i.e. the idea being that you can do a "diff -u board_A.dts board_B.dts" and see something meaningful. The general rule I've applied is that entries for values normally parsed by humans are left in decimal (i.e. IRQ, cache size, clock rates, basic counts and indexes) and all other data (i.e. reg and ranges, IRQ flags etc.) remain in hex. I've used dtc to confirm that the output prior to this changeset matches the output after this changeset is applied for all boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc836x_mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts260
1 files changed, 131 insertions, 129 deletions
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index dc6caf0b4c2d..55f03e8dc97f 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -14,6 +14,8 @@
14/memreserve/ 00000000 1000000; 14/memreserve/ 00000000 1000000;
15*/ 15*/
16 16
17/dts-v1/;
18
17/ { 19/ {
18 model = "MPC8360MDS"; 20 model = "MPC8360MDS";
19 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS"; 21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
@@ -34,39 +36,39 @@
34 36
35 PowerPC,8360@0 { 37 PowerPC,8360@0 {
36 device_type = "cpu"; 38 device_type = "cpu";
37 reg = <0>; 39 reg = <0x0>;
38 d-cache-line-size = <20>; // 32 bytes 40 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <20>; // 32 bytes 41 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <8000>; // L1, 32K 42 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <8000>; // L1, 32K 43 i-cache-size = <32768>; // L1, 32K
42 timebase-frequency = <3EF1480>; 44 timebase-frequency = <66000000>;
43 bus-frequency = <FBC5200>; 45 bus-frequency = <264000000>;
44 clock-frequency = <1F78A400>; 46 clock-frequency = <528000000>;
45 }; 47 };
46 }; 48 };
47 49
48 memory { 50 memory {
49 device_type = "memory"; 51 device_type = "memory";
50 reg = <00000000 10000000>; 52 reg = <0x00000000 0x10000000>;
51 }; 53 };
52 54
53 bcsr@f8000000 { 55 bcsr@f8000000 {
54 device_type = "board-control"; 56 device_type = "board-control";
55 reg = <f8000000 8000>; 57 reg = <0xf8000000 0x8000>;
56 }; 58 };
57 59
58 soc8360@e0000000 { 60 soc8360@e0000000 {
59 #address-cells = <1>; 61 #address-cells = <1>;
60 #size-cells = <1>; 62 #size-cells = <1>;
61 device_type = "soc"; 63 device_type = "soc";
62 ranges = <0 e0000000 00100000>; 64 ranges = <0x0 0xe0000000 0x00100000>;
63 reg = <e0000000 00000200>; 65 reg = <0xe0000000 0x00000200>;
64 bus-frequency = <FBC5200>; 66 bus-frequency = <264000000>;
65 67
66 wdt@200 { 68 wdt@200 {
67 device_type = "watchdog"; 69 device_type = "watchdog";
68 compatible = "mpc83xx_wdt"; 70 compatible = "mpc83xx_wdt";
69 reg = <200 100>; 71 reg = <0x200 0x100>;
70 }; 72 };
71 73
72 i2c@3000 { 74 i2c@3000 {
@@ -74,14 +76,14 @@
74 #size-cells = <0>; 76 #size-cells = <0>;
75 cell-index = <0>; 77 cell-index = <0>;
76 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
77 reg = <3000 100>; 79 reg = <0x3000 0x100>;
78 interrupts = <e 8>; 80 interrupts = <14 0x8>;
79 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
80 dfsrr; 82 dfsrr;
81 83
82 rtc@68 { 84 rtc@68 {
83 compatible = "dallas,ds1374"; 85 compatible = "dallas,ds1374";
84 reg = <68>; 86 reg = <0x68>;
85 }; 87 };
86 }; 88 };
87 89
@@ -90,9 +92,9 @@
90 #size-cells = <0>; 92 #size-cells = <0>;
91 cell-index = <1>; 93 cell-index = <1>;
92 compatible = "fsl-i2c"; 94 compatible = "fsl-i2c";
93 reg = <3100 100>; 95 reg = <0x3100 0x100>;
94 interrupts = <f 8>; 96 interrupts = <15 0x8>;
95 interrupt-parent = < &ipic >; 97 interrupt-parent = <&ipic>;
96 dfsrr; 98 dfsrr;
97 }; 99 };
98 100
@@ -100,46 +102,46 @@
100 cell-index = <0>; 102 cell-index = <0>;
101 device_type = "serial"; 103 device_type = "serial";
102 compatible = "ns16550"; 104 compatible = "ns16550";
103 reg = <4500 100>; 105 reg = <0x4500 0x100>;
104 clock-frequency = <FBC5200>; 106 clock-frequency = <264000000>;
105 interrupts = <9 8>; 107 interrupts = <9 0x8>;
106 interrupt-parent = < &ipic >; 108 interrupt-parent = <&ipic>;
107 }; 109 };
108 110
109 serial1: serial@4600 { 111 serial1: serial@4600 {
110 cell-index = <1>; 112 cell-index = <1>;
111 device_type = "serial"; 113 device_type = "serial";
112 compatible = "ns16550"; 114 compatible = "ns16550";
113 reg = <4600 100>; 115 reg = <0x4600 0x100>;
114 clock-frequency = <FBC5200>; 116 clock-frequency = <264000000>;
115 interrupts = <a 8>; 117 interrupts = <10 0x8>;
116 interrupt-parent = < &ipic >; 118 interrupt-parent = <&ipic>;
117 }; 119 };
118 120
119 crypto@30000 { 121 crypto@30000 {
120 device_type = "crypto"; 122 device_type = "crypto";
121 model = "SEC2"; 123 model = "SEC2";
122 compatible = "talitos"; 124 compatible = "talitos";
123 reg = <30000 10000>; 125 reg = <0x30000 0x10000>;
124 interrupts = <b 8>; 126 interrupts = <11 0x8>;
125 interrupt-parent = < &ipic >; 127 interrupt-parent = <&ipic>;
126 num-channels = <4>; 128 num-channels = <4>;
127 channel-fifo-len = <18>; 129 channel-fifo-len = <24>;
128 exec-units-mask = <0000007e>; 130 exec-units-mask = <0x0000007e>;
129 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 131 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
130 descriptor-types-mask = <01010ebf>; 132 descriptor-types-mask = <0x01010ebf>;
131 }; 133 };
132 134
133 ipic: pic@700 { 135 ipic: pic@700 {
134 interrupt-controller; 136 interrupt-controller;
135 #address-cells = <0>; 137 #address-cells = <0>;
136 #interrupt-cells = <2>; 138 #interrupt-cells = <2>;
137 reg = <700 100>; 139 reg = <0x700 0x100>;
138 device_type = "ipic"; 140 device_type = "ipic";
139 }; 141 };
140 142
141 par_io@1400 { 143 par_io@1400 {
142 reg = <1400 100>; 144 reg = <0x1400 0x100>;
143 device_type = "par_io"; 145 device_type = "par_io";
144 num-ports = <7>; 146 num-ports = <7>;
145 147
@@ -153,19 +155,19 @@
153 1 6 1 0 3 0 /* TxD4 */ 155 1 6 1 0 3 0 /* TxD4 */
154 1 7 1 0 1 0 /* TxD5 */ 156 1 7 1 0 1 0 /* TxD5 */
155 1 9 1 0 2 0 /* TxD6 */ 157 1 9 1 0 2 0 /* TxD6 */
156 1 a 1 0 2 0 /* TxD7 */ 158 1 10 1 0 2 0 /* TxD7 */
157 0 9 2 0 1 0 /* RxD0 */ 159 0 9 2 0 1 0 /* RxD0 */
158 0 a 2 0 1 0 /* RxD1 */ 160 0 10 2 0 1 0 /* RxD1 */
159 0 b 2 0 1 0 /* RxD2 */ 161 0 11 2 0 1 0 /* RxD2 */
160 0 c 2 0 1 0 /* RxD3 */ 162 0 12 2 0 1 0 /* RxD3 */
161 0 d 2 0 1 0 /* RxD4 */ 163 0 13 2 0 1 0 /* RxD4 */
162 1 1 2 0 2 0 /* RxD5 */ 164 1 1 2 0 2 0 /* RxD5 */
163 1 0 2 0 2 0 /* RxD6 */ 165 1 0 2 0 2 0 /* RxD6 */
164 1 4 2 0 2 0 /* RxD7 */ 166 1 4 2 0 2 0 /* RxD7 */
165 0 7 1 0 1 0 /* TX_EN */ 167 0 7 1 0 1 0 /* TX_EN */
166 0 8 1 0 1 0 /* TX_ER */ 168 0 8 1 0 1 0 /* TX_ER */
167 0 f 2 0 1 0 /* RX_DV */ 169 0 15 2 0 1 0 /* RX_DV */
168 0 10 2 0 1 0 /* RX_ER */ 170 0 16 2 0 1 0 /* RX_ER */
169 0 0 2 0 1 0 /* RX_CLK */ 171 0 0 2 0 1 0 /* RX_CLK */
170 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 172 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
171 2 8 2 0 1 0>; /* GTX125 - CLK9 */ 173 2 8 2 0 1 0>; /* GTX125 - CLK9 */
@@ -173,27 +175,27 @@
173 pio2: ucc_pin@02 { 175 pio2: ucc_pin@02 {
174 pio-map = < 176 pio-map = <
175 /* port pin dir open_drain assignment has_irq */ 177 /* port pin dir open_drain assignment has_irq */
176 0 11 1 0 1 0 /* TxD0 */ 178 0 17 1 0 1 0 /* TxD0 */
177 0 12 1 0 1 0 /* TxD1 */ 179 0 18 1 0 1 0 /* TxD1 */
178 0 13 1 0 1 0 /* TxD2 */ 180 0 19 1 0 1 0 /* TxD2 */
179 0 14 1 0 1 0 /* TxD3 */ 181 0 20 1 0 1 0 /* TxD3 */
180 1 2 1 0 1 0 /* TxD4 */ 182 1 2 1 0 1 0 /* TxD4 */
181 1 3 1 0 2 0 /* TxD5 */ 183 1 3 1 0 2 0 /* TxD5 */
182 1 5 1 0 3 0 /* TxD6 */ 184 1 5 1 0 3 0 /* TxD6 */
183 1 8 1 0 3 0 /* TxD7 */ 185 1 8 1 0 3 0 /* TxD7 */
184 0 17 2 0 1 0 /* RxD0 */ 186 0 23 2 0 1 0 /* RxD0 */
185 0 18 2 0 1 0 /* RxD1 */ 187 0 24 2 0 1 0 /* RxD1 */
186 0 19 2 0 1 0 /* RxD2 */ 188 0 25 2 0 1 0 /* RxD2 */
187 0 1a 2 0 1 0 /* RxD3 */ 189 0 26 2 0 1 0 /* RxD3 */
188 0 1b 2 0 1 0 /* RxD4 */ 190 0 27 2 0 1 0 /* RxD4 */
189 1 c 2 0 2 0 /* RxD5 */ 191 1 12 2 0 2 0 /* RxD5 */
190 1 d 2 0 3 0 /* RxD6 */ 192 1 13 2 0 3 0 /* RxD6 */
191 1 b 2 0 2 0 /* RxD7 */ 193 1 11 2 0 2 0 /* RxD7 */
192 0 15 1 0 1 0 /* TX_EN */ 194 0 21 1 0 1 0 /* TX_EN */
193 0 16 1 0 1 0 /* TX_ER */ 195 0 22 1 0 1 0 /* TX_ER */
194 0 1d 2 0 1 0 /* RX_DV */ 196 0 29 2 0 1 0 /* RX_DV */
195 0 1e 2 0 1 0 /* RX_ER */ 197 0 30 2 0 1 0 /* RX_ER */
196 0 1f 2 0 1 0 /* RX_CLK */ 198 0 31 2 0 1 0 /* RX_CLK */
197 2 2 1 0 2 0 /* GTX_CLK - CLK10 */ 199 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
198 2 3 2 0 1 0 /* GTX125 - CLK4 */ 200 2 3 2 0 1 0 /* GTX125 - CLK4 */
199 0 1 3 0 2 0 /* MDIO */ 201 0 1 3 0 2 0 /* MDIO */
@@ -208,47 +210,47 @@
208 #size-cells = <1>; 210 #size-cells = <1>;
209 device_type = "qe"; 211 device_type = "qe";
210 compatible = "fsl,qe"; 212 compatible = "fsl,qe";
211 ranges = <0 e0100000 00100000>; 213 ranges = <0x0 0xe0100000 0x00100000>;
212 reg = <e0100000 480>; 214 reg = <0xe0100000 0x480>;
213 brg-frequency = <0>; 215 brg-frequency = <0>;
214 bus-frequency = <179A7B00>; 216 bus-frequency = <396000000>;
215 217
216 muram@10000 { 218 muram@10000 {
217 #address-cells = <1>; 219 #address-cells = <1>;
218 #size-cells = <1>; 220 #size-cells = <1>;
219 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 221 compatible = "fsl,qe-muram", "fsl,cpm-muram";
220 ranges = <0 00010000 0000c000>; 222 ranges = <0x0 0x00010000 0x0000c000>;
221 223
222 data-only@0 { 224 data-only@0 {
223 compatible = "fsl,qe-muram-data", 225 compatible = "fsl,qe-muram-data",
224 "fsl,cpm-muram-data"; 226 "fsl,cpm-muram-data";
225 reg = <0 c000>; 227 reg = <0x0 0xc000>;
226 }; 228 };
227 }; 229 };
228 230
229 spi@4c0 { 231 spi@4c0 {
230 cell-index = <0>; 232 cell-index = <0>;
231 compatible = "fsl,spi"; 233 compatible = "fsl,spi";
232 reg = <4c0 40>; 234 reg = <0x4c0 0x40>;
233 interrupts = <2>; 235 interrupts = <2>;
234 interrupt-parent = < &qeic >; 236 interrupt-parent = <&qeic>;
235 mode = "cpu"; 237 mode = "cpu";
236 }; 238 };
237 239
238 spi@500 { 240 spi@500 {
239 cell-index = <1>; 241 cell-index = <1>;
240 compatible = "fsl,spi"; 242 compatible = "fsl,spi";
241 reg = <500 40>; 243 reg = <0x500 0x40>;
242 interrupts = <1>; 244 interrupts = <1>;
243 interrupt-parent = < &qeic >; 245 interrupt-parent = <&qeic>;
244 mode = "cpu"; 246 mode = "cpu";
245 }; 247 };
246 248
247 usb@6c0 { 249 usb@6c0 {
248 compatible = "qe_udc"; 250 compatible = "qe_udc";
249 reg = <6c0 40 8B00 100>; 251 reg = <0x6c0 0x40 0x8b00 0x100>;
250 interrupts = <b>; 252 interrupts = <11>;
251 interrupt-parent = < &qeic >; 253 interrupt-parent = <&qeic>;
252 mode = "slave"; 254 mode = "slave";
253 }; 255 };
254 256
@@ -258,15 +260,15 @@
258 model = "UCC"; 260 model = "UCC";
259 cell-index = <1>; 261 cell-index = <1>;
260 device-id = <1>; 262 device-id = <1>;
261 reg = <2000 200>; 263 reg = <0x2000 0x200>;
262 interrupts = <20>; 264 interrupts = <32>;
263 interrupt-parent = < &qeic >; 265 interrupt-parent = <&qeic>;
264 local-mac-address = [ 00 00 00 00 00 00 ]; 266 local-mac-address = [ 00 00 00 00 00 00 ];
265 rx-clock-name = "none"; 267 rx-clock-name = "none";
266 tx-clock-name = "clk9"; 268 tx-clock-name = "clk9";
267 phy-handle = < &phy0 >; 269 phy-handle = <&phy0>;
268 phy-connection-type = "rgmii-id"; 270 phy-connection-type = "rgmii-id";
269 pio-handle = < &pio1 >; 271 pio-handle = <&pio1>;
270 }; 272 };
271 273
272 enet1: ucc@3000 { 274 enet1: ucc@3000 {
@@ -275,33 +277,33 @@
275 model = "UCC"; 277 model = "UCC";
276 cell-index = <2>; 278 cell-index = <2>;
277 device-id = <2>; 279 device-id = <2>;
278 reg = <3000 200>; 280 reg = <0x3000 0x200>;
279 interrupts = <21>; 281 interrupts = <33>;
280 interrupt-parent = < &qeic >; 282 interrupt-parent = <&qeic>;
281 local-mac-address = [ 00 00 00 00 00 00 ]; 283 local-mac-address = [ 00 00 00 00 00 00 ];
282 rx-clock-name = "none"; 284 rx-clock-name = "none";
283 tx-clock-name = "clk4"; 285 tx-clock-name = "clk4";
284 phy-handle = < &phy1 >; 286 phy-handle = <&phy1>;
285 phy-connection-type = "rgmii-id"; 287 phy-connection-type = "rgmii-id";
286 pio-handle = < &pio2 >; 288 pio-handle = <&pio2>;
287 }; 289 };
288 290
289 mdio@2120 { 291 mdio@2120 {
290 #address-cells = <1>; 292 #address-cells = <1>;
291 #size-cells = <0>; 293 #size-cells = <0>;
292 reg = <2120 18>; 294 reg = <0x2120 0x18>;
293 compatible = "fsl,ucc-mdio"; 295 compatible = "fsl,ucc-mdio";
294 296
295 phy0: ethernet-phy@00 { 297 phy0: ethernet-phy@00 {
296 interrupt-parent = < &ipic >; 298 interrupt-parent = <&ipic>;
297 interrupts = <11 8>; 299 interrupts = <17 0x8>;
298 reg = <0>; 300 reg = <0x0>;
299 device_type = "ethernet-phy"; 301 device_type = "ethernet-phy";
300 }; 302 };
301 phy1: ethernet-phy@01 { 303 phy1: ethernet-phy@01 {
302 interrupt-parent = < &ipic >; 304 interrupt-parent = <&ipic>;
303 interrupts = <12 8>; 305 interrupts = <18 0x8>;
304 reg = <1>; 306 reg = <0x1>;
305 device_type = "ethernet-phy"; 307 device_type = "ethernet-phy";
306 }; 308 };
307 }; 309 };
@@ -311,70 +313,70 @@
311 compatible = "fsl,qe-ic"; 313 compatible = "fsl,qe-ic";
312 #address-cells = <0>; 314 #address-cells = <0>;
313 #interrupt-cells = <1>; 315 #interrupt-cells = <1>;
314 reg = <80 80>; 316 reg = <0x80 0x80>;
315 big-endian; 317 big-endian;
316 interrupts = <20 8 21 8>; //high:32 low:33 318 interrupts = <32 0x8 33 0x8>; // high:32 low:33
317 interrupt-parent = < &ipic >; 319 interrupt-parent = <&ipic>;
318 }; 320 };
319 }; 321 };
320 322
321 pci0: pci@e0008500 { 323 pci0: pci@e0008500 {
322 cell-index = <1>; 324 cell-index = <1>;
323 interrupt-map-mask = <f800 0 0 7>; 325 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
324 interrupt-map = < 326 interrupt-map = <
325 327
326 /* IDSEL 0x11 AD17 */ 328 /* IDSEL 0x11 AD17 */
327 8800 0 0 1 &ipic 14 8 329 0x8800 0x0 0x0 0x1 &ipic 20 0x8
328 8800 0 0 2 &ipic 15 8 330 0x8800 0x0 0x0 0x2 &ipic 21 0x8
329 8800 0 0 3 &ipic 16 8 331 0x8800 0x0 0x0 0x3 &ipic 22 0x8
330 8800 0 0 4 &ipic 17 8 332 0x8800 0x0 0x0 0x4 &ipic 23 0x8
331 333
332 /* IDSEL 0x12 AD18 */ 334 /* IDSEL 0x12 AD18 */
333 9000 0 0 1 &ipic 16 8 335 0x9000 0x0 0x0 0x1 &ipic 22 0x8
334 9000 0 0 2 &ipic 17 8 336 0x9000 0x0 0x0 0x2 &ipic 23 0x8
335 9000 0 0 3 &ipic 14 8 337 0x9000 0x0 0x0 0x3 &ipic 20 0x8
336 9000 0 0 4 &ipic 15 8 338 0x9000 0x0 0x0 0x4 &ipic 21 0x8
337 339
338 /* IDSEL 0x13 AD19 */ 340 /* IDSEL 0x13 AD19 */
339 9800 0 0 1 &ipic 17 8 341 0x9800 0x0 0x0 0x1 &ipic 23 0x8
340 9800 0 0 2 &ipic 14 8 342 0x9800 0x0 0x0 0x2 &ipic 20 0x8
341 9800 0 0 3 &ipic 15 8 343 0x9800 0x0 0x0 0x3 &ipic 21 0x8
342 9800 0 0 4 &ipic 16 8 344 0x9800 0x0 0x0 0x4 &ipic 22 0x8
343 345
344 /* IDSEL 0x15 AD21*/ 346 /* IDSEL 0x15 AD21*/
345 a800 0 0 1 &ipic 14 8 347 0xa800 0x0 0x0 0x1 &ipic 20 0x8
346 a800 0 0 2 &ipic 15 8 348 0xa800 0x0 0x0 0x2 &ipic 21 0x8
347 a800 0 0 3 &ipic 16 8 349 0xa800 0x0 0x0 0x3 &ipic 22 0x8
348 a800 0 0 4 &ipic 17 8 350 0xa800 0x0 0x0 0x4 &ipic 23 0x8
349 351
350 /* IDSEL 0x16 AD22*/ 352 /* IDSEL 0x16 AD22*/
351 b000 0 0 1 &ipic 17 8 353 0xb000 0x0 0x0 0x1 &ipic 23 0x8
352 b000 0 0 2 &ipic 14 8 354 0xb000 0x0 0x0 0x2 &ipic 20 0x8
353 b000 0 0 3 &ipic 15 8 355 0xb000 0x0 0x0 0x3 &ipic 21 0x8
354 b000 0 0 4 &ipic 16 8 356 0xb000 0x0 0x0 0x4 &ipic 22 0x8
355 357
356 /* IDSEL 0x17 AD23*/ 358 /* IDSEL 0x17 AD23*/
357 b800 0 0 1 &ipic 16 8 359 0xb800 0x0 0x0 0x1 &ipic 22 0x8
358 b800 0 0 2 &ipic 17 8 360 0xb800 0x0 0x0 0x2 &ipic 23 0x8
359 b800 0 0 3 &ipic 14 8 361 0xb800 0x0 0x0 0x3 &ipic 20 0x8
360 b800 0 0 4 &ipic 15 8 362 0xb800 0x0 0x0 0x4 &ipic 21 0x8
361 363
362 /* IDSEL 0x18 AD24*/ 364 /* IDSEL 0x18 AD24*/
363 c000 0 0 1 &ipic 15 8 365 0xc000 0x0 0x0 0x1 &ipic 21 0x8
364 c000 0 0 2 &ipic 16 8 366 0xc000 0x0 0x0 0x2 &ipic 22 0x8
365 c000 0 0 3 &ipic 17 8 367 0xc000 0x0 0x0 0x3 &ipic 23 0x8
366 c000 0 0 4 &ipic 14 8>; 368 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
367 interrupt-parent = < &ipic >; 369 interrupt-parent = <&ipic>;
368 interrupts = <42 8>; 370 interrupts = <66 0x8>;
369 bus-range = <0 0>; 371 bus-range = <0 0>;
370 ranges = <02000000 0 a0000000 a0000000 0 10000000 372 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
371 42000000 0 80000000 80000000 0 10000000 373 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
372 01000000 0 00000000 e2000000 0 00100000>; 374 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
373 clock-frequency = <3f940aa>; 375 clock-frequency = <66666666>;
374 #interrupt-cells = <1>; 376 #interrupt-cells = <1>;
375 #size-cells = <2>; 377 #size-cells = <2>;
376 #address-cells = <3>; 378 #address-cells = <3>;
377 reg = <e0008500 100>; 379 reg = <0xe0008500 0x100>;
378 compatible = "fsl,mpc8349-pci"; 380 compatible = "fsl,mpc8349-pci";
379 device_type = "pci"; 381 device_type = "pci";
380 }; 382 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 05:36:20 -0500