diff options
author | Diana CRACIUN <Diana.Craciun@freescale.com> | 2012-02-01 10:50:34 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2012-03-16 17:15:19 -0400 |
commit | da3b6c0534c76bc08ce5524342586138687fd106 (patch) | |
tree | e67ea548f1389cf8fca6aa7415451fef30645888 /arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi | |
parent | a2279e3fe484e89f744e03421377d5c0fca9f77d (diff) |
powerpc/fsl: Added aliased MSIIR register address to MSI node in dts
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg = <0x41600 0x200 0x44140 4>;
The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi')
-rw-r--r-- | arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi index b9bada6a87dc..08f42271f86a 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi | |||
@@ -53,7 +53,7 @@ timer@41100 { | |||
53 | 53 | ||
54 | msi0: msi@41600 { | 54 | msi0: msi@41600 { |
55 | compatible = "fsl,mpic-msi"; | 55 | compatible = "fsl,mpic-msi"; |
56 | reg = <0x41600 0x200>; | 56 | reg = <0x41600 0x200 0x44140 4>; |
57 | msi-available-ranges = <0 0x100>; | 57 | msi-available-ranges = <0 0x100>; |
58 | interrupts = < | 58 | interrupts = < |
59 | 0xe0 0 0 0 | 59 | 0xe0 0 0 0 |
@@ -68,7 +68,7 @@ msi0: msi@41600 { | |||
68 | 68 | ||
69 | msi1: msi@41800 { | 69 | msi1: msi@41800 { |
70 | compatible = "fsl,mpic-msi"; | 70 | compatible = "fsl,mpic-msi"; |
71 | reg = <0x41800 0x200>; | 71 | reg = <0x41800 0x200 0x45140 4>; |
72 | msi-available-ranges = <0 0x100>; | 72 | msi-available-ranges = <0 0x100>; |
73 | interrupts = < | 73 | interrupts = < |
74 | 0xe8 0 0 0 | 74 | 0xe8 0 0 0 |
@@ -83,7 +83,7 @@ msi1: msi@41800 { | |||
83 | 83 | ||
84 | msi2: msi@41a00 { | 84 | msi2: msi@41a00 { |
85 | compatible = "fsl,mpic-msi"; | 85 | compatible = "fsl,mpic-msi"; |
86 | reg = <0x41a00 0x200>; | 86 | reg = <0x41a00 0x200 0x46140 4>; |
87 | msi-available-ranges = <0 0x100>; | 87 | msi-available-ranges = <0 0x100>; |
88 | interrupts = < | 88 | interrupts = < |
89 | 0xf0 0 0 0 | 89 | 0xf0 0 0 0 |