diff options
author | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-08-20 08:28:30 -0400 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-08-20 08:28:30 -0400 |
commit | e90f3b74d884d0f2826e06dbab4f615ca346eaa4 (patch) | |
tree | 19b10d012a78ec644c7ce65be5df1c9d80f96ddc /arch/powerpc/boot/4xx.c | |
parent | 869680c16fb028ac4ad9a449283e0514789c654a (diff) |
[POWERPC] 4xx bootwrapper reworks
Make the fixup_memsize function common for all of 4xx as several chips share
the same SDRAM controller. Also add functions to reset 40x chips and quiesce
the ethernet.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/4xx.c')
-rw-r--r-- | arch/powerpc/boot/4xx.c | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 9f64e840bef6..59026e4585dc 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c | |||
@@ -21,8 +21,8 @@ | |||
21 | #include "reg.h" | 21 | #include "reg.h" |
22 | #include "dcr.h" | 22 | #include "dcr.h" |
23 | 23 | ||
24 | /* Read the 44x memory controller to get size of system memory. */ | 24 | /* Read the 4xx SDRAM controller to get size of system memory. */ |
25 | void ibm44x_fixup_memsize(void) | 25 | void ibm4xx_fixup_memsize(void) |
26 | { | 26 | { |
27 | int i; | 27 | int i; |
28 | unsigned long memsize, bank_config; | 28 | unsigned long memsize, bank_config; |
@@ -39,8 +39,9 @@ void ibm44x_fixup_memsize(void) | |||
39 | dt_fixup_memory(0, memsize); | 39 | dt_fixup_memory(0, memsize); |
40 | } | 40 | } |
41 | 41 | ||
42 | #define SPRN_DBCR0 0x134 | 42 | #define SPRN_DBCR0_40X 0x3F2 |
43 | #define DBCR0_RST_SYSTEM 0x30000000 | 43 | #define SPRN_DBCR0_44X 0x134 |
44 | #define DBCR0_RST_SYSTEM 0x30000000 | ||
44 | 45 | ||
45 | void ibm44x_dbcr_reset(void) | 46 | void ibm44x_dbcr_reset(void) |
46 | { | 47 | { |
@@ -50,11 +51,35 @@ void ibm44x_dbcr_reset(void) | |||
50 | "mfspr %0,%1\n" | 51 | "mfspr %0,%1\n" |
51 | "oris %0,%0,%2@h\n" | 52 | "oris %0,%0,%2@h\n" |
52 | "mtspr %1,%0" | 53 | "mtspr %1,%0" |
53 | : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM) | 54 | : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM) |
54 | ); | 55 | ); |
55 | 56 | ||
56 | } | 57 | } |
57 | 58 | ||
59 | void ibm40x_dbcr_reset(void) | ||
60 | { | ||
61 | unsigned long tmp; | ||
62 | |||
63 | asm volatile ( | ||
64 | "mfspr %0,%1\n" | ||
65 | "oris %0,%0,%2@h\n" | ||
66 | "mtspr %1,%0" | ||
67 | : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM) | ||
68 | ); | ||
69 | } | ||
70 | |||
71 | #define EMAC_RESET 0x20000000 | ||
72 | void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) | ||
73 | { | ||
74 | /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */ | ||
75 | if (emac0) | ||
76 | *emac0 = EMAC_RESET; | ||
77 | if (emac1) | ||
78 | *emac1 = EMAC_RESET; | ||
79 | |||
80 | mtdcr(DCRN_MAL0_CFG, MAL_RESET); | ||
81 | } | ||
82 | |||
58 | /* Read 4xx EBC bus bridge registers to get mappings of the peripheral | 83 | /* Read 4xx EBC bus bridge registers to get mappings of the peripheral |
59 | * banks into the OPB address space */ | 84 | * banks into the OPB address space */ |
60 | void ibm4xx_fixup_ebc_ranges(const char *ebc) | 85 | void ibm4xx_fixup_ebc_ranges(const char *ebc) |