parisc: disable preemption while flushing D- or I-caches through TMPALIAS region

It is necessary to disable preemption during cache flushes done through the
TMPALIAS region to ensure that the TLB setup is not clobbered by another flush.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 1c61b8245650..4b12890642eb 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -267,9 +267,11 @@ static inline void
 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
                    unsigned long physaddr)
 {
+        preempt_disable();
         flush_dcache_page_asm(physaddr, vmaddr);
         if (vma->vm_flags & VM_EXEC)
                 flush_icache_page_asm(physaddr, vmaddr);
+        preempt_enable();
 }
 
 void flush_dcache_page(struct page *page)