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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 17:06:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 17:06:36 -0400
commit809b4e00baf006a990a73329ba381d536c6fa277 (patch)
treee949e0efd019d6f932537aba762792b07a84351c /arch/mn10300/mm/cache.c
parenta0a55682b83fd5f012afadcf415b030d7424ae68 (diff)
parent79a94c3538bda6869d7bb150b5e02dd3a72314dd (diff)
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/mn10300/mm/cache.c')
-rw-r--r--arch/mn10300/mm/cache.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/mn10300/mm/cache.c b/arch/mn10300/mm/cache.c
index 1b76719ec1c3..9261217e8d2c 100644
--- a/arch/mn10300/mm/cache.c
+++ b/arch/mn10300/mm/cache.c
@@ -54,13 +54,30 @@ EXPORT_SYMBOL(flush_icache_page);
54void flush_icache_range(unsigned long start, unsigned long end) 54void flush_icache_range(unsigned long start, unsigned long end)
55{ 55{
56#ifdef CONFIG_MN10300_CACHE_WBACK 56#ifdef CONFIG_MN10300_CACHE_WBACK
57 unsigned long addr, size, off; 57 unsigned long addr, size, base, off;
58 struct page *page; 58 struct page *page;
59 pgd_t *pgd; 59 pgd_t *pgd;
60 pud_t *pud; 60 pud_t *pud;
61 pmd_t *pmd; 61 pmd_t *pmd;
62 pte_t *ppte, pte; 62 pte_t *ppte, pte;
63 63
64 if (end > 0x80000000UL) {
65 /* addresses above 0xa0000000 do not go through the cache */
66 if (end > 0xa0000000UL) {
67 end = 0xa0000000UL;
68 if (start >= end)
69 return;
70 }
71
72 /* kernel addresses between 0x80000000 and 0x9fffffff do not
73 * require page tables, so we just map such addresses directly */
74 base = (start >= 0x80000000UL) ? start : 0x80000000UL;
75 mn10300_dcache_flush_range(base, end);
76 if (base == start)
77 goto invalidate;
78 end = base;
79 }
80
64 for (; start < end; start += size) { 81 for (; start < end; start += size) {
65 /* work out how much of the page to flush */ 82 /* work out how much of the page to flush */
66 off = start & (PAGE_SIZE - 1); 83 off = start & (PAGE_SIZE - 1);
@@ -104,6 +121,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
104 } 121 }
105#endif 122#endif
106 123
124invalidate:
107 mn10300_icache_inv(); 125 mn10300_icache_inv();
108} 126}
109EXPORT_SYMBOL(flush_icache_range); 127EXPORT_SYMBOL(flush_icache_range);