MIPS: BMIPS: Add special cache handling in c-r4k.c

BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.

BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$.  But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 43 insertions, 0 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fbcd8674ff1d..dd261df005c2 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -917,6 +917,18 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
         }
 }
 
+static void b5k_instruction_hazard(void)
+{
+        __sync();
+        __sync();
+        __asm__ __volatile__(
+        "       nop; nop; nop; nop; nop; nop; nop; nop\n"
+        "       nop; nop; nop; nop; nop; nop; nop; nop\n"
+        "       nop; nop; nop; nop; nop; nop; nop; nop\n"
+        "       nop; nop; nop; nop; nop; nop; nop; nop\n"
+        : : : "memory");
+}
+
 static char *way_string[] = { NULL, "direct mapped", "2-way",
         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 };
@@ -1683,6 +1695,37 @@ void r4k_cache_init(void)
 
         coherency_setup();
         board_cache_error_setup = r4k_cache_error_setup;
+
+        /*
+         * Per-CPU overrides
+         */
+        switch (current_cpu_type()) {
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                /* No IPI is needed because all CPUs share the same D$ */
+                flush_data_cache_page = r4k_blast_dcache_page;
+                break;
+        case CPU_BMIPS5000:
+                /* We lose our superpowers if L2 is disabled */
+                if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
+                        break;
+
+                /* I$ fills from D$ just by emptying the write buffers */
+                flush_cache_page = (void *)b5k_instruction_hazard;
+                flush_cache_range = (void *)b5k_instruction_hazard;
+                flush_cache_sigtramp = (void *)b5k_instruction_hazard;
+                local_flush_data_cache_page = (void *)b5k_instruction_hazard;
+                flush_data_cache_page = (void *)b5k_instruction_hazard;
+                flush_icache_range = (void *)b5k_instruction_hazard;
+                local_flush_icache_range = (void *)b5k_instruction_hazard;
+
+                /* Cache aliases are handled in hardware; allow HIGHMEM */
+                current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
+
+                /* Optimization: an L2 flush implicitly flushes the L1 */
+                current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
+                break;
+        }
 }
 
 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,