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authorManuel Lauss <manuel.lauss@googlemail.com>2009-06-06 08:09:56 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-06-17 06:06:28 -0400
commitbb706b28bbd647c2fd7f22d6bf03a18b9552be05 (patch)
treed3665800f631759b923de1a0083bd2483babee4b /arch/mips
parent51e02b02e650183ff1277bcbad6a01d6ea0e9edb (diff)
MIPS: Alchemy: MTX-1: Use linux gpio api.
Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 8ed1ae12bc55..cc32c69a74ad 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -28,6 +28,7 @@
28 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */ 29 */
30 30
31#include <linux/gpio.h>
31#include <linux/init.h> 32#include <linux/init.h>
32 33
33#include <asm/mach-au1x00/au1000.h> 34#include <asm/mach-au1x00/au1000.h>
@@ -55,10 +56,11 @@ void __init board_setup(void)
55 } 56 }
56#endif 57#endif
57 58
59 alchemy_gpio2_enable();
60
58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 61#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
59 /* Enable USB power switch */ 62 /* Enable USB power switch */
60 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); 63 alchemy_gpio_direction_output(204, 0);
61 au_writel(0x100000, GPIO2_OUTPUT);
62#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 64#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
63 65
64#ifdef CONFIG_PCI 66#ifdef CONFIG_PCI
@@ -74,14 +76,14 @@ void __init board_setup(void)
74 76
75 /* Initialize GPIO */ 77 /* Initialize GPIO */
76 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); 78 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
77 au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */ 79 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
78 au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */ 80 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
79 au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ 81 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
80 au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */ 82 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
81 83
82 /* Enable LED and set it to green */ 84 /* Enable LED and set it to green */
83 au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR); 85 alchemy_gpio_direction_output(211, 1); /* green on */
84 au_writel(0x18000800, GPIO2_OUTPUT); 86 alchemy_gpio_direction_output(212, 0); /* red off */
85 87
86 board_pci_idsel = mtx1_pci_idsel; 88 board_pci_idsel = mtx1_pci_idsel;
87 89
@@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
101 103
102 if (assert && devsel != 0) 104 if (assert && devsel != 0)
103 /* Suppress signal to Cardbus */ 105 /* Suppress signal to Cardbus */
104 au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ 106 gpio_set_value(1, 0); /* set EXT_IO3 OFF */
105 else 107 else
106 au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ 108 gpio_set_value(1, 1); /* set EXT_IO3 ON */
109
107 au_sync_udelay(1); 110 au_sync_udelay(1);
108 return 1; 111 return 1;
109} 112}
110