diff options
author | Maciej W. Rozycki <macro@codesourcery.com> | 2013-05-23 10:31:23 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-05-23 11:47:51 -0400 |
commit | a9a6e7a09598013ff97e34ebd84c39d1f51f261a (patch) | |
tree | 24e4328fd8d8d0f8cab547e57d41ec3adcd48ee7 /arch/mips | |
parent | 8f657933a3c2086d4731350c98f91a990783c0d3 (diff) |
MIPS: Trap exception handling fixes
2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in
the standard MIPS mode. Additionally the microMIPS-mode trap code mask is
wrong, as it's a 4-bit field. Here's a fix.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5309/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/kernel/traps.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e3be67012d78..a75ae40184aa 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -897,22 +897,24 @@ out_sigsegv: | |||
897 | 897 | ||
898 | asmlinkage void do_tr(struct pt_regs *regs) | 898 | asmlinkage void do_tr(struct pt_regs *regs) |
899 | { | 899 | { |
900 | unsigned int opcode, tcode = 0; | 900 | u32 opcode, tcode = 0; |
901 | u16 instr[2]; | 901 | u16 instr[2]; |
902 | unsigned long epc = exception_epc(regs); | 902 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
903 | 903 | ||
904 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) || | 904 | if (get_isa16_mode(regs->cp0_epc)) { |
905 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))) | 905 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || |
906 | __get_user(instr[1], (u16 __user *)(epc + 2))) | ||
906 | goto out_sigsegv; | 907 | goto out_sigsegv; |
907 | opcode = (instr[0] << 16) | instr[1]; | 908 | opcode = (instr[0] << 16) | instr[1]; |
908 | 909 | /* Immediate versions don't provide a code. */ | |
909 | /* Immediate versions don't provide a code. */ | 910 | if (!(opcode & OPCODE)) |
910 | if (!(opcode & OPCODE)) { | 911 | tcode = (opcode >> 12) & ((1 << 4) - 1); |
911 | if (get_isa16_mode(regs->cp0_epc)) | 912 | } else { |
912 | /* microMIPS */ | 913 | if (__get_user(opcode, (u32 __user *)epc)) |
913 | tcode = (opcode >> 12) & 0x1f; | 914 | goto out_sigsegv; |
914 | else | 915 | /* Immediate versions don't provide a code. */ |
915 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | 916 | if (!(opcode & OPCODE)) |
917 | tcode = (opcode >> 6) & ((1 << 10) - 1); | ||
916 | } | 918 | } |
917 | 919 | ||
918 | do_trap_or_bp(regs, tcode, "Trap"); | 920 | do_trap_or_bp(regs, tcode, "Trap"); |