MIPS: Add EIC support for GIC.

Add support to use an external interrupt controller with the GIC.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

2 files changed, 95 insertions, 8 deletions

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9599d..75323925e537 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,7 @@
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
+#include <asm/gic.h>
 
 /*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
@@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev)
  */
 static int c0_compare_int_pending(void)
 {
+#ifdef CONFIG_IRQ_GIC
+        if (cpu_has_veic)
+                return gic_get_timer_pending();
+#endif
         return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
 }
 
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 770c07552518..e9a46d0205a2 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -13,6 +13,8 @@
 
 #include <asm/io.h>
 #include <asm/gic.h>
+#include <asm/setup.h>
+#include <asm/traps.h>
 #include <asm/gcmpregs.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
@@ -21,22 +23,71 @@ unsigned long _gic_base;
 unsigned int gic_irq_base;
 unsigned int gic_irq_flags[GIC_NUM_INTRS];
 
+/* The index into this array is the vector # of the interrupt. */
+struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
+
 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
 
+unsigned int gic_get_timer_pending(void)
+{
+        unsigned int vpe_pending;
+
+        GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
+        GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
+        return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
+}
+
+void gic_bind_eic_interrupt(int irq, int set)
+{
+        /* Convert irq vector # to hw int # */
+        irq -= GIC_PIN_TO_VEC_OFFSET;
+
+        /* Set irq to use shadow set */
+        GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
+}
+
 void gic_send_ipi(unsigned int intr)
 {
         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 }
 
+static void gic_eic_irq_dispatch(void)
+{
+        unsigned int cause = read_c0_cause();
+        int irq;
+
+        irq = (cause & ST0_IM) >> STATUSB_IP2;
+        if (irq == 0)
+                irq = -1;
+
+        if (irq >= 0)
+                do_IRQ(gic_irq_base + irq);
+        else
+                spurious_interrupt();
+}
+
 static void __init vpe_local_setup(unsigned int numvpes)
 {
-        unsigned long timer_interrupt = GIC_INT_TMR;
-        unsigned long perf_interrupt = GIC_INT_PERFCTR;
+        unsigned long timer_intr = GIC_INT_TMR;
+        unsigned long perf_intr = GIC_INT_PERFCTR;
         unsigned int vpe_ctl;
         int i;
 
+        if (cpu_has_veic) {
+                /*
+                 * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+                /*
+                 * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+        }
+
         /*
          * Setup the default performance counter timer interrupts
          * for all VPEs
@@ -48,11 +99,20 @@ static void __init vpe_local_setup(unsigned int numvpes)
                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
-                                 GIC_MAP_TO_PIN_MSK | timer_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | timer_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
+                }
 
                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
-                                 GIC_MAP_TO_PIN_MSK | perf_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | perf_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
+                        gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
+                }
         }
 }
 
@@ -145,6 +205,8 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
         unsigned int pin, unsigned int polarity, unsigned int trigtype,
         unsigned int flags)
 {
+        struct gic_shared_intr_map *map_ptr;
+
         /* Setup Intr to Pin mapping */
         if (pin & GIC_MAP_TO_NMI_MSK) {
                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
@@ -159,6 +221,14 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
                          GIC_MAP_TO_PIN_MSK | pin);
                 /* Setup Intr to CPU mapping */
                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
+                if (cpu_has_veic) {
+                        set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
+                        if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
+                                BUG();
+                        map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
+                }
         }
 
         /* Setup Intr Polarity */
@@ -169,11 +239,10 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 
         /* Init Intr Masks */
         GIC_CLR_INTR_MASK(intr);
-
         /* Initialise per-cpu Interrupt software masks */
         if (flags & GIC_FLAG_IPI)
                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
-        if (flags & GIC_FLAG_TRANSPARENT)
+        if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
                 GIC_SET_INTR_MASK(intr);
         if (trigtype == GIC_TRIG_EDGE)
                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
@@ -183,16 +252,29 @@ static void __init gic_basic_init(int numintrs, int numvpes,
                         struct gic_intr_map *intrmap, int mapsize)
 {
         unsigned int i, cpu;
+        unsigned int pin_offset = 0;
+
+        board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 
         /* Setup defaults */
         for (i = 0; i < numintrs; i++) {
                 GIC_SET_POLARITY(i, GIC_POL_POS);
                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
                 GIC_CLR_INTR_MASK(i);
-                if (i < GIC_NUM_INTRS)
+                if (i < GIC_NUM_INTRS) {
                         gic_irq_flags[i] = 0;
+                        gic_shared_intr_map[i].num_shared_intr = 0;
+                        gic_shared_intr_map[i].local_intr_mask = 0;
+                }
         }
 
+        /*
+         * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
+         * one because the GIC will add one (since 0=no intr).
+         */
+        if (cpu_has_veic)
+                pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+
         /* Setup specifics */
         for (i = 0; i < mapsize; i++) {
                 cpu = intrmap[i].cpunum;
@@ -202,7 +284,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
                         continue;
                 gic_setup_intr(i,
                         intrmap[i].cpunum,
-                        intrmap[i].pin,
+                        intrmap[i].pin + pin_offset,
                         intrmap[i].polarity,
                         intrmap[i].trigtype,
                         intrmap[i].flags);