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authorManuel Lauss <manuel.lauss@gmail.com>2012-12-17 01:14:08 -0500
committerRalf Baechle <ralf@linux-mips.org>2012-12-27 10:27:35 -0500
commit8e0d7372f595c254d83316fba1530164010f7b33 (patch)
tree7174fa3805150483ba7c77658769a3194a74d5b2 /arch/mips
parenta49f0d1ea3ec94fc7cf33a7c36a16343b74bd565 (diff)
MIPS: Alchemy: Make 32kHz and r4k timer coexist peacefully
Now that the r4k timer is registered no matter what, bump the rating of the Alchemy 32kHz timer so that it gets used when it is working, and fall back on the r4k when it isn't. This fixes a timer-related hang on platform with a working 32kHz timer (the better rated c0 timer stops while executing 'wait' leading to (almost) eternal sleep) and an oops on boot on platforms without a working 32kHz timer (due to double registration of the r4k timer). Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/4728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/common/time.c25
1 files changed, 5 insertions, 20 deletions
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index a7193ae13a5d..b67930d19325 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -53,7 +53,7 @@ static struct clocksource au1x_counter1_clocksource = {
53 .read = au1x_counter1_read, 53 .read = au1x_counter1_read,
54 .mask = CLOCKSOURCE_MASK(32), 54 .mask = CLOCKSOURCE_MASK(32),
55 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 55 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
56 .rating = 100, 56 .rating = 1500,
57}; 57};
58 58
59static int au1x_rtcmatch2_set_next_event(unsigned long delta, 59static int au1x_rtcmatch2_set_next_event(unsigned long delta,
@@ -84,7 +84,7 @@ static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
84static struct clock_event_device au1x_rtcmatch2_clockdev = { 84static struct clock_event_device au1x_rtcmatch2_clockdev = {
85 .name = "rtcmatch2", 85 .name = "rtcmatch2",
86 .features = CLOCK_EVT_FEAT_ONESHOT, 86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .rating = 100, 87 .rating = 1500,
88 .set_next_event = au1x_rtcmatch2_set_next_event, 88 .set_next_event = au1x_rtcmatch2_set_next_event,
89 .set_mode = au1x_rtcmatch2_set_mode, 89 .set_mode = au1x_rtcmatch2_set_mode,
90 .cpumask = cpu_all_mask, 90 .cpumask = cpu_all_mask,
@@ -158,20 +158,6 @@ cntr_err:
158 return -1; 158 return -1;
159} 159}
160 160
161static void __init alchemy_setup_c0timer(void)
162{
163 /*
164 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
165 * function is called. Because the Alchemy counters are unusable
166 * the C0 timekeeping code is installed and use of the 'wait'
167 * instruction must be prohibited, which is done most easily by
168 * assigning NULL to cpu_wait.
169 */
170 cpu_wait = NULL;
171 r4k_clockevent_init();
172 init_r4k_clocksource();
173}
174
175static int alchemy_m2inttab[] __initdata = { 161static int alchemy_m2inttab[] __initdata = {
176 AU1000_RTC_MATCH2_INT, 162 AU1000_RTC_MATCH2_INT,
177 AU1500_RTC_MATCH2_INT, 163 AU1500_RTC_MATCH2_INT,
@@ -186,8 +172,7 @@ void __init plat_time_init(void)
186 int t; 172 int t;
187 173
188 t = alchemy_get_cputype(); 174 t = alchemy_get_cputype();
189 if (t == ALCHEMY_CPU_UNKNOWN) 175 if (t == ALCHEMY_CPU_UNKNOWN ||
190 alchemy_setup_c0timer(); 176 alchemy_time_init(alchemy_m2inttab[t]))
191 else if (alchemy_time_init(alchemy_m2inttab[t])) 177 cpu_wait = NULL; /* wait doesn't work with r4k timer */
192 alchemy_setup_c0timer();
193} 178}