MIPS: Emulate the new MIPS R6 BALC instruction

MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

3 files changed, 19 insertions, 1 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 78335414b18a..32063c52f24b 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -33,7 +33,7 @@ enum major_op {
         sdl_op, sdr_op, swr_op, cache_op,
         ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
         lld_op, ldc1_op, ldc2_op, ld_op,
-        sc_op, swc1_op, swc2_op, major_3b_op,
+        sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
         scd_op, sdc1_op, sdc2_op, sd_op
 };
 
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 37c752757346..1f28724d23e5 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -789,6 +789,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                 }
                 regs->cp0_epc += 8;
                 break;
+        case balc6_op:
+                if (!cpu_has_mips_r6) {
+                        ret = -SIGILL;
+                        break;
+                }
+                /* Compact branch: BALC */
+                regs->regs[31] = epc + 4;
+                epc += 4 + (insn.i_format.simmediate << 2);
+                regs->cp0_epc = epc;
+                break;
 #endif
         case cbcond0_op:
         case cbcond1_op:
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 0d8407b51470..d732100c99f0 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -671,6 +671,14 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                         dec_insn.next_pc_inc;
 
                 return 1;
+        case balc6_op:
+                if (!cpu_has_mips_r6)
+                        break;
+                regs->regs[31] = regs->cp0_epc + 4;
+                *contpc = regs->cp0_epc + dec_insn.pc_inc +
+                        dec_insn.next_pc_inc;
+
+                return 1;
 #endif
         case cop0_op:
         case cop1_op: