aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-10 07:03:26 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:06 -0500
commit64cd04d0cffa3b3af0e81aa3112b71f135739e1a (patch)
tree7c66ce3a94ae3cc638a88fd2e55a86bcaf760880 /arch/mips
parent809f36c6f4a0568178c909ff1096ca83eae33f7d (diff)
MIPS: Alchemy: Basic support for the DB1300 board.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2867/ Patchwork: https://patchwork.linux-mips.org/patch/2919/ Patchwork: https://patchwork.linux-mips.org/patch/2928/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/Kconfig8
-rw-r--r--arch/mips/alchemy/Platform7
-rw-r--r--arch/mips/alchemy/devboards/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1300.c787
-rw-r--r--arch/mips/alchemy/devboards/prom.c4
-rw-r--r--arch/mips/boot/compressed/uart-alchemy.c5
-rw-r--r--arch/mips/configs/db1300_defconfig391
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h34
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1300.h40
-rw-r--r--arch/mips/include/asm/mach-db1x00/irq.h23
10 files changed, 1292 insertions, 8 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 766badaef3b0..f9a13beada4a 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -49,6 +49,14 @@ config MIPS_DB1200
49 select SYS_SUPPORTS_LITTLE_ENDIAN 49 select SYS_SUPPORTS_LITTLE_ENDIAN
50 select SYS_HAS_EARLY_PRINTK 50 select SYS_HAS_EARLY_PRINTK
51 51
52config MIPS_DB1300
53 bool "NetLogic DB1300 board"
54 select ALCHEMY_GPIOINT_AU1300
55 select DMA_COHERENT
56 select MIPS_DISABLE_OBSOLETE_IDE
57 select SYS_SUPPORTS_LITTLE_ENDIAN
58 select SYS_HAS_EARLY_PRINTK
59
52config MIPS_DB1500 60config MIPS_DB1500
53 bool "Alchemy DB1500 board" 61 bool "Alchemy DB1500 board"
54 select ALCHEMY_GPIOINT_AU1000 62 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 2920af9c2569..4d13e21eaf83 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -68,6 +68,13 @@ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
68load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 68load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
69 69
70# 70#
71# NetLogic DBAu1300 development platform
72#
73platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/
74cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
75load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000
76
77#
71# 4G-Systems eval board 78# 4G-Systems eval board
72# 79#
73platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/ 80platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 5afaf944868f..2eb75c92a583 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -11,5 +11,6 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/
11obj-$(CONFIG_MIPS_DB1000) += db1x00/ 11obj-$(CONFIG_MIPS_DB1000) += db1x00/
12obj-$(CONFIG_MIPS_DB1100) += db1x00/ 12obj-$(CONFIG_MIPS_DB1100) += db1x00/
13obj-$(CONFIG_MIPS_DB1200) += db1200/ 13obj-$(CONFIG_MIPS_DB1200) += db1200/
14obj-$(CONFIG_MIPS_DB1300) += db1300.o
14obj-$(CONFIG_MIPS_DB1500) += db1x00/ 15obj-$(CONFIG_MIPS_DB1500) += db1x00/
15obj-$(CONFIG_MIPS_DB1550) += db1x00/ 16obj-$(CONFIG_MIPS_DB1550) += db1x00/
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
new file mode 100644
index 000000000000..c41788c59278
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -0,0 +1,787 @@
1/*
2 * DBAu1300 init and platform device setup.
3 *
4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/gpio_keys.h>
10#include <linux/init.h>
11#include <linux/input.h> /* KEY_* codes */
12#include <linux/i2c.h>
13#include <linux/io.h>
14#include <linux/leds.h>
15#include <linux/ata_platform.h>
16#include <linux/mmc/host.h>
17#include <linux/module.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/platform_device.h>
22#include <linux/smsc911x.h>
23
24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1100_mmc.h>
26#include <asm/mach-au1x00/au1xxx_dbdma.h>
27#include <asm/mach-au1x00/au1xxx_psc.h>
28#include <asm/mach-db1x00/db1300.h>
29#include <asm/mach-db1x00/bcsr.h>
30#include <asm/mach-au1x00/prom.h>
31
32#include "platform.h"
33
34static struct i2c_board_info db1300_i2c_devs[] __initdata = {
35 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
36 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
37};
38
39/* multifunction pins to assign to GPIO controller */
40static int db1300_gpio_pins[] __initdata = {
41 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
42 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
43 AU1300_PIN_EXTCLK1,
44 -1, /* terminator */
45};
46
47/* multifunction pins to assign to device functions */
48static int db1300_dev_pins[] __initdata = {
49 /* wake-from-str pins 0-3 */
50 AU1300_PIN_WAKE0,
51 /* external clock sources for PSC0 */
52 AU1300_PIN_EXTCLK0,
53 /* 8bit MMC interface on SD0: 6-9 */
54 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
55 AU1300_PIN_SD0DAT7,
56 /* UART1 pins: 11-18 */
57 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
58 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
59 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
60 /* UART0 pins: 19-24 */
61 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
62 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
63 /* UART2: 25-26 */
64 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
65 /* UART3: 27-28 */
66 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
67 /* LCD controller PWMs, ext pixclock: 30-31 */
68 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
69 /* SD1 interface: 32-37 */
70 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
71 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
72 /* SD2 interface: 38-43 */
73 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
74 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
75 /* PSC0/1 clocks: 44-45 */
76 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
77 /* PSCs: 46-49/50-53/54-57/58-61 */
78 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
79 AU1300_PIN_PSC0D1,
80 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
81 AU1300_PIN_PSC1D1,
82 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
83 AU1300_PIN_PSC2D1,
84 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
85 AU1300_PIN_PSC3D1,
86 /* PCMCIA interface: 62-70 */
87 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
88 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
89 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
90 /* camera interface H/V sync inputs: 71-72 */
91 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
92 /* PSC2/3 clocks: 73-74 */
93 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
94 -1, /* terminator */
95};
96
97static void __init db1300_gpio_config(void)
98{
99 int *i;
100
101 i = &db1300_dev_pins[0];
102 while (*i != -1)
103 au1300_pinfunc_to_dev(*i++);
104
105 i = &db1300_gpio_pins[0];
106 while (*i != -1)
107 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
108
109 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
110}
111
112char *get_system_type(void)
113{
114 return "DB1300";
115}
116
117/**********************************************************************/
118
119static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
120 unsigned int ctrl)
121{
122 struct nand_chip *this = mtd->priv;
123 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
124
125 ioaddr &= 0xffffff00;
126
127 if (ctrl & NAND_CLE) {
128 ioaddr += MEM_STNAND_CMD;
129 } else if (ctrl & NAND_ALE) {
130 ioaddr += MEM_STNAND_ADDR;
131 } else {
132 /* assume we want to r/w real data by default */
133 ioaddr += MEM_STNAND_DATA;
134 }
135 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
136 if (cmd != NAND_CMD_NONE) {
137 __raw_writeb(cmd, this->IO_ADDR_W);
138 wmb();
139 }
140}
141
142static int au1300_nand_device_ready(struct mtd_info *mtd)
143{
144 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
145}
146
147static const char *db1300_part_probes[] = { "cmdlinepart", NULL };
148
149static struct mtd_partition db1300_nand_parts[] = {
150 {
151 .name = "NAND FS 0",
152 .offset = 0,
153 .size = 8 * 1024 * 1024,
154 },
155 {
156 .name = "NAND FS 1",
157 .offset = MTDPART_OFS_APPEND,
158 .size = MTDPART_SIZ_FULL
159 },
160};
161
162struct platform_nand_data db1300_nand_platdata = {
163 .chip = {
164 .nr_chips = 1,
165 .chip_offset = 0,
166 .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
167 .partitions = db1300_nand_parts,
168 .chip_delay = 20,
169 .part_probe_types = db1300_part_probes,
170 },
171 .ctrl = {
172 .dev_ready = au1300_nand_device_ready,
173 .cmd_ctrl = au1300_nand_cmd_ctrl,
174 },
175};
176
177static struct resource db1300_nand_res[] = {
178 [0] = {
179 .start = DB1300_NAND_PHYS_ADDR,
180 .end = DB1300_NAND_PHYS_ADDR + 0xff,
181 .flags = IORESOURCE_MEM,
182 },
183};
184
185static struct platform_device db1300_nand_dev = {
186 .name = "gen_nand",
187 .num_resources = ARRAY_SIZE(db1300_nand_res),
188 .resource = db1300_nand_res,
189 .id = -1,
190 .dev = {
191 .platform_data = &db1300_nand_platdata,
192 }
193};
194
195/**********************************************************************/
196
197static struct resource db1300_eth_res[] = {
198 [0] = {
199 .start = DB1300_ETH_PHYS_ADDR,
200 .end = DB1300_ETH_PHYS_END,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = DB1300_ETH_INT,
205 .end = DB1300_ETH_INT,
206 .flags = IORESOURCE_IRQ,
207 },
208};
209
210static struct smsc911x_platform_config db1300_eth_config = {
211 .phy_interface = PHY_INTERFACE_MODE_MII,
212 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
213 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
214 .flags = SMSC911X_USE_32BIT,
215};
216
217static struct platform_device db1300_eth_dev = {
218 .name = "smsc911x",
219 .id = -1,
220 .num_resources = ARRAY_SIZE(db1300_eth_res),
221 .resource = db1300_eth_res,
222 .dev = {
223 .platform_data = &db1300_eth_config,
224 },
225};
226
227/**********************************************************************/
228
229static struct resource au1300_psc1_res[] = {
230 [0] = {
231 .start = AU1300_PSC1_PHYS_ADDR,
232 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = AU1300_PSC1_INT,
237 .end = AU1300_PSC1_INT,
238 .flags = IORESOURCE_IRQ,
239 },
240 [2] = {
241 .start = AU1300_DSCR_CMD0_PSC1_TX,
242 .end = AU1300_DSCR_CMD0_PSC1_TX,
243 .flags = IORESOURCE_DMA,
244 },
245 [3] = {
246 .start = AU1300_DSCR_CMD0_PSC1_RX,
247 .end = AU1300_DSCR_CMD0_PSC1_RX,
248 .flags = IORESOURCE_DMA,
249 },
250};
251
252static struct platform_device db1300_ac97_dev = {
253 .name = "au1xpsc_ac97",
254 .id = 1, /* PSC ID. match with AC97 codec ID! */
255 .num_resources = ARRAY_SIZE(au1300_psc1_res),
256 .resource = au1300_psc1_res,
257};
258
259/**********************************************************************/
260
261static struct resource au1300_psc2_res[] = {
262 [0] = {
263 .start = AU1300_PSC2_PHYS_ADDR,
264 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
265 .flags = IORESOURCE_MEM,
266 },
267 [1] = {
268 .start = AU1300_PSC2_INT,
269 .end = AU1300_PSC2_INT,
270 .flags = IORESOURCE_IRQ,
271 },
272 [2] = {
273 .start = AU1300_DSCR_CMD0_PSC2_TX,
274 .end = AU1300_DSCR_CMD0_PSC2_TX,
275 .flags = IORESOURCE_DMA,
276 },
277 [3] = {
278 .start = AU1300_DSCR_CMD0_PSC2_RX,
279 .end = AU1300_DSCR_CMD0_PSC2_RX,
280 .flags = IORESOURCE_DMA,
281 },
282};
283
284static struct platform_device db1300_i2s_dev = {
285 .name = "au1xpsc_i2s",
286 .id = 2, /* PSC ID */
287 .num_resources = ARRAY_SIZE(au1300_psc2_res),
288 .resource = au1300_psc2_res,
289};
290
291/**********************************************************************/
292
293static struct resource au1300_psc3_res[] = {
294 [0] = {
295 .start = AU1300_PSC3_PHYS_ADDR,
296 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
297 .flags = IORESOURCE_MEM,
298 },
299 [1] = {
300 .start = AU1300_PSC3_INT,
301 .end = AU1300_PSC3_INT,
302 .flags = IORESOURCE_IRQ,
303 },
304 [2] = {
305 .start = AU1300_DSCR_CMD0_PSC3_TX,
306 .end = AU1300_DSCR_CMD0_PSC3_TX,
307 .flags = IORESOURCE_DMA,
308 },
309 [3] = {
310 .start = AU1300_DSCR_CMD0_PSC3_RX,
311 .end = AU1300_DSCR_CMD0_PSC3_RX,
312 .flags = IORESOURCE_DMA,
313 },
314};
315
316static struct platform_device db1300_i2c_dev = {
317 .name = "au1xpsc_smbus",
318 .id = 0, /* bus number */
319 .num_resources = ARRAY_SIZE(au1300_psc3_res),
320 .resource = au1300_psc3_res,
321};
322
323/**********************************************************************/
324
325/* proper key assignments when facing the LCD panel. For key assignments
326 * according to the schematics swap up with down and left with right.
327 * I chose to use it to emulate the arrow keys of a keyboard.
328 */
329static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
330 {
331 .code = KEY_DOWN,
332 .gpio = AU1300_PIN_LCDPWM0,
333 .type = EV_KEY,
334 .debounce_interval = 1,
335 .active_low = 1,
336 .desc = "5waysw-down",
337 },
338 {
339 .code = KEY_UP,
340 .gpio = AU1300_PIN_PSC2SYNC1,
341 .type = EV_KEY,
342 .debounce_interval = 1,
343 .active_low = 1,
344 .desc = "5waysw-up",
345 },
346 {
347 .code = KEY_RIGHT,
348 .gpio = AU1300_PIN_WAKE3,
349 .type = EV_KEY,
350 .debounce_interval = 1,
351 .active_low = 1,
352 .desc = "5waysw-right",
353 },
354 {
355 .code = KEY_LEFT,
356 .gpio = AU1300_PIN_WAKE2,
357 .type = EV_KEY,
358 .debounce_interval = 1,
359 .active_low = 1,
360 .desc = "5waysw-left",
361 },
362 {
363 .code = KEY_ENTER,
364 .gpio = AU1300_PIN_WAKE1,
365 .type = EV_KEY,
366 .debounce_interval = 1,
367 .active_low = 1,
368 .desc = "5waysw-push",
369 },
370};
371
372static struct gpio_keys_platform_data db1300_5waysw_data = {
373 .buttons = db1300_5waysw_arrowkeys,
374 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
375 .rep = 1,
376 .name = "db1300-5wayswitch",
377};
378
379static struct platform_device db1300_5waysw_dev = {
380 .name = "gpio-keys",
381 .dev = {
382 .platform_data = &db1300_5waysw_data,
383 },
384};
385
386/**********************************************************************/
387
388static struct platform_device db1300_rtc_dev = {
389 .name = "rtc-au1xxx",
390 .id = -1,
391};
392
393/**********************************************************************/
394
395static struct pata_platform_info db1300_ide_info = {
396 .ioport_shift = DB1300_IDE_REG_SHIFT,
397};
398
399#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
400static struct resource db1300_ide_res[] = {
401 [0] = {
402 .start = DB1300_IDE_PHYS_ADDR,
403 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
404 .flags = IORESOURCE_MEM,
405 },
406 [1] = {
407 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
408 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
409 .flags = IORESOURCE_MEM,
410 },
411 [2] = {
412 .start = DB1300_IDE_INT,
413 .end = DB1300_IDE_INT,
414 .flags = IORESOURCE_IRQ,
415 },
416};
417
418static struct platform_device db1300_ide_dev = {
419 .dev = {
420 .platform_data = &db1300_ide_info,
421 },
422 .name = "pata_platform",
423 .resource = db1300_ide_res,
424 .num_resources = ARRAY_SIZE(db1300_ide_res),
425};
426
427/**********************************************************************/
428
429static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
430{
431 void(*mmc_cd)(struct mmc_host *, unsigned long);
432
433 /* disable the one currently screaming. No other way to shut it up */
434 if (irq == DB1300_SD1_INSERT_INT) {
435 disable_irq_nosync(DB1300_SD1_INSERT_INT);
436 enable_irq(DB1300_SD1_EJECT_INT);
437 } else {
438 disable_irq_nosync(DB1300_SD1_EJECT_INT);
439 enable_irq(DB1300_SD1_INSERT_INT);
440 }
441
442 /* link against CONFIG_MMC=m. We can only be called once MMC core has
443 * initialized the controller, so symbol_get() should always succeed.
444 */
445 mmc_cd = symbol_get(mmc_detect_change);
446 mmc_cd(ptr, msecs_to_jiffies(500));
447 symbol_put(mmc_detect_change);
448
449 return IRQ_HANDLED;
450}
451
452static int db1300_mmc_card_readonly(void *mmc_host)
453{
454 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
455 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
456}
457
458static int db1300_mmc_card_inserted(void *mmc_host)
459{
460 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
461}
462
463static int db1300_mmc_cd_setup(void *mmc_host, int en)
464{
465 int ret;
466
467 if (en) {
468 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
469 "sd_insert", mmc_host);
470 if (ret)
471 goto out;
472
473 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
474 "sd_eject", mmc_host);
475 if (ret) {
476 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
477 goto out;
478 }
479
480 if (db1300_mmc_card_inserted(mmc_host))
481 enable_irq(DB1300_SD1_EJECT_INT);
482 else
483 enable_irq(DB1300_SD1_INSERT_INT);
484
485 } else {
486 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
487 free_irq(DB1300_SD1_EJECT_INT, mmc_host);
488 }
489 ret = 0;
490out:
491 return ret;
492}
493
494static void db1300_mmcled_set(struct led_classdev *led,
495 enum led_brightness brightness)
496{
497 if (brightness != LED_OFF)
498 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
499 else
500 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
501}
502
503static struct led_classdev db1300_mmc_led = {
504 .brightness_set = db1300_mmcled_set,
505};
506
507struct au1xmmc_platform_data db1300_sd1_platdata = {
508 .cd_setup = db1300_mmc_cd_setup,
509 .card_inserted = db1300_mmc_card_inserted,
510 .card_readonly = db1300_mmc_card_readonly,
511 .led = &db1300_mmc_led,
512};
513
514static struct resource au1300_sd1_res[] = {
515 [0] = {
516 .start = AU1300_SD1_PHYS_ADDR,
517 .end = AU1300_SD1_PHYS_ADDR,
518 .flags = IORESOURCE_MEM,
519 },
520 [1] = {
521 .start = AU1300_SD1_INT,
522 .end = AU1300_SD1_INT,
523 .flags = IORESOURCE_IRQ,
524 },
525 [2] = {
526 .start = AU1300_DSCR_CMD0_SDMS_TX1,
527 .end = AU1300_DSCR_CMD0_SDMS_TX1,
528 .flags = IORESOURCE_DMA,
529 },
530 [3] = {
531 .start = AU1300_DSCR_CMD0_SDMS_RX1,
532 .end = AU1300_DSCR_CMD0_SDMS_RX1,
533 .flags = IORESOURCE_DMA,
534 },
535};
536
537static struct platform_device db1300_sd1_dev = {
538 .dev = {
539 .platform_data = &db1300_sd1_platdata,
540 },
541 .name = "au1xxx-mmc",
542 .id = 1,
543 .resource = au1300_sd1_res,
544 .num_resources = ARRAY_SIZE(au1300_sd1_res),
545};
546
547/**********************************************************************/
548
549static int db1300_movinand_inserted(void *mmc_host)
550{
551 return 0; /* disable for now, it doesn't work yet */
552}
553
554static int db1300_movinand_readonly(void *mmc_host)
555{
556 return 0;
557}
558
559static void db1300_movinand_led_set(struct led_classdev *led,
560 enum led_brightness brightness)
561{
562 if (brightness != LED_OFF)
563 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
564 else
565 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
566}
567
568static struct led_classdev db1300_movinand_led = {
569 .brightness_set = db1300_movinand_led_set,
570};
571
572struct au1xmmc_platform_data db1300_sd0_platdata = {
573 .card_inserted = db1300_movinand_inserted,
574 .card_readonly = db1300_movinand_readonly,
575 .led = &db1300_movinand_led,
576 .mask_host_caps = MMC_CAP_NEEDS_POLL,
577};
578
579static struct resource au1300_sd0_res[] = {
580 [0] = {
581 .start = AU1100_SD0_PHYS_ADDR,
582 .end = AU1100_SD0_PHYS_ADDR,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 .start = AU1300_SD0_INT,
587 .end = AU1300_SD0_INT,
588 .flags = IORESOURCE_IRQ,
589 },
590 [2] = {
591 .start = AU1300_DSCR_CMD0_SDMS_TX0,
592 .end = AU1300_DSCR_CMD0_SDMS_TX0,
593 .flags = IORESOURCE_DMA,
594 },
595 [3] = {
596 .start = AU1300_DSCR_CMD0_SDMS_RX0,
597 .end = AU1300_DSCR_CMD0_SDMS_RX0,
598 .flags = IORESOURCE_DMA,
599 },
600};
601
602static struct platform_device db1300_sd0_dev = {
603 .dev = {
604 .platform_data = &db1300_sd0_platdata,
605 },
606 .name = "au1xxx-mmc",
607 .id = 0,
608 .resource = au1300_sd0_res,
609 .num_resources = ARRAY_SIZE(au1300_sd0_res),
610};
611
612/**********************************************************************/
613
614static struct platform_device db1300_wm9715_dev = {
615 .name = "wm9712-codec",
616 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
617};
618
619static struct platform_device db1300_ac97dma_dev = {
620 .name = "au1xpsc-pcm",
621 .id = 1, /* PSC ID */
622};
623
624static struct platform_device db1300_i2sdma_dev = {
625 .name = "au1xpsc-pcm",
626 .id = 2, /* PSC ID */
627};
628
629static struct platform_device db1300_sndac97_dev = {
630 .name = "db1300-ac97",
631};
632
633static struct platform_device db1300_sndi2s_dev = {
634 .name = "db1300-i2s",
635};
636
637/**********************************************************************/
638
639static struct resource au1300_lcd_res[] = {
640 [0] = {
641 .start = AU1200_LCD_PHYS_ADDR,
642 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
643 .flags = IORESOURCE_MEM,
644 },
645 [1] = {
646 .start = AU1300_LCD_INT,
647 .end = AU1300_LCD_INT,
648 .flags = IORESOURCE_IRQ,
649 }
650};
651
652static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
653
654static struct platform_device db1300_lcd_dev = {
655 .name = "au1200-lcd",
656 .id = 0,
657 .dev = {
658 .dma_mask = &au1300_lcd_dmamask,
659 .coherent_dma_mask = DMA_BIT_MASK(32),
660 },
661 .num_resources = ARRAY_SIZE(au1300_lcd_res),
662 .resource = au1300_lcd_res,
663};
664
665/**********************************************************************/
666
667static struct platform_device *db1300_dev[] __initdata = {
668 &db1300_eth_dev,
669 &db1300_i2c_dev,
670 &db1300_5waysw_dev,
671 &db1300_rtc_dev,
672 &db1300_nand_dev,
673 &db1300_ide_dev,
674 &db1300_sd0_dev,
675 &db1300_sd1_dev,
676 &db1300_lcd_dev,
677 &db1300_ac97_dev,
678 &db1300_i2s_dev,
679 &db1300_wm9715_dev,
680 &db1300_ac97dma_dev,
681 &db1300_i2sdma_dev,
682 &db1300_sndac97_dev,
683 &db1300_sndi2s_dev,
684};
685
686static int __init db1300_device_init(void)
687{
688 int swapped, cpldirq;
689
690 /* setup CPLD IRQ muxer */
691 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
692 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
693 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
694
695 /* insert/eject IRQs: one always triggers so don't enable them
696 * when doing request_irq() on them. DB1200 has this bug too.
697 */
698 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
699 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
700 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
701 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
702
703 /*
704 * setup board
705 */
706 prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
707
708 i2c_register_board_info(0, db1300_i2c_devs,
709 ARRAY_SIZE(db1300_i2c_devs));
710
711 /* Audio PSC clock is supplied by codecs (PSC1, 2) */
712 __raw_writel(PSC_SEL_CLK_SERCLK,
713 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
714 wmb();
715 __raw_writel(PSC_SEL_CLK_SERCLK,
716 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
717 wmb();
718 /* I2C uses internal 48MHz EXTCLK1 */
719 __raw_writel(PSC_SEL_CLK_INTCLK,
720 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
721 wmb();
722
723 /* enable power to USB ports */
724 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
725
726 /* although it is socket #0, it uses the CPLD bits which previous boards
727 * have used for socket #1.
728 */
729 db1x_register_pcmcia_socket(
730 AU1000_PCMCIA_ATTR_PHYS_ADDR,
731 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
732 AU1000_PCMCIA_MEM_PHYS_ADDR,
733 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
734 AU1000_PCMCIA_IO_PHYS_ADDR,
735 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
736 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
737
738 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
739 db1x_register_norflash(64 << 20, 2, swapped);
740
741 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
742}
743device_initcall(db1300_device_init);
744
745
746void __init board_setup(void)
747{
748 unsigned short whoami;
749
750 db1300_gpio_config();
751 bcsr_init(DB1300_BCSR_PHYS_ADDR,
752 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
753
754 whoami = bcsr_read(BCSR_WHOAMI);
755 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
756 "BoardID %d CPLD Rev %d DaughtercardID %d\n",
757 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
758 BCSR_WHOAMI_DCID(whoami));
759
760 /* enable UARTs, YAMON only enables #2 */
761 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
762 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
763 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
764}
765
766
767/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
768int board_au1200fb_panel(void)
769{
770 return 9; /* DB1300_800x480 */
771}
772
773int board_au1200fb_panel_init(void)
774{
775 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
776 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
777 BCSR_BOARD_LCDBL);
778 return 0;
779}
780
781int board_au1200fb_panel_shutdown(void)
782{
783 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
784 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
785 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
786 return 0;
787}
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index f734833fbdda..3a73f9663b0f 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -61,5 +61,9 @@ void __init prom_init(void)
61 61
62void prom_putchar(unsigned char c) 62void prom_putchar(unsigned char c)
63{ 63{
64#ifdef CONFIG_MIPS_DB1300
65 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
66#else
64 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 67 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
68#endif
65} 69}
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
index eb063e6dead9..3112df8f90db 100644
--- a/arch/mips/boot/compressed/uart-alchemy.c
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -2,6 +2,9 @@
2 2
3void putc(char c) 3void putc(char c)
4{ 4{
5 /* all current (Jan. 2010) in-kernel boards */ 5#ifdef CONFIG_MIPS_DB1300
6 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
7#else
6 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 8 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
9#endif
7} 10}
diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig
new file mode 100644
index 000000000000..c38b190151c4
--- /dev/null
+++ b/arch/mips/configs/db1300_defconfig
@@ -0,0 +1,391 @@
1CONFIG_MIPS=y
2CONFIG_MIPS_ALCHEMY=y
3CONFIG_ALCHEMY_GPIOINT_AU1300=y
4CONFIG_MIPS_DB1300=y
5CONFIG_SOC_AU1300=y
6CONFIG_RWSEM_GENERIC_SPINLOCK=y
7CONFIG_ARCH_SUPPORTS_OPROFILE=y
8CONFIG_GENERIC_HWEIGHT=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_CMOS_UPDATE=y
12CONFIG_SCHED_OMIT_FRAME_POINTER=y
13CONFIG_CEVT_R4K_LIB=y
14CONFIG_CSRC_R4K_LIB=y
15CONFIG_DMA_COHERENT=y
16CONFIG_SYS_HAS_EARLY_PRINTK=y
17CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
18CONFIG_GENERIC_GPIO=y
19CONFIG_CPU_LITTLE_ENDIAN=y
20CONFIG_SYS_SUPPORTS_APM_EMULATION=y
21CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
22CONFIG_IRQ_CPU=y
23CONFIG_MIPS_L1_CACHE_SHIFT=5
24CONFIG_CPU_MIPS32_R1=y
25CONFIG_SYS_SUPPORTS_ZBOOT=y
26CONFIG_SYS_HAS_CPU_MIPS32_R1=y
27CONFIG_CPU_MIPS32=y
28CONFIG_CPU_MIPSR1=y
29CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
30CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
31CONFIG_HARDWARE_WATCHPOINTS=y
32CONFIG_32BIT=y
33CONFIG_PAGE_SIZE_4KB=y
34CONFIG_FORCE_MAX_ZONEORDER=11
35CONFIG_CPU_HAS_PREFETCH=y
36CONFIG_MIPS_MT_DISABLED=y
37CONFIG_64BIT_PHYS_ADDR=y
38CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
39CONFIG_CPU_HAS_SYNC=y
40CONFIG_CPU_SUPPORTS_HIGHMEM=y
41CONFIG_ARCH_FLATMEM_ENABLE=y
42CONFIG_ARCH_POPULATES_NODE_MAP=y
43CONFIG_SELECT_MEMORY_MODEL=y
44CONFIG_FLATMEM_MANUAL=y
45CONFIG_FLATMEM=y
46CONFIG_FLAT_NODE_MEM_MAP=y
47CONFIG_PAGEFLAGS_EXTENDED=y
48CONFIG_SPLIT_PTLOCK_CPUS=4
49CONFIG_COMPACTION=y
50CONFIG_MIGRATION=y
51CONFIG_PHYS_ADDR_T_64BIT=y
52CONFIG_ZONE_DMA_FLAG=0
53CONFIG_VIRT_TO_BUS=y
54CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
55CONFIG_NEED_PER_CPU_KM=y
56CONFIG_TICK_ONESHOT=y
57CONFIG_NO_HZ=y
58CONFIG_HIGH_RES_TIMERS=y
59CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
60CONFIG_HZ_100=y
61CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
62CONFIG_HZ=100
63CONFIG_PREEMPT_NONE=y
64CONFIG_LOCKDEP_SUPPORT=y
65CONFIG_STACKTRACE_SUPPORT=y
66CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
67CONFIG_CONSTRUCTORS=y
68CONFIG_HAVE_IRQ_WORK=y
69CONFIG_EXPERIMENTAL=y
70CONFIG_BROKEN_ON_SMP=y
71CONFIG_INIT_ENV_ARG_LIMIT=32
72CONFIG_CROSS_COMPILE=""
73CONFIG_LOCALVERSION="-db1300"
74CONFIG_LOCALVERSION_AUTO=y
75CONFIG_HAVE_KERNEL_GZIP=y
76CONFIG_HAVE_KERNEL_BZIP2=y
77CONFIG_HAVE_KERNEL_LZMA=y
78CONFIG_HAVE_KERNEL_LZO=y
79CONFIG_KERNEL_LZMA=y
80CONFIG_SWAP=y
81CONFIG_SYSVIPC=y
82CONFIG_SYSVIPC_SYSCTL=y
83CONFIG_POSIX_MQUEUE=y
84CONFIG_POSIX_MQUEUE_SYSCTL=y
85CONFIG_FHANDLE=y
86CONFIG_HAVE_GENERIC_HARDIRQS=y
87CONFIG_GENERIC_HARDIRQS=y
88CONFIG_GENERIC_IRQ_PROBE=y
89CONFIG_GENERIC_IRQ_SHOW=y
90CONFIG_TINY_RCU=y
91CONFIG_LOG_BUF_SHIFT=19
92CONFIG_NAMESPACES=y
93CONFIG_UTS_NS=y
94CONFIG_IPC_NS=y
95CONFIG_USER_NS=y
96CONFIG_PID_NS=y
97CONFIG_NET_NS=y
98CONFIG_SYSCTL=y
99CONFIG_ANON_INODES=y
100CONFIG_EXPERT=y
101CONFIG_SYSCTL_SYSCALL=y
102CONFIG_KALLSYMS=y
103CONFIG_KALLSYMS_ALL=y
104CONFIG_HOTPLUG=y
105CONFIG_PRINTK=y
106CONFIG_BUG=y
107CONFIG_ELF_CORE=y
108CONFIG_BASE_FULL=y
109CONFIG_FUTEX=y
110CONFIG_EPOLL=y
111CONFIG_SIGNALFD=y
112CONFIG_TIMERFD=y
113CONFIG_EVENTFD=y
114CONFIG_SHMEM=y
115CONFIG_AIO=y
116CONFIG_EMBEDDED=y
117CONFIG_HAVE_PERF_EVENTS=y
118CONFIG_PERF_USE_VMALLOC=y
119CONFIG_SLAB=y
120CONFIG_HAVE_OPROFILE=y
121CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_DMA_ATTRS=y
124CONFIG_HAVE_DMA_API_DEBUG=y
125CONFIG_HAVE_ARCH_JUMP_LABEL=y
126CONFIG_HAVE_GENERIC_DMA_COHERENT=y
127CONFIG_SLABINFO=y
128CONFIG_RT_MUTEXES=y
129CONFIG_BASE_SMALL=0
130CONFIG_BLOCK=y
131CONFIG_LBDAF=y
132CONFIG_BLK_DEV_BSG=y
133CONFIG_IOSCHED_NOOP=y
134CONFIG_DEFAULT_NOOP=y
135CONFIG_DEFAULT_IOSCHED="noop"
136CONFIG_INLINE_SPIN_UNLOCK=y
137CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
138CONFIG_INLINE_READ_UNLOCK=y
139CONFIG_INLINE_READ_UNLOCK_IRQ=y
140CONFIG_INLINE_WRITE_UNLOCK=y
141CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
142CONFIG_MMU=y
143CONFIG_PCCARD=y
144CONFIG_PCMCIA=y
145CONFIG_PCMCIA_LOAD_CIS=y
146CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
147CONFIG_BINFMT_ELF=y
148CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
149CONFIG_TRAD_SIGNALS=y
150CONFIG_ARCH_HIBERNATION_POSSIBLE=y
151CONFIG_ARCH_SUSPEND_POSSIBLE=y
152CONFIG_NET=y
153CONFIG_PACKET=y
154CONFIG_UNIX=y
155CONFIG_XFRM=y
156CONFIG_INET=y
157CONFIG_IP_MULTICAST=y
158CONFIG_IP_PNP=y
159CONFIG_IP_PNP_DHCP=y
160CONFIG_IP_PNP_BOOTP=y
161CONFIG_IP_PNP_RARP=y
162CONFIG_INET_TUNNEL=y
163CONFIG_TCP_CONG_CUBIC=y
164CONFIG_DEFAULT_TCP_CONG="cubic"
165CONFIG_IPV6=y
166CONFIG_INET6_XFRM_MODE_TRANSPORT=y
167CONFIG_INET6_XFRM_MODE_TUNNEL=y
168CONFIG_INET6_XFRM_MODE_BEET=y
169CONFIG_IPV6_SIT=y
170CONFIG_IPV6_NDISC_NODETYPE=y
171CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
172CONFIG_STANDALONE=y
173CONFIG_PREVENT_FIRMWARE_BUILD=y
174CONFIG_FW_LOADER=y
175CONFIG_FIRMWARE_IN_KERNEL=y
176CONFIG_EXTRA_FIRMWARE=""
177CONFIG_MTD=y
178CONFIG_MTD_CMDLINE_PARTS=y
179CONFIG_MTD_CHAR=y
180CONFIG_MTD_BLKDEVS=y
181CONFIG_MTD_BLOCK=y
182CONFIG_MTD_CFI=y
183CONFIG_MTD_GEN_PROBE=y
184CONFIG_MTD_MAP_BANK_WIDTH_1=y
185CONFIG_MTD_MAP_BANK_WIDTH_2=y
186CONFIG_MTD_MAP_BANK_WIDTH_4=y
187CONFIG_MTD_CFI_I1=y
188CONFIG_MTD_CFI_I2=y
189CONFIG_MTD_CFI_AMDSTD=y
190CONFIG_MTD_CFI_UTIL=y
191CONFIG_MTD_PHYSMAP=y
192CONFIG_MTD_NAND_ECC=y
193CONFIG_MTD_NAND=y
194CONFIG_MTD_NAND_IDS=y
195CONFIG_MTD_NAND_PLATFORM=y
196CONFIG_BLK_DEV=y
197CONFIG_BLK_DEV_LOOP=y
198CONFIG_BLK_DEV_UB=y
199CONFIG_HAVE_IDE=y
200CONFIG_IDE=y
201CONFIG_IDE_GD=y
202CONFIG_IDE_GD_ATA=y
203CONFIG_BLK_DEV_IDECS=y
204CONFIG_IDE_TASK_IOCTL=y
205CONFIG_IDE_PROC_FS=y
206CONFIG_BLK_DEV_PLATFORM=y
207CONFIG_SCSI_MOD=y
208CONFIG_NETDEVICES=y
209CONFIG_MII=y
210CONFIG_PHYLIB=y
211CONFIG_SMSC_PHY=y
212CONFIG_NET_ETHERNET=y
213CONFIG_SMSC911X=y
214CONFIG_INPUT=y
215CONFIG_INPUT_EVDEV=y
216CONFIG_INPUT_KEYBOARD=y
217CONFIG_KEYBOARD_GPIO=y
218CONFIG_INPUT_TOUCHSCREEN=y
219CONFIG_TOUCHSCREEN_WM97XX=y
220CONFIG_TOUCHSCREEN_WM9712=y
221CONFIG_TOUCHSCREEN_WM9713=y
222CONFIG_INPUT_MISC=y
223CONFIG_INPUT_UINPUT=y
224CONFIG_VT=y
225CONFIG_CONSOLE_TRANSLATIONS=y
226CONFIG_VT_CONSOLE=y
227CONFIG_HW_CONSOLE=y
228CONFIG_VT_HW_CONSOLE_BINDING=y
229CONFIG_UNIX98_PTYS=y
230CONFIG_SERIAL_8250=y
231CONFIG_SERIAL_8250_CONSOLE=y
232CONFIG_SERIAL_8250_NR_UARTS=4
233CONFIG_SERIAL_8250_RUNTIME_UARTS=4
234CONFIG_SERIAL_CORE=y
235CONFIG_SERIAL_CORE_CONSOLE=y
236CONFIG_I2C=y
237CONFIG_I2C_BOARDINFO=y
238CONFIG_I2C_CHARDEV=y
239CONFIG_I2C_SMBUS=y
240CONFIG_I2C_AU1550=y
241CONFIG_SPI=y
242CONFIG_SPI_MASTER=y
243CONFIG_SPI_AU1550=y
244CONFIG_SPI_BITBANG=y
245CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
246CONFIG_HWMON=y
247CONFIG_HWMON_VID=y
248CONFIG_SENSORS_ADM1025=y
249CONFIG_FB=y
250CONFIG_FB_AU1200=y
251CONFIG_DUMMY_CONSOLE=y
252CONFIG_FRAMEBUFFER_CONSOLE=y
253CONFIG_FONTS=y
254CONFIG_FONT_ACORN_8x8=y
255CONFIG_LOGO=y
256CONFIG_LOGO_LINUX_CLUT224=y
257CONFIG_SOUND=y
258CONFIG_SND=y
259CONFIG_SND_TIMER=y
260CONFIG_SND_PCM=y
261CONFIG_SND_JACK=y
262CONFIG_SND_HRTIMER=y
263CONFIG_SND_DYNAMIC_MINORS=y
264CONFIG_SND_VERBOSE_PROCFS=y
265CONFIG_SND_VERBOSE_PRINTK=y
266CONFIG_SND_VMASTER=y
267CONFIG_SND_AC97_CODEC=y
268CONFIG_SND_SOC=y
269CONFIG_SND_SOC_CACHE_LZO=y
270CONFIG_SND_SOC_AC97_BUS=y
271CONFIG_SND_SOC_AU1XPSC=y
272CONFIG_SND_SOC_AU1XPSC_I2S=y
273CONFIG_SND_SOC_AU1XPSC_AC97=y
274CONFIG_SND_SOC_DB1300=y
275CONFIG_SND_SOC_I2C_AND_SPI=y
276CONFIG_SND_SOC_WM8731=y
277CONFIG_SND_SOC_WM9712=y
278CONFIG_AC97_BUS=y
279CONFIG_HID_SUPPORT=y
280CONFIG_HID=y
281CONFIG_HIDRAW=y
282CONFIG_USB_HID=y
283CONFIG_USB_HIDDEV=y
284CONFIG_USB_SUPPORT=y
285CONFIG_USB_ARCH_HAS_HCD=y
286CONFIG_USB_ARCH_HAS_OHCI=y
287CONFIG_USB_ARCH_HAS_EHCI=y
288CONFIG_USB=y
289CONFIG_USB_DYNAMIC_MINORS=y
290CONFIG_USB_EHCI_HCD=y
291CONFIG_USB_EHCI_ROOT_HUB_TT=y
292CONFIG_USB_EHCI_TT_NEWSCHED=y
293CONFIG_USB_OHCI_HCD=y
294CONFIG_USB_OHCI_LITTLE_ENDIAN=y
295CONFIG_RTC_LIB=y
296CONFIG_RTC_CLASS=y
297CONFIG_RTC_HCTOSYS=y
298CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
299CONFIG_RTC_INTF_SYSFS=y
300CONFIG_RTC_INTF_PROC=y
301CONFIG_RTC_INTF_DEV=y
302CONFIG_RTC_INTF_DEV_UIE_EMUL=y
303CONFIG_RTC_DRV_AU1XXX=y
304CONFIG_EXT2_FS=y
305CONFIG_FS_POSIX_ACL=y
306CONFIG_EXPORTFS=y
307CONFIG_FILE_LOCKING=y
308CONFIG_FSNOTIFY=y
309CONFIG_DNOTIFY=y
310CONFIG_INOTIFY_USER=y
311CONFIG_GENERIC_ACL=y
312CONFIG_FAT_FS=y
313CONFIG_VFAT_FS=y
314CONFIG_FAT_DEFAULT_CODEPAGE=437
315CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
316CONFIG_PROC_FS=y
317CONFIG_PROC_SYSCTL=y
318CONFIG_PROC_PAGE_MONITOR=y
319CONFIG_SYSFS=y
320CONFIG_TMPFS=y
321CONFIG_TMPFS_POSIX_ACL=y
322CONFIG_TMPFS_XATTR=y
323CONFIG_MISC_FILESYSTEMS=y
324CONFIG_JFFS2_FS=y
325CONFIG_JFFS2_FS_DEBUG=0
326CONFIG_JFFS2_FS_WRITEBUFFER=y
327CONFIG_JFFS2_SUMMARY=y
328CONFIG_JFFS2_FS_XATTR=y
329CONFIG_JFFS2_FS_POSIX_ACL=y
330CONFIG_JFFS2_FS_SECURITY=y
331CONFIG_JFFS2_COMPRESSION_OPTIONS=y
332CONFIG_JFFS2_ZLIB=y
333CONFIG_JFFS2_LZO=y
334CONFIG_JFFS2_RTIME=y
335CONFIG_JFFS2_RUBIN=y
336CONFIG_JFFS2_CMODE_PRIORITY=y
337CONFIG_SQUASHFS=y
338CONFIG_SQUASHFS_XZ=y
339CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
340CONFIG_NETWORK_FILESYSTEMS=y
341CONFIG_NFS_FS=y
342CONFIG_NFS_V3=y
343CONFIG_ROOT_NFS=y
344CONFIG_LOCKD=y
345CONFIG_LOCKD_V4=y
346CONFIG_NFS_COMMON=y
347CONFIG_SUNRPC=y
348CONFIG_MSDOS_PARTITION=y
349CONFIG_NLS=y
350CONFIG_NLS_DEFAULT="iso8859-1"
351CONFIG_NLS_CODEPAGE_437=y
352CONFIG_NLS_CODEPAGE_850=y
353CONFIG_NLS_ASCII=y
354CONFIG_NLS_ISO8859_1=y
355CONFIG_NLS_ISO8859_15=y
356CONFIG_NLS_UTF8=y
357CONFIG_TRACE_IRQFLAGS_SUPPORT=y
358CONFIG_PRINTK_TIME=y
359CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
360CONFIG_ENABLE_WARN_DEPRECATED=y
361CONFIG_ENABLE_MUST_CHECK=y
362CONFIG_FRAME_WARN=1024
363CONFIG_MAGIC_SYSRQ=y
364CONFIG_STRIP_ASM_SYMS=y
365CONFIG_HAVE_FUNCTION_TRACER=y
366CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
367CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
368CONFIG_HAVE_DYNAMIC_FTRACE=y
369CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
370CONFIG_HAVE_C_RECORDMCOUNT=y
371CONFIG_TRACING_SUPPORT=y
372CONFIG_HAVE_ARCH_KGDB=y
373CONFIG_EARLY_PRINTK=y
374CONFIG_CMDLINE_BOOL=y
375CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200"
376CONFIG_DEBUG_ZBOOT=y
377CONFIG_DEFAULT_SECURITY_DAC=y
378CONFIG_DEFAULT_SECURITY=""
379CONFIG_CRYPTO=y
380CONFIG_BITREVERSE=y
381CONFIG_CRC32=y
382CONFIG_ZLIB_INFLATE=y
383CONFIG_ZLIB_DEFLATE=y
384CONFIG_LZO_COMPRESS=y
385CONFIG_LZO_DECOMPRESS=y
386CONFIG_XZ_DEC=y
387CONFIG_HAS_IOMEM=y
388CONFIG_HAS_IOPORT=y
389CONFIG_HAS_DMA=y
390CONFIG_NLATTR=y
391CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..0ef630071304 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36 36
37#define DB1300_BCSR_PHYS_ADDR 0x19800000
38#define DB1300_BCSR_HEXLED_OFS 0x00400000
37 39
38enum bcsr_id { 40enum bcsr_id {
39 /* BCSR base 1 */ 41 /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2, 108 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200, 109 BCSR_WHOAMI_DB1200,
110 BCSR_WHOAMI_DB1300,
108}; 111};
109 112
110/* STATUS reg. Unless otherwise noted, they're valid on all boards. 113/* STATUS reg. Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
118#define BCSR_STATUS_SRAMWIDTH 0x0080 121#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100 122#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400 123#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */
122#define BCSR_STATUS_SD1WP 0x0800 125#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000 132#define BCSR_STATUS_FLASHDEN 0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135 138
139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */
140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */
142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */
143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */
136 144
137/* DB/PB1000,1100,1500,1550 */ 145/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001 146#define BCSR_RESETS_PHY0 0x0001
@@ -160,12 +168,12 @@ enum bcsr_whoami_boards {
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161 169
162 170
163/* DB/PB1200 */ 171/* DB/PB1200/1300 */
164#define BCSR_RESETS_ETH 0x0001 172#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002 173#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004 174#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008 175#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */ 176#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */
169/* Not resets but in the same register */ 177/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 178#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 179#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
174#define BCSR_RESETS_SPISEL 0x4000 182#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 183#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176 184
185#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */
186#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */
187#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */
188#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */
189#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
190#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */
191#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */
192
177#define BCSR_BOARD_LCDVEE 0x0001 193#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002 194#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004 195#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010 196#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020 197#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040 198#define BCSR_BOARD_SD0PWR 0x0040
183 199#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */
200#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */
184 201
185#define BCSR_SWITCHES_DIP 0x00FF 202#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080 203#define BCSR_SWITCHES_DIP_1 0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 231#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 232#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 233#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217 234#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */
235#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */
236#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */
237#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */
218 238
219 239
220 240
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
1/*
2 * NetLogic DB1300 board constants
3 */
4
5#ifndef _DB1300_H_
6#define _DB1300_H_
7
8/* FPGA (external mux) interrupt sources */
9#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR 0x19000000
29#define DB1300_ETH_PHYS_END 0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR 0x18800000
33#define DB1300_IDE_REG_SHIFT 5
34#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR 0x20000000
38#define DB1300_NAND_PHYS_END 0x20000fff
39
40#endif /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_IRQ_H
9#define __ASM_MACH_GENERIC_IRQ_H
10
11
12#ifdef NR_IRQS
13#undef NR_IRQS
14#endif
15
16#ifndef MIPS_CPU_IRQ_BASE
17#define MIPS_CPU_IRQ_BASE 0
18#endif
19
20/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
21#define NR_IRQS 152
22
23#endif /* __ASM_MACH_GENERIC_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 15:52:07 -0500