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authorAndrew Bresticker <abrestic@chromium.org>2014-10-20 15:03:53 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 01:44:59 -0500
commit4060bbe9931eca2ed3c2124022a070a75d507472 (patch)
treed3e579a5eb683dabd44ab0a057c0d1d58f5751ce /arch/mips
parent5f68fea09ef1bc36e16d1059a84cf8b833cfb789 (diff)
MIPS: Move gic.h to include/linux/irqchip/mips-gic.h
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/gic.h325
-rw-r--r--arch/mips/include/asm/mips-boards/maltaint.h2
-rw-r--r--arch/mips/include/asm/mips-boards/sead3int.h2
-rw-r--r--arch/mips/kernel/cevt-gic.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/csrc-gic.c3
-rw-r--r--arch/mips/kernel/smp-cmp.c2
-rw-r--r--arch/mips/kernel/smp-cps.c2
-rw-r--r--arch/mips/kernel/smp-gic.c2
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/mti-malta/malta-int.c2
-rw-r--r--arch/mips/mti-malta/malta-time.c2
-rw-r--r--arch/mips/mti-sead3/sead3-ehci.c2
-rw-r--r--arch/mips/mti-sead3/sead3-int.c2
-rw-r--r--arch/mips/mti-sead3/sead3-net.c2
-rw-r--r--arch/mips/mti-sead3/sead3-platform.c2
-rw-r--r--arch/mips/mti-sead3/sead3-time.c2
17 files changed, 16 insertions, 342 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
deleted file mode 100644
index 285944ca9f6c..000000000000
--- a/arch/mips/include/asm/gic.h
+++ /dev/null
@@ -1,325 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * GIC Register Definitions
9 *
10 */
11#ifndef _ASM_GICREGS_H
12#define _ASM_GICREGS_H
13
14#include <linux/bitmap.h>
15#include <linux/threads.h>
16
17#include <irq.h>
18
19#define GIC_MAX_INTRS 256
20
21/* Constants */
22#define GIC_POL_POS 1
23#define GIC_POL_NEG 0
24#define GIC_TRIG_EDGE 1
25#define GIC_TRIG_LEVEL 0
26#define GIC_TRIG_DUAL_ENABLE 1
27#define GIC_TRIG_DUAL_DISABLE 0
28
29#define MSK(n) ((1 << (n)) - 1)
30
31/* Accessors */
32#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
33
34/* GIC Address Space */
35#define SHARED_SECTION_OFS 0x0000
36#define SHARED_SECTION_SIZE 0x8000
37#define VPE_LOCAL_SECTION_OFS 0x8000
38#define VPE_LOCAL_SECTION_SIZE 0x4000
39#define VPE_OTHER_SECTION_OFS 0xc000
40#define VPE_OTHER_SECTION_SIZE 0x4000
41#define USM_VISIBLE_SECTION_OFS 0x10000
42#define USM_VISIBLE_SECTION_SIZE 0x10000
43
44/* Register Map for Shared Section */
45
46#define GIC_SH_CONFIG_OFS 0x0000
47
48/* Shared Global Counter */
49#define GIC_SH_COUNTER_31_00_OFS 0x0010
50#define GIC_SH_COUNTER_63_32_OFS 0x0014
51#define GIC_SH_REVISIONID_OFS 0x0020
52
53/* Interrupt Polarity */
54#define GIC_SH_POL_31_0_OFS 0x0100
55#define GIC_SH_POL_63_32_OFS 0x0104
56#define GIC_SH_POL_95_64_OFS 0x0108
57#define GIC_SH_POL_127_96_OFS 0x010c
58#define GIC_SH_POL_159_128_OFS 0x0110
59#define GIC_SH_POL_191_160_OFS 0x0114
60#define GIC_SH_POL_223_192_OFS 0x0118
61#define GIC_SH_POL_255_224_OFS 0x011c
62
63/* Edge/Level Triggering */
64#define GIC_SH_TRIG_31_0_OFS 0x0180
65#define GIC_SH_TRIG_63_32_OFS 0x0184
66#define GIC_SH_TRIG_95_64_OFS 0x0188
67#define GIC_SH_TRIG_127_96_OFS 0x018c
68#define GIC_SH_TRIG_159_128_OFS 0x0190
69#define GIC_SH_TRIG_191_160_OFS 0x0194
70#define GIC_SH_TRIG_223_192_OFS 0x0198
71#define GIC_SH_TRIG_255_224_OFS 0x019c
72
73/* Dual Edge Triggering */
74#define GIC_SH_DUAL_31_0_OFS 0x0200
75#define GIC_SH_DUAL_63_32_OFS 0x0204
76#define GIC_SH_DUAL_95_64_OFS 0x0208
77#define GIC_SH_DUAL_127_96_OFS 0x020c
78#define GIC_SH_DUAL_159_128_OFS 0x0210
79#define GIC_SH_DUAL_191_160_OFS 0x0214
80#define GIC_SH_DUAL_223_192_OFS 0x0218
81#define GIC_SH_DUAL_255_224_OFS 0x021c
82
83/* Set/Clear corresponding bit in Edge Detect Register */
84#define GIC_SH_WEDGE_OFS 0x0280
85
86/* Reset Mask - Disables Interrupt */
87#define GIC_SH_RMASK_31_0_OFS 0x0300
88#define GIC_SH_RMASK_63_32_OFS 0x0304
89#define GIC_SH_RMASK_95_64_OFS 0x0308
90#define GIC_SH_RMASK_127_96_OFS 0x030c
91#define GIC_SH_RMASK_159_128_OFS 0x0310
92#define GIC_SH_RMASK_191_160_OFS 0x0314
93#define GIC_SH_RMASK_223_192_OFS 0x0318
94#define GIC_SH_RMASK_255_224_OFS 0x031c
95
96/* Set Mask (WO) - Enables Interrupt */
97#define GIC_SH_SMASK_31_0_OFS 0x0380
98#define GIC_SH_SMASK_63_32_OFS 0x0384
99#define GIC_SH_SMASK_95_64_OFS 0x0388
100#define GIC_SH_SMASK_127_96_OFS 0x038c
101#define GIC_SH_SMASK_159_128_OFS 0x0390
102#define GIC_SH_SMASK_191_160_OFS 0x0394
103#define GIC_SH_SMASK_223_192_OFS 0x0398
104#define GIC_SH_SMASK_255_224_OFS 0x039c
105
106/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
107#define GIC_SH_MASK_31_0_OFS 0x0400
108#define GIC_SH_MASK_63_32_OFS 0x0404
109#define GIC_SH_MASK_95_64_OFS 0x0408
110#define GIC_SH_MASK_127_96_OFS 0x040c
111#define GIC_SH_MASK_159_128_OFS 0x0410
112#define GIC_SH_MASK_191_160_OFS 0x0414
113#define GIC_SH_MASK_223_192_OFS 0x0418
114#define GIC_SH_MASK_255_224_OFS 0x041c
115
116/* Pending Global Interrupts (RO) */
117#define GIC_SH_PEND_31_0_OFS 0x0480
118#define GIC_SH_PEND_63_32_OFS 0x0484
119#define GIC_SH_PEND_95_64_OFS 0x0488
120#define GIC_SH_PEND_127_96_OFS 0x048c
121#define GIC_SH_PEND_159_128_OFS 0x0490
122#define GIC_SH_PEND_191_160_OFS 0x0494
123#define GIC_SH_PEND_223_192_OFS 0x0498
124#define GIC_SH_PEND_255_224_OFS 0x049c
125
126#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
127
128/* Maps Interrupt X to a Pin */
129#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
130
131#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
132
133/* Maps Interrupt X to a VPE */
134#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
135 ((32 * (intr)) + (((vpe) / 32) * 4))
136#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
137
138/* Convert an interrupt number to a byte offset/bit for multi-word registers */
139#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
140#define GIC_INTR_BIT(intr) ((intr) % 32)
141
142/* Polarity : Reset Value is always 0 */
143#define GIC_SH_SET_POLARITY_OFS 0x0100
144
145/* Triggering : Reset Value is always 0 */
146#define GIC_SH_SET_TRIGGER_OFS 0x0180
147
148/* Dual edge triggering : Reset Value is always 0 */
149#define GIC_SH_SET_DUAL_OFS 0x0200
150
151/* Mask manipulation */
152#define GIC_SH_SMASK_OFS 0x0380
153#define GIC_SH_RMASK_OFS 0x0300
154
155/* Register Map for Local Section */
156#define GIC_VPE_CTL_OFS 0x0000
157#define GIC_VPE_PEND_OFS 0x0004
158#define GIC_VPE_MASK_OFS 0x0008
159#define GIC_VPE_RMASK_OFS 0x000c
160#define GIC_VPE_SMASK_OFS 0x0010
161#define GIC_VPE_WD_MAP_OFS 0x0040
162#define GIC_VPE_COMPARE_MAP_OFS 0x0044
163#define GIC_VPE_TIMER_MAP_OFS 0x0048
164#define GIC_VPE_FDC_MAP_OFS 0x004c
165#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
166#define GIC_VPE_SWINT0_MAP_OFS 0x0054
167#define GIC_VPE_SWINT1_MAP_OFS 0x0058
168#define GIC_VPE_OTHER_ADDR_OFS 0x0080
169#define GIC_VPE_WD_CONFIG0_OFS 0x0090
170#define GIC_VPE_WD_COUNT0_OFS 0x0094
171#define GIC_VPE_WD_INITIAL0_OFS 0x0098
172#define GIC_VPE_COMPARE_LO_OFS 0x00a0
173#define GIC_VPE_COMPARE_HI_OFS 0x00a4
174
175#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
176#define GIC_VPE_EIC_SS(intr) (4 * (intr))
177
178#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800
179#define GIC_VPE_EIC_VEC(intr) (4 * (intr))
180
181#define GIC_VPE_TENABLE_NMI_OFS 0x1000
182#define GIC_VPE_TENABLE_YQ_OFS 0x1004
183#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
184#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
185
186/* User Mode Visible Section Register Map */
187#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
188#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
189
190/* Masks */
191#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
192#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
193
194#define GIC_SH_CONFIG_COUNTBITS_SHF 24
195#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
196
197#define GIC_SH_CONFIG_NUMINTRS_SHF 16
198#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
199
200#define GIC_SH_CONFIG_NUMVPES_SHF 0
201#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
202
203#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
204#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
205
206#define GIC_MAP_TO_PIN_SHF 31
207#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
208#define GIC_MAP_TO_NMI_SHF 30
209#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
210#define GIC_MAP_TO_YQ_SHF 29
211#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
212#define GIC_MAP_SHF 0
213#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
214
215/* GIC_VPE_CTL Masks */
216#define GIC_VPE_CTL_FDC_RTBL_SHF 4
217#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
218#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
219#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
220#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
221#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
222#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
223#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
224#define GIC_VPE_CTL_EIC_MODE_SHF 0
225#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
226
227/* GIC_VPE_PEND Masks */
228#define GIC_VPE_PEND_WD_SHF 0
229#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
230#define GIC_VPE_PEND_CMP_SHF 1
231#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
232#define GIC_VPE_PEND_TIMER_SHF 2
233#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
234#define GIC_VPE_PEND_PERFCOUNT_SHF 3
235#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
236#define GIC_VPE_PEND_SWINT0_SHF 4
237#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
238#define GIC_VPE_PEND_SWINT1_SHF 5
239#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
240
241/* GIC_VPE_RMASK Masks */
242#define GIC_VPE_RMASK_WD_SHF 0
243#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
244#define GIC_VPE_RMASK_CMP_SHF 1
245#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
246#define GIC_VPE_RMASK_TIMER_SHF 2
247#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
248#define GIC_VPE_RMASK_PERFCNT_SHF 3
249#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
250#define GIC_VPE_RMASK_SWINT0_SHF 4
251#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
252#define GIC_VPE_RMASK_SWINT1_SHF 5
253#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
254
255/* GIC_VPE_SMASK Masks */
256#define GIC_VPE_SMASK_WD_SHF 0
257#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
258#define GIC_VPE_SMASK_CMP_SHF 1
259#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
260#define GIC_VPE_SMASK_TIMER_SHF 2
261#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
262#define GIC_VPE_SMASK_PERFCNT_SHF 3
263#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
264#define GIC_VPE_SMASK_SWINT0_SHF 4
265#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
266#define GIC_VPE_SMASK_SWINT1_SHF 5
267#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
268
269/* GIC nomenclature for Core Interrupt Pins. */
270#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
271#define GIC_CPU_INT1 1 /* . */
272#define GIC_CPU_INT2 2 /* . */
273#define GIC_CPU_INT3 3 /* . */
274#define GIC_CPU_INT4 4 /* . */
275#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
276
277/* Add 2 to convert GIC CPU pin to core interrupt */
278#define GIC_CPU_PIN_OFFSET 2
279
280/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
281#define GIC_CPU_TO_VEC_OFFSET (2)
282
283/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
284#define GIC_PIN_TO_VEC_OFFSET (1)
285
286/* Local GIC interrupts. */
287#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
288#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
289#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
290#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
291#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
292#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
293#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
294#define GIC_NUM_LOCAL_INTRS 7
295
296/* Convert between local/shared IRQ number and GIC HW IRQ number. */
297#define GIC_LOCAL_HWIRQ_BASE 0
298#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
299#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
300#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
301#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
302#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
303
304#include <linux/clocksource.h>
305#include <linux/irq.h>
306
307extern unsigned int gic_present;
308extern unsigned int gic_frequency;
309
310extern void gic_init(unsigned long gic_base_addr,
311 unsigned long gic_addrspace_size, unsigned int cpu_vec,
312 unsigned int irqbase);
313extern void gic_clocksource_init(unsigned int);
314extern cycle_t gic_read_count(void);
315extern unsigned int gic_get_count_width(void);
316extern cycle_t gic_read_compare(void);
317extern void gic_write_compare(cycle_t cnt);
318extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
319extern void gic_send_ipi(unsigned int intr);
320extern unsigned int plat_ipi_call_int_xlate(unsigned int);
321extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
322extern unsigned int gic_get_timer_pending(void);
323extern int gic_get_c0_compare_int(void);
324extern int gic_get_c0_perfcount_int(void);
325#endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 38b06a027437..987ff580466b 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -10,7 +10,7 @@
10#ifndef _MIPS_MALTAINT_H 10#ifndef _MIPS_MALTAINT_H
11#define _MIPS_MALTAINT_H 11#define _MIPS_MALTAINT_H
12 12
13#include <asm/gic.h> 13#include <linux/irqchip/mips-gic.h>
14 14
15/* 15/*
16 * Interrupts 0..15 are used for Malta ISA compatible interrupts 16 * Interrupts 0..15 are used for Malta ISA compatible interrupts
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index 59d6c32c7595..8932c7de0419 100644
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -10,7 +10,7 @@
10#ifndef _MIPS_SEAD3INT_H 10#ifndef _MIPS_SEAD3INT_H
11#define _MIPS_SEAD3INT_H 11#define _MIPS_SEAD3INT_H
12 12
13#include <asm/gic.h> 13#include <linux/irqchip/mips-gic.h>
14 14
15/* SEAD-3 GIC address space definitions. */ 15/* SEAD-3 GIC address space definitions. */
16#define GIC_BASE_ADDR 0x1b1c0000 16#define GIC_BASE_ADDR 0x1b1c0000
diff --git a/arch/mips/kernel/cevt-gic.c b/arch/mips/kernel/cevt-gic.c
index 4f9262ab04f9..9caa68a2bcdc 100644
--- a/arch/mips/kernel/cevt-gic.c
+++ b/arch/mips/kernel/cevt-gic.c
@@ -10,9 +10,9 @@
10#include <linux/percpu.h> 10#include <linux/percpu.h>
11#include <linux/smp.h> 11#include <linux/smp.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/irqchip/mips-gic.h>
13 14
14#include <asm/time.h> 15#include <asm/time.h>
15#include <asm/gic.h>
16#include <asm/mips-boards/maltaint.h> 16#include <asm/mips-boards/maltaint.h>
17 17
18DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); 18DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index fd0ef8d851cc..6acaad0480af 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -11,10 +11,10 @@
11#include <linux/percpu.h> 11#include <linux/percpu.h>
12#include <linux/smp.h> 12#include <linux/smp.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/irqchip/mips-gic.h>
14 15
15#include <asm/time.h> 16#include <asm/time.h>
16#include <asm/cevt-r4k.h> 17#include <asm/cevt-r4k.h>
17#include <asm/gic.h>
18 18
19static int mips_next_event(unsigned long delta, 19static int mips_next_event(unsigned long delta,
20 struct clock_event_device *evt) 20 struct clock_event_device *evt)
diff --git a/arch/mips/kernel/csrc-gic.c b/arch/mips/kernel/csrc-gic.c
index ab615c6c51a5..0bf28e6aca7a 100644
--- a/arch/mips/kernel/csrc-gic.c
+++ b/arch/mips/kernel/csrc-gic.c
@@ -6,10 +6,9 @@
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/irqchip/mips-gic.h>
9#include <linux/time.h> 10#include <linux/time.h>
10 11
11#include <asm/gic.h>
12
13static cycle_t gic_hpt_read(struct clocksource *cs) 12static cycle_t gic_hpt_read(struct clocksource *cs)
14{ 13{
15 return gic_read_count(); 14 return gic_read_count();
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index fc8a51553426..1e0a93c5a3e7 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -24,6 +24,7 @@
24#include <linux/cpumask.h> 24#include <linux/cpumask.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/compiler.h> 26#include <linux/compiler.h>
27#include <linux/irqchip/mips-gic.h>
27 28
28#include <linux/atomic.h> 29#include <linux/atomic.h>
29#include <asm/cacheflush.h> 30#include <asm/cacheflush.h>
@@ -37,7 +38,6 @@
37#include <asm/mipsmtregs.h> 38#include <asm/mipsmtregs.h>
38#include <asm/mips_mt.h> 39#include <asm/mips_mt.h>
39#include <asm/amon.h> 40#include <asm/amon.h>
40#include <asm/gic.h>
41 41
42static void cmp_init_secondary(void) 42static void cmp_init_secondary(void)
43{ 43{
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index cd20acad7f17..bed7590e475f 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -9,13 +9,13 @@
9 */ 9 */
10 10
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/irqchip/mips-gic.h>
12#include <linux/sched.h> 13#include <linux/sched.h>
13#include <linux/slab.h> 14#include <linux/slab.h>
14#include <linux/smp.h> 15#include <linux/smp.h>
15#include <linux/types.h> 16#include <linux/types.h>
16 17
17#include <asm/bcache.h> 18#include <asm/bcache.h>
18#include <asm/gic.h>
19#include <asm/mips-cm.h> 19#include <asm/mips-cm.h>
20#include <asm/mips-cpc.h> 20#include <asm/mips-cpc.h>
21#include <asm/mips_mt.h> 21#include <asm/mips_mt.h>
diff --git a/arch/mips/kernel/smp-gic.c b/arch/mips/kernel/smp-gic.c
index 3b21a96d1ccb..5f0ab5bcd01e 100644
--- a/arch/mips/kernel/smp-gic.c
+++ b/arch/mips/kernel/smp-gic.c
@@ -12,9 +12,9 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15#include <linux/irqchip/mips-gic.h>
15#include <linux/printk.h> 16#include <linux/printk.h>
16 17
17#include <asm/gic.h>
18#include <asm/mips-cpc.h> 18#include <asm/mips-cpc.h>
19#include <asm/smp-ops.h> 19#include <asm/smp-ops.h>
20 20
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index d60475fe5957..ad86951b73bd 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -21,6 +21,7 @@
21#include <linux/sched.h> 21#include <linux/sched.h>
22#include <linux/cpumask.h> 22#include <linux/cpumask.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irqchip/mips-gic.h>
24#include <linux/compiler.h> 25#include <linux/compiler.h>
25#include <linux/smp.h> 26#include <linux/smp.h>
26 27
@@ -34,7 +35,6 @@
34#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
35#include <asm/mipsmtregs.h> 36#include <asm/mipsmtregs.h>
36#include <asm/mips_mt.h> 37#include <asm/mips_mt.h>
37#include <asm/gic.h>
38 38
39static void __init smvp_copy_vpe_config(void) 39static void __init smvp_copy_vpe_config(void)
40{ 40{
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index a058e0ba2a26..d1392f8f5811 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -18,6 +18,7 @@
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/irqchip/mips-gic.h>
21#include <linux/kernel_stat.h> 22#include <linux/kernel_stat.h>
22#include <linux/kernel.h> 23#include <linux/kernel.h>
23#include <linux/random.h> 24#include <linux/random.h>
@@ -33,7 +34,6 @@
33#include <asm/mips-boards/generic.h> 34#include <asm/mips-boards/generic.h>
34#include <asm/mips-boards/msc01_pci.h> 35#include <asm/mips-boards/msc01_pci.h>
35#include <asm/msc01_ic.h> 36#include <asm/msc01_ic.h>
36#include <asm/gic.h>
37#include <asm/setup.h> 37#include <asm/setup.h>
38#include <asm/rtlx.h> 38#include <asm/rtlx.h>
39 39
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 39f3902ed341..608655f8e6dd 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -24,6 +24,7 @@
24#include <linux/sched.h> 24#include <linux/sched.h>
25#include <linux/spinlock.h> 25#include <linux/spinlock.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/irqchip/mips-gic.h>
27#include <linux/timex.h> 28#include <linux/timex.h>
28#include <linux/mc146818rtc.h> 29#include <linux/mc146818rtc.h>
29 30
@@ -37,7 +38,6 @@
37#include <asm/time.h> 38#include <asm/time.h>
38#include <asm/mc146818-time.h> 39#include <asm/mc146818-time.h>
39#include <asm/msc01_ic.h> 40#include <asm/msc01_ic.h>
40#include <asm/gic.h>
41 41
42#include <asm/mips-boards/generic.h> 42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/maltaint.h> 43#include <asm/mips-boards/maltaint.h>
diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c
index 4ddaa0fd5804..014dd7ba4d68 100644
--- a/arch/mips/mti-sead3/sead3-ehci.c
+++ b/arch/mips/mti-sead3/sead3-ehci.c
@@ -9,8 +9,8 @@
9#include <linux/irq.h> 9#include <linux/irq.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/irqchip/mips-gic.h>
12 13
13#include <asm/gic.h>
14#include <asm/mips-boards/sead3int.h> 14#include <asm/mips-boards/sead3int.h>
15 15
16struct resource ehci_resources[] = { 16struct resource ehci_resources[] = {
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
index 02bf0dba1127..e31e17f81eef 100644
--- a/arch/mips/mti-sead3/sead3-int.c
+++ b/arch/mips/mti-sead3/sead3-int.c
@@ -7,9 +7,9 @@
7 */ 7 */
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/irq.h> 9#include <linux/irq.h>
10#include <linux/irqchip/mips-gic.h>
10#include <linux/io.h> 11#include <linux/io.h>
11 12
12#include <asm/gic.h>
13#include <asm/irq_cpu.h> 13#include <asm/irq_cpu.h>
14#include <asm/setup.h> 14#include <asm/setup.h>
15 15
diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c
index c9f728a41bdb..46176b804576 100644
--- a/arch/mips/mti-sead3/sead3-net.c
+++ b/arch/mips/mti-sead3/sead3-net.c
@@ -7,10 +7,10 @@
7 */ 7 */
8#include <linux/module.h> 8#include <linux/module.h>
9#include <linux/irq.h> 9#include <linux/irq.h>
10#include <linux/irqchip/mips-gic.h>
10#include <linux/platform_device.h> 11#include <linux/platform_device.h>
11#include <linux/smsc911x.h> 12#include <linux/smsc911x.h>
12 13
13#include <asm/gic.h>
14#include <asm/mips-boards/sead3int.h> 14#include <asm/mips-boards/sead3int.h>
15 15
16static struct smsc911x_platform_config sead3_smsc911x_data = { 16static struct smsc911x_platform_config sead3_smsc911x_data = {
diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c
index d9661eb6fd6d..53ee6f1f018d 100644
--- a/arch/mips/mti-sead3/sead3-platform.c
+++ b/arch/mips/mti-sead3/sead3-platform.c
@@ -7,9 +7,9 @@
7 */ 7 */
8#include <linux/module.h> 8#include <linux/module.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/irqchip/mips-gic.h>
10#include <linux/serial_8250.h> 11#include <linux/serial_8250.h>
11 12
12#include <asm/gic.h>
13#include <asm/mips-boards/sead3int.h> 13#include <asm/mips-boards/sead3int.h>
14 14
15#define UART(base) \ 15#define UART(base) \
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index fd40de352c57..ec1dd2491f96 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -6,9 +6,9 @@
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/irqchip/mips-gic.h>
9 10
10#include <asm/cpu.h> 11#include <asm/cpu.h>
11#include <asm/gic.h>
12#include <asm/setup.h> 12#include <asm/setup.h>
13#include <asm/time.h> 13#include <asm/time.h>
14#include <asm/irq.h> 14#include <asm/irq.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 03:25:20 -0400