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authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-02 07:53:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:05 -0500
commit3f724080a3e91d76ba6d5cacd3cf0a0cf16d121a (patch)
tree5e5b5606bd4822b6b8a4a0f1ef87332b7874af47 /arch/mips
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
MIPS: Alchemy: remove PB1000 support
Noone seems to have test hardware or care anymore. Drop PB1000 support and along with it the old Alchemy PCMCIA socket driver. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-pcmcia@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/2881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/Kconfig9
-rw-r--r--arch/mips/alchemy/Platform7
-rw-r--r--arch/mips/alchemy/common/irq.c11
-rw-r--r--arch/mips/alchemy/devboards/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c209
-rw-r--r--arch/mips/alchemy/devboards/prom.c2
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
8 files changed, 1 insertions, 333 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2a68be6a1b97..5a48387d0751 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -78,15 +78,6 @@ config MIPS_MIRAGE
78 select SYS_SUPPORTS_LITTLE_ENDIAN 78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK 79 select SYS_HAS_EARLY_PRINTK
80 80
81config MIPS_PB1000
82 bool "Alchemy PB1000 board"
83 select ALCHEMY_GPIOINT_AU1000
84 select DMA_NONCOHERENT
85 select HW_HAS_PCI
86 select SWAP_IO_SPACE
87 select SYS_SUPPORTS_LITTLE_ENDIAN
88 select SYS_HAS_EARLY_PRINTK
89
90config MIPS_PB1100 81config MIPS_PB1100
91 bool "Alchemy PB1100 board" 82 bool "Alchemy PB1100 board"
92 select ALCHEMY_GPIOINT_AU1000 83 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 96e9e41f1b2a..4e079672f9bf 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -5,13 +5,6 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
5 5
6 6
7# 7#
8# AMD Alchemy Pb1000 eval board
9#
10platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
11cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
12load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
13
14#
15# AMD Alchemy Pb1100 eval board 8# AMD Alchemy Pb1100 eval board
16# 9#
17platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/ 10platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..2a94a64b7333 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -35,9 +35,6 @@
35#include <asm/irq_cpu.h> 35#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
37#include <asm/mach-au1x00/au1000.h> 37#include <asm/mach-au1x00/au1000.h>
38#ifdef CONFIG_MIPS_PB1000
39#include <asm/mach-pb1x00/pb1000.h>
40#endif
41 38
42/* Interrupt Controller register offsets */ 39/* Interrupt Controller register offsets */
43#define IC_CFG0RD 0x40 40#define IC_CFG0RD 0x40
@@ -265,14 +262,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
265 262
266 __raw_writel(1 << bit, base + IC_MASKSET); 263 __raw_writel(1 << bit, base + IC_MASKSET);
267 __raw_writel(1 << bit, base + IC_WAKESET); 264 __raw_writel(1 << bit, base + IC_WAKESET);
268
269/* very hacky. does the pb1000 cpld auto-disable this int?
270 * nowhere in the current kernel sources is it disabled. --mlau
271 */
272#if defined(CONFIG_MIPS_PB1000)
273 if (d->irq == AU1000_GPIO15_INT)
274 __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
275#endif
276 wmb(); 265 wmb();
277} 266}
278 267
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 826449c817c3..bea80d787781 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y += prom.o bcsr.o platform.o 5obj-y += prom.o bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/
8obj-$(CONFIG_MIPS_PB1100) += pb1100/ 7obj-$(CONFIG_MIPS_PB1100) += pb1100/
9obj-$(CONFIG_MIPS_PB1200) += pb1200/ 8obj-$(CONFIG_MIPS_PB1200) += pb1200/
10obj-$(CONFIG_MIPS_PB1500) += pb1500/ 9obj-$(CONFIG_MIPS_PB1500) += pb1500/
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
deleted file mode 100644
index 97c6615ba2bb..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1000 board.
6#
7
8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
deleted file mode 100644
index e64fdcbf75d0..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/pm.h>
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1000.h>
33#include <asm/reboot.h>
34#include <prom.h>
35
36#include "../platform.h"
37
38const char *get_system_type(void)
39{
40 return "Alchemy Pb1000";
41}
42
43static void board_reset(char *c)
44{
45 asm volatile ("jr %0" : : "r" (0xbfc00000));
46}
47
48static void board_power_off(void)
49{
50 while (1)
51 asm volatile (
52 " .set mips32 \n"
53 " wait \n"
54 " .set mips0 \n");
55}
56
57void __init board_setup(void)
58{
59 u32 pin_func, static_cfg0;
60 u32 sys_freqctrl, sys_clksrc;
61 u32 prid = read_c0_prid();
62
63 sys_freqctrl = 0;
64 sys_clksrc = 0;
65
66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
67 au_writel(8, SYS_AUXPLL);
68 alchemy_gpio1_input_enable();
69 udelay(100);
70
71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
72 /* Zero and disable FREQ2 */
73 sys_freqctrl = au_readl(SYS_FREQCTRL0);
74 sys_freqctrl &= ~0xFFF00000;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /* Zero and disable USBH/USBD clocks */
78 sys_clksrc = au_readl(SYS_CLKSRC);
79 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
80 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 sys_freqctrl = au_readl(SYS_FREQCTRL0);
84 sys_freqctrl &= ~0xFFF00000;
85
86 sys_clksrc = au_readl(SYS_CLKSRC);
87 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
88 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
89
90 switch (prid & 0x000000FF) {
91 case 0x00: /* DA */
92 case 0x01: /* HA */
93 case 0x02: /* HB */
94 /* CPU core freq to 48 MHz to slow it way down... */
95 au_writel(4, SYS_CPUPLL);
96
97 /*
98 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
99 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
100 */
101 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
102 au_writel(sys_freqctrl, SYS_FREQCTRL0);
103
104 /* CPU core freq to 384 MHz */
105 au_writel(0x20, SYS_CPUPLL);
106
107 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
108 break;
109
110 default: /* HC and newer */
111 /* FREQ2 = aux / 2 = 48 MHz */
112 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
113 SYS_FC_FE2 | SYS_FC_FS2;
114 au_writel(sys_freqctrl, SYS_FREQCTRL0);
115 break;
116 }
117
118 /*
119 * Route 48 MHz FREQ2 into USB Host and/or Device
120 */
121 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
122 au_writel(sys_clksrc, SYS_CLKSRC);
123
124 /* Configure pins GPIO[14:9] as GPIO */
125 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
126
127 /* 2nd USB port is USB host */
128 pin_func |= SYS_PF_USB;
129
130 au_writel(pin_func, SYS_PINFUNC);
131
132 alchemy_gpio_direction_input(11);
133 alchemy_gpio_direction_input(13);
134 alchemy_gpio_direction_output(4, 0);
135 alchemy_gpio_direction_output(5, 0);
136#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
137
138 /* Make GPIO 15 an input (for interrupt line) */
139 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
140 /* We don't need I2S, so make it available for GPIO[31:29] */
141 pin_func |= SYS_PF_I2S;
142 au_writel(pin_func, SYS_PINFUNC);
143
144 alchemy_gpio_direction_input(15);
145
146 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
147 au_writel(static_cfg0, MEM_STCFG0);
148
149 /* configure RCE2* for LCD */
150 au_writel(0x00000004, MEM_STCFG2);
151
152 /* MEM_STTIME2 */
153 au_writel(0x09000000, MEM_STTIME2);
154
155 /* Set 32-bit base address decoding for RCE2* */
156 au_writel(0x10003ff0, MEM_STADDR2);
157
158 /*
159 * PCI CPLD setup
160 * Expand CE0 to cover PCI
161 */
162 au_writel(0x11803e40, MEM_STADDR1);
163
164 /* Burst visibility on */
165 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
166
167 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
168 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
169
170 /* Setup the static bus controller */
171 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
172 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
173 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
174
175 /*
176 * Enable Au1000 BCLK switching - note: sed1356 must not use
177 * its BCLK (Au1000 LCLK) for any timings
178 */
179 switch (prid & 0x000000FF) {
180 case 0x00: /* DA */
181 case 0x01: /* HA */
182 case 0x02: /* HB */
183 break;
184 default: /* HC and newer */
185 /*
186 * Enable sys bus clock divider when IDLE state or no bus
187 * activity.
188 */
189 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
190 break;
191 }
192
193 pm_power_off = board_power_off;
194 _machine_halt = board_power_off;
195 _machine_restart = board_reset;
196}
197
198static int __init pb1000_init_irq(void)
199{
200 irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
201 return 0;
202}
203arch_initcall(pb1000_init_irq);
204
205static int __init pb1000_device_init(void)
206{
207 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
208}
209device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index e5306b56da6d..56d7ea52fd97 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -33,7 +33,7 @@
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <prom.h> 34#include <prom.h>
35 35
36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ 36#if defined(CONFIG_MIPS_DB1000) || \
37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ 37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ 38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) 39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
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