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authorIngo Molnar <mingo@kernel.org>2013-07-01 05:16:54 -0400
committerIngo Molnar <mingo@kernel.org>2013-07-01 05:18:53 -0400
commit2fd1b487884310d0aa0c0640179dc7490ad86313 (patch)
tree1083dce15bd7dc0858c3883b8a361242046c5e09 /arch/mips
parent333bb864f192015a53b5060b829089decd0220ef (diff)
parent8bb495e3f02401ee6f76d1b1d77f3ac9f079e376 (diff)
Merge tag 'v3.10' into sched/core
Merge in a recent upstream commit: c2853c8df57f include/linux/math64.h: add div64_ul() because: 72a4cf20cb71 sched: Change cfs_rq load avg to unsigned long relies on it. [ We don't rebase sched/core for this, because the handful of followup commits after the broken commit are not behavioral changes so are unlikely to be needed during bisection. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/cavium-octeon/setup.c15
-rw-r--r--arch/mips/include/asm/kvm_host.h4
-rw-r--r--arch/mips/include/asm/mmu_context.h2
-rw-r--r--arch/mips/include/asm/ptrace.h32
-rw-r--r--arch/mips/include/uapi/asm/kvm.h134
-rw-r--r--arch/mips/include/uapi/asm/ptrace.h17
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c11
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c11
-rw-r--r--arch/mips/kernel/ftrace.c4
-rw-r--r--arch/mips/kernel/idle.c13
-rw-r--r--arch/mips/kernel/rtlx.c1
-rw-r--r--arch/mips/kernel/traps.c28
-rw-r--r--arch/mips/kvm/kvm_mips.c305
-rw-r--r--arch/mips/kvm/kvm_trap_emul.c50
-rw-r--r--arch/mips/mm/tlbex.c4
-rw-r--r--arch/mips/ralink/of.c2
16 files changed, 485 insertions, 148 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b0baa299f899..01b1b3f94feb 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -428,13 +428,16 @@ static void octeon_restart(char *command)
428 */ 428 */
429static void octeon_kill_core(void *arg) 429static void octeon_kill_core(void *arg)
430{ 430{
431 mb(); 431 if (octeon_is_simulation())
432 if (octeon_is_simulation()) {
433 /* The simulator needs the watchdog to stop for dead cores */
434 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
435 /* A break instruction causes the simulator stop a core */ 432 /* A break instruction causes the simulator stop a core */
436 asm volatile ("sync\nbreak"); 433 asm volatile ("break" ::: "memory");
437 } 434
435 local_irq_disable();
436 /* Disable watchdog on this core. */
437 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
438 /* Spin in a low power mode. */
439 while (true)
440 asm volatile ("wait" ::: "memory");
438} 441}
439 442
440 443
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 143875c6c95a..4d6fa0bf1305 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -496,10 +496,6 @@ struct kvm_mips_callbacks {
496 uint32_t cause); 496 uint32_t cause);
497 int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority, 497 int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
498 uint32_t cause); 498 uint32_t cause);
499 int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu,
500 struct kvm_regs *regs);
501 int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu,
502 struct kvm_regs *regs);
503}; 499};
504extern struct kvm_mips_callbacks *kvm_mips_callbacks; 500extern struct kvm_mips_callbacks *kvm_mips_callbacks;
505int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); 501int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
117 if (! ((asid += ASID_INC) & ASID_MASK) ) { 117 if (! ((asid += ASID_INC) & ASID_MASK) ) {
118 if (cpu_has_vtag_icache) 118 if (cpu_has_vtag_icache)
119 flush_icache_all(); 119 flush_icache_all();
120#ifdef CONFIG_VIRTUALIZATION 120#ifdef CONFIG_KVM
121 kvm_local_flush_tlb_all(); /* start new asid cycle */ 121 kvm_local_flush_tlb_all(); /* start new asid cycle */
122#else 122#else
123 local_flush_tlb_all(); /* start new asid cycle */ 123 local_flush_tlb_all(); /* start new asid cycle */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index a3186f2bb8a0..5e6cd0947393 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -16,6 +16,38 @@
16#include <asm/isadep.h> 16#include <asm/isadep.h>
17#include <uapi/asm/ptrace.h> 17#include <uapi/asm/ptrace.h>
18 18
19/*
20 * This struct defines the way the registers are stored on the stack during a
21 * system call/exception. As usual the registers k0/k1 aren't being saved.
22 */
23struct pt_regs {
24#ifdef CONFIG_32BIT
25 /* Pad bytes for argument save space on the stack. */
26 unsigned long pad0[6];
27#endif
28
29 /* Saved main processor registers. */
30 unsigned long regs[32];
31
32 /* Saved special registers. */
33 unsigned long cp0_status;
34 unsigned long hi;
35 unsigned long lo;
36#ifdef CONFIG_CPU_HAS_SMARTMIPS
37 unsigned long acx;
38#endif
39 unsigned long cp0_badvaddr;
40 unsigned long cp0_cause;
41 unsigned long cp0_epc;
42#ifdef CONFIG_MIPS_MT_SMTC
43 unsigned long cp0_tcstatus;
44#endif /* CONFIG_MIPS_MT_SMTC */
45#ifdef CONFIG_CPU_CAVIUM_OCTEON
46 unsigned long long mpl[3]; /* MTM{0,1,2} */
47 unsigned long long mtp[3]; /* MTP{0,1,2} */
48#endif
49} __aligned(8);
50
19struct task_struct; 51struct task_struct;
20 52
21extern int ptrace_getregs(struct task_struct *child, __s64 __user *data); 53extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 85789eacbf18..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -1,55 +1,135 @@
1/* 1/*
2* This file is subject to the terms and conditions of the GNU General Public 2 * This file is subject to the terms and conditions of the GNU General Public
3* License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4* for more details. 4 * for more details.
5* 5 *
6* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7* Authors: Sanjay Lal <sanjayl@kymasys.com> 7 * Copyright (C) 2013 Cavium, Inc.
8*/ 8 * Authors: Sanjay Lal <sanjayl@kymasys.com>
9 */
9 10
10#ifndef __LINUX_KVM_MIPS_H 11#ifndef __LINUX_KVM_MIPS_H
11#define __LINUX_KVM_MIPS_H 12#define __LINUX_KVM_MIPS_H
12 13
13#include <linux/types.h> 14#include <linux/types.h>
14 15
15#define __KVM_MIPS 16/*
16 17 * KVM MIPS specific structures and definitions.
17#define N_MIPS_COPROC_REGS 32 18 *
18#define N_MIPS_COPROC_SEL 8 19 * Some parts derived from the x86 version of this file.
20 */
19 21
20/* for KVM_GET_REGS and KVM_SET_REGS */ 22/*
23 * for KVM_GET_REGS and KVM_SET_REGS
24 *
25 * If Config[AT] is zero (32-bit CPU), the register contents are
26 * stored in the lower 32-bits of the struct kvm_regs fields and sign
27 * extended to 64-bits.
28 */
21struct kvm_regs { 29struct kvm_regs {
22 __u32 gprs[32]; 30 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
23 __u32 hi; 31 __u64 gpr[32];
24 __u32 lo; 32 __u64 hi;
25 __u32 pc; 33 __u64 lo;
26 34 __u64 pc;
27 __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
28};
29
30/* for KVM_GET_SREGS and KVM_SET_SREGS */
31struct kvm_sregs {
32}; 35};
33 36
34/* for KVM_GET_FPU and KVM_SET_FPU */ 37/*
38 * for KVM_GET_FPU and KVM_SET_FPU
39 *
40 * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs
41 * are zero filled.
42 */
35struct kvm_fpu { 43struct kvm_fpu {
44 __u64 fpr[32];
45 __u32 fir;
46 __u32 fccr;
47 __u32 fexr;
48 __u32 fenr;
49 __u32 fcsr;
50 __u32 pad;
36}; 51};
37 52
53
54/*
55 * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
56 * registers. The id field is broken down as follows:
57 *
58 * bits[2..0] - Register 'sel' index.
59 * bits[7..3] - Register 'rd' index.
60 * bits[15..8] - Must be zero.
61 * bits[31..16] - 1 -> CP0 registers.
62 * bits[51..32] - Must be zero.
63 * bits[63..52] - As per linux/kvm.h
64 *
65 * Other sets registers may be added in the future. Each set would
66 * have its own identifier in bits[31..16].
67 *
68 * The registers defined in struct kvm_regs are also accessible, the
69 * id values for these are below.
70 */
71
72#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
73#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
74#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
75#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
76#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
77#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
78#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
79#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
80#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
81#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
82#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
83#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
84#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
85#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
86#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
87#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
88#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
89#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
90#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
91#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
92#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
93#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
94#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
95#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
96#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
97#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
98#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
99#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
100#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
101#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
102#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
103#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
104
105#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
106#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
107#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
108
109/*
110 * KVM MIPS specific structures and definitions
111 *
112 */
38struct kvm_debug_exit_arch { 113struct kvm_debug_exit_arch {
114 __u64 epc;
39}; 115};
40 116
41/* for KVM_SET_GUEST_DEBUG */ 117/* for KVM_SET_GUEST_DEBUG */
42struct kvm_guest_debug_arch { 118struct kvm_guest_debug_arch {
43}; 119};
44 120
121/* definition of registers in kvm_run */
122struct kvm_sync_regs {
123};
124
125/* dummy definition */
126struct kvm_sregs {
127};
128
45struct kvm_mips_interrupt { 129struct kvm_mips_interrupt {
46 /* in */ 130 /* in */
47 __u32 cpu; 131 __u32 cpu;
48 __u32 irq; 132 __u32 irq;
49}; 133};
50 134
51/* definition of registers in kvm_run */
52struct kvm_sync_regs {
53};
54
55#endif /* __LINUX_KVM_MIPS_H */ 135#endif /* __LINUX_KVM_MIPS_H */
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index 4d58d8468705..b26f7e317279 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -22,16 +22,12 @@
22#define DSP_CONTROL 77 22#define DSP_CONTROL 77
23#define ACX 78 23#define ACX 78
24 24
25#ifndef __KERNEL__
25/* 26/*
26 * This struct defines the way the registers are stored on the stack during a 27 * This struct defines the way the registers are stored on the stack during a
27 * system call/exception. As usual the registers k0/k1 aren't being saved. 28 * system call/exception. As usual the registers k0/k1 aren't being saved.
28 */ 29 */
29struct pt_regs { 30struct pt_regs {
30#ifdef CONFIG_32BIT
31 /* Pad bytes for argument save space on the stack. */
32 unsigned long pad0[6];
33#endif
34
35 /* Saved main processor registers. */ 31 /* Saved main processor registers. */
36 unsigned long regs[32]; 32 unsigned long regs[32];
37 33
@@ -39,20 +35,11 @@ struct pt_regs {
39 unsigned long cp0_status; 35 unsigned long cp0_status;
40 unsigned long hi; 36 unsigned long hi;
41 unsigned long lo; 37 unsigned long lo;
42#ifdef CONFIG_CPU_HAS_SMARTMIPS
43 unsigned long acx;
44#endif
45 unsigned long cp0_badvaddr; 38 unsigned long cp0_badvaddr;
46 unsigned long cp0_cause; 39 unsigned long cp0_cause;
47 unsigned long cp0_epc; 40 unsigned long cp0_epc;
48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
54#endif
55} __attribute__ ((aligned (8))); 41} __attribute__ ((aligned (8)));
42#endif /* __KERNEL__ */
56 43
57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 44/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
58#define PTRACE_GETREGS 12 45#define PTRACE_GETREGS 12
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index e06f777e9c49..1188e00bb120 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -119,4 +119,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
119#undef TASK_SIZE 119#undef TASK_SIZE
120#define TASK_SIZE TASK_SIZE32 120#define TASK_SIZE TASK_SIZE32
121 121
122#undef cputime_to_timeval
123#define cputime_to_timeval cputime_to_compat_timeval
124static __inline__ void
125cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
126{
127 unsigned long jiffies = cputime_to_jiffies(cputime);
128
129 value->tv_usec = (jiffies % HZ) * (1000000L / HZ);
130 value->tv_sec = jiffies / HZ;
131}
132
122#include "../../../fs/binfmt_elf.c" 133#include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 97c5a1668e53..202e581e6096 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -162,4 +162,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
162#undef TASK_SIZE 162#undef TASK_SIZE
163#define TASK_SIZE TASK_SIZE32 163#define TASK_SIZE TASK_SIZE32
164 164
165#undef cputime_to_timeval
166#define cputime_to_timeval cputime_to_compat_timeval
167static __inline__ void
168cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
169{
170 unsigned long jiffies = cputime_to_jiffies(cputime);
171
172 value->tv_usec = (jiffies % HZ) * (1000000L / HZ);
173 value->tv_sec = jiffies / HZ;
174}
175
165#include "../../../fs/binfmt_elf.c" 176#include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
25#define MCOUNT_OFFSET_INSNS 4 25#define MCOUNT_OFFSET_INSNS 4
26#endif 26#endif
27 27
28#ifdef CONFIG_DYNAMIC_FTRACE
29
28/* Arch override because MIPS doesn't need to run this from stop_machine() */ 30/* Arch override because MIPS doesn't need to run this from stop_machine() */
29void arch_ftrace_update_code(int command) 31void arch_ftrace_update_code(int command)
30{ 32{
31 ftrace_modify_all_code(command); 33 ftrace_modify_all_code(command);
32} 34}
33 35
36#endif
37
34/* 38/*
35 * Check if the address is in kernel space 39 * Check if the address is in kernel space
36 * 40 *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
93} 93}
94 94
95/* 95/*
96 * The Au1xxx wait is available only if using 32khz counter or 96 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 * external timer source, but specifically not CP0 Counter. 97 * since coreclock (and the cp0 counter) stops upon executing it. Only an
98 * alchemy/common/time.c may override cpu_wait! 98 * interrupt can wake it, so they must be enabled before entering idle modes.
99 */ 99 */
100static void au1k_wait(void) 100static void au1k_wait(void)
101{ 101{
102 unsigned long c0status = read_c0_status() | 1; /* irqs on */
103
102 __asm__( 104 __asm__(
103 " .set mips3 \n" 105 " .set mips3 \n"
104 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n" 107 " cache 0x14, 32(%0) \n"
106 " sync \n" 108 " sync \n"
107 " nop \n" 109 " mtc0 %1, $12 \n" /* wr c0status */
108 " wait \n" 110 " wait \n"
109 " nop \n" 111 " nop \n"
110 " nop \n" 112 " nop \n"
111 " nop \n" 113 " nop \n"
112 " nop \n" 114 " nop \n"
113 " .set mips0 \n" 115 " .set mips0 \n"
114 : : "r" (au1k_wait)); 116 : : "r" (au1k_wait), "r" (c0status));
115 local_irq_enable();
116} 117}
117 118
118static int __initdata nowait; 119static int __initdata nowait;
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 93c070b41b0d..6fa198db8999 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -40,6 +40,7 @@
40#include <asm/processor.h> 40#include <asm/processor.h>
41#include <asm/vpe.h> 41#include <asm/vpe.h>
42#include <asm/rtlx.h> 42#include <asm/rtlx.h>
43#include <asm/setup.h>
43 44
44static struct rtlx_info *rtlx; 45static struct rtlx_info *rtlx;
45static int major; 46static int major;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e3be67012d78..a75ae40184aa 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -897,22 +897,24 @@ out_sigsegv:
897 897
898asmlinkage void do_tr(struct pt_regs *regs) 898asmlinkage void do_tr(struct pt_regs *regs)
899{ 899{
900 unsigned int opcode, tcode = 0; 900 u32 opcode, tcode = 0;
901 u16 instr[2]; 901 u16 instr[2];
902 unsigned long epc = exception_epc(regs); 902 unsigned long epc = msk_isa16_mode(exception_epc(regs));
903 903
904 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) || 904 if (get_isa16_mode(regs->cp0_epc)) {
905 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))) 905 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
906 __get_user(instr[1], (u16 __user *)(epc + 2)))
906 goto out_sigsegv; 907 goto out_sigsegv;
907 opcode = (instr[0] << 16) | instr[1]; 908 opcode = (instr[0] << 16) | instr[1];
908 909 /* Immediate versions don't provide a code. */
909 /* Immediate versions don't provide a code. */ 910 if (!(opcode & OPCODE))
910 if (!(opcode & OPCODE)) { 911 tcode = (opcode >> 12) & ((1 << 4) - 1);
911 if (get_isa16_mode(regs->cp0_epc)) 912 } else {
912 /* microMIPS */ 913 if (__get_user(opcode, (u32 __user *)epc))
913 tcode = (opcode >> 12) & 0x1f; 914 goto out_sigsegv;
914 else 915 /* Immediate versions don't provide a code. */
915 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 916 if (!(opcode & OPCODE))
917 tcode = (opcode >> 6) & ((1 << 10) - 1);
916 } 918 }
917 919
918 do_trap_or_bp(regs, tcode, "Trap"); 920 do_trap_or_bp(regs, tcode, "Trap");
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index e0dad0289797..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -195,7 +195,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
195long 195long
196kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 196kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
197{ 197{
198 return -EINVAL; 198 return -ENOIOCTLCMD;
199} 199}
200 200
201void kvm_arch_free_memslot(struct kvm_memory_slot *free, 201void kvm_arch_free_memslot(struct kvm_memory_slot *free,
@@ -401,7 +401,7 @@ int
401kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 401kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
402 struct kvm_guest_debug *dbg) 402 struct kvm_guest_debug *dbg)
403{ 403{
404 return -EINVAL; 404 return -ENOIOCTLCMD;
405} 405}
406 406
407int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 407int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
@@ -475,14 +475,248 @@ int
475kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 475kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
476 struct kvm_mp_state *mp_state) 476 struct kvm_mp_state *mp_state)
477{ 477{
478 return -EINVAL; 478 return -ENOIOCTLCMD;
479} 479}
480 480
481int 481int
482kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 482kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
483 struct kvm_mp_state *mp_state) 483 struct kvm_mp_state *mp_state)
484{ 484{
485 return -EINVAL; 485 return -ENOIOCTLCMD;
486}
487
488#define MIPS_CP0_32(_R, _S) \
489 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
490
491#define MIPS_CP0_64(_R, _S) \
492 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
493
494#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
495#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
496#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
497#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
498#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
499#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
500#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
501#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
502#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
503#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
504#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
505#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
506#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
507#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
508#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
509#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
510#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
511#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
512#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
513#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
514#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
515#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
516#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
517
518static u64 kvm_mips_get_one_regs[] = {
519 KVM_REG_MIPS_R0,
520 KVM_REG_MIPS_R1,
521 KVM_REG_MIPS_R2,
522 KVM_REG_MIPS_R3,
523 KVM_REG_MIPS_R4,
524 KVM_REG_MIPS_R5,
525 KVM_REG_MIPS_R6,
526 KVM_REG_MIPS_R7,
527 KVM_REG_MIPS_R8,
528 KVM_REG_MIPS_R9,
529 KVM_REG_MIPS_R10,
530 KVM_REG_MIPS_R11,
531 KVM_REG_MIPS_R12,
532 KVM_REG_MIPS_R13,
533 KVM_REG_MIPS_R14,
534 KVM_REG_MIPS_R15,
535 KVM_REG_MIPS_R16,
536 KVM_REG_MIPS_R17,
537 KVM_REG_MIPS_R18,
538 KVM_REG_MIPS_R19,
539 KVM_REG_MIPS_R20,
540 KVM_REG_MIPS_R21,
541 KVM_REG_MIPS_R22,
542 KVM_REG_MIPS_R23,
543 KVM_REG_MIPS_R24,
544 KVM_REG_MIPS_R25,
545 KVM_REG_MIPS_R26,
546 KVM_REG_MIPS_R27,
547 KVM_REG_MIPS_R28,
548 KVM_REG_MIPS_R29,
549 KVM_REG_MIPS_R30,
550 KVM_REG_MIPS_R31,
551
552 KVM_REG_MIPS_HI,
553 KVM_REG_MIPS_LO,
554 KVM_REG_MIPS_PC,
555
556 KVM_REG_MIPS_CP0_INDEX,
557 KVM_REG_MIPS_CP0_CONTEXT,
558 KVM_REG_MIPS_CP0_PAGEMASK,
559 KVM_REG_MIPS_CP0_WIRED,
560 KVM_REG_MIPS_CP0_BADVADDR,
561 KVM_REG_MIPS_CP0_ENTRYHI,
562 KVM_REG_MIPS_CP0_STATUS,
563 KVM_REG_MIPS_CP0_CAUSE,
564 /* EPC set via kvm_regs, et al. */
565 KVM_REG_MIPS_CP0_CONFIG,
566 KVM_REG_MIPS_CP0_CONFIG1,
567 KVM_REG_MIPS_CP0_CONFIG2,
568 KVM_REG_MIPS_CP0_CONFIG3,
569 KVM_REG_MIPS_CP0_CONFIG7,
570 KVM_REG_MIPS_CP0_ERROREPC
571};
572
573static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
574 const struct kvm_one_reg *reg)
575{
576 struct mips_coproc *cop0 = vcpu->arch.cop0;
577 s64 v;
578
579 switch (reg->id) {
580 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
581 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
582 break;
583 case KVM_REG_MIPS_HI:
584 v = (long)vcpu->arch.hi;
585 break;
586 case KVM_REG_MIPS_LO:
587 v = (long)vcpu->arch.lo;
588 break;
589 case KVM_REG_MIPS_PC:
590 v = (long)vcpu->arch.pc;
591 break;
592
593 case KVM_REG_MIPS_CP0_INDEX:
594 v = (long)kvm_read_c0_guest_index(cop0);
595 break;
596 case KVM_REG_MIPS_CP0_CONTEXT:
597 v = (long)kvm_read_c0_guest_context(cop0);
598 break;
599 case KVM_REG_MIPS_CP0_PAGEMASK:
600 v = (long)kvm_read_c0_guest_pagemask(cop0);
601 break;
602 case KVM_REG_MIPS_CP0_WIRED:
603 v = (long)kvm_read_c0_guest_wired(cop0);
604 break;
605 case KVM_REG_MIPS_CP0_BADVADDR:
606 v = (long)kvm_read_c0_guest_badvaddr(cop0);
607 break;
608 case KVM_REG_MIPS_CP0_ENTRYHI:
609 v = (long)kvm_read_c0_guest_entryhi(cop0);
610 break;
611 case KVM_REG_MIPS_CP0_STATUS:
612 v = (long)kvm_read_c0_guest_status(cop0);
613 break;
614 case KVM_REG_MIPS_CP0_CAUSE:
615 v = (long)kvm_read_c0_guest_cause(cop0);
616 break;
617 case KVM_REG_MIPS_CP0_ERROREPC:
618 v = (long)kvm_read_c0_guest_errorepc(cop0);
619 break;
620 case KVM_REG_MIPS_CP0_CONFIG:
621 v = (long)kvm_read_c0_guest_config(cop0);
622 break;
623 case KVM_REG_MIPS_CP0_CONFIG1:
624 v = (long)kvm_read_c0_guest_config1(cop0);
625 break;
626 case KVM_REG_MIPS_CP0_CONFIG2:
627 v = (long)kvm_read_c0_guest_config2(cop0);
628 break;
629 case KVM_REG_MIPS_CP0_CONFIG3:
630 v = (long)kvm_read_c0_guest_config3(cop0);
631 break;
632 case KVM_REG_MIPS_CP0_CONFIG7:
633 v = (long)kvm_read_c0_guest_config7(cop0);
634 break;
635 default:
636 return -EINVAL;
637 }
638 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
639 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
640 return put_user(v, uaddr64);
641 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
642 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
643 u32 v32 = (u32)v;
644 return put_user(v32, uaddr32);
645 } else {
646 return -EINVAL;
647 }
648}
649
650static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
651 const struct kvm_one_reg *reg)
652{
653 struct mips_coproc *cop0 = vcpu->arch.cop0;
654 u64 v;
655
656 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
657 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
658
659 if (get_user(v, uaddr64) != 0)
660 return -EFAULT;
661 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
662 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
663 s32 v32;
664
665 if (get_user(v32, uaddr32) != 0)
666 return -EFAULT;
667 v = (s64)v32;
668 } else {
669 return -EINVAL;
670 }
671
672 switch (reg->id) {
673 case KVM_REG_MIPS_R0:
674 /* Silently ignore requests to set $0 */
675 break;
676 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
677 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
678 break;
679 case KVM_REG_MIPS_HI:
680 vcpu->arch.hi = v;
681 break;
682 case KVM_REG_MIPS_LO:
683 vcpu->arch.lo = v;
684 break;
685 case KVM_REG_MIPS_PC:
686 vcpu->arch.pc = v;
687 break;
688
689 case KVM_REG_MIPS_CP0_INDEX:
690 kvm_write_c0_guest_index(cop0, v);
691 break;
692 case KVM_REG_MIPS_CP0_CONTEXT:
693 kvm_write_c0_guest_context(cop0, v);
694 break;
695 case KVM_REG_MIPS_CP0_PAGEMASK:
696 kvm_write_c0_guest_pagemask(cop0, v);
697 break;
698 case KVM_REG_MIPS_CP0_WIRED:
699 kvm_write_c0_guest_wired(cop0, v);
700 break;
701 case KVM_REG_MIPS_CP0_BADVADDR:
702 kvm_write_c0_guest_badvaddr(cop0, v);
703 break;
704 case KVM_REG_MIPS_CP0_ENTRYHI:
705 kvm_write_c0_guest_entryhi(cop0, v);
706 break;
707 case KVM_REG_MIPS_CP0_STATUS:
708 kvm_write_c0_guest_status(cop0, v);
709 break;
710 case KVM_REG_MIPS_CP0_CAUSE:
711 kvm_write_c0_guest_cause(cop0, v);
712 break;
713 case KVM_REG_MIPS_CP0_ERROREPC:
714 kvm_write_c0_guest_errorepc(cop0, v);
715 break;
716 default:
717 return -EINVAL;
718 }
719 return 0;
486} 720}
487 721
488long 722long
@@ -491,9 +725,38 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
491 struct kvm_vcpu *vcpu = filp->private_data; 725 struct kvm_vcpu *vcpu = filp->private_data;
492 void __user *argp = (void __user *)arg; 726 void __user *argp = (void __user *)arg;
493 long r; 727 long r;
494 int intr;
495 728
496 switch (ioctl) { 729 switch (ioctl) {
730 case KVM_SET_ONE_REG:
731 case KVM_GET_ONE_REG: {
732 struct kvm_one_reg reg;
733 if (copy_from_user(&reg, argp, sizeof(reg)))
734 return -EFAULT;
735 if (ioctl == KVM_SET_ONE_REG)
736 return kvm_mips_set_reg(vcpu, &reg);
737 else
738 return kvm_mips_get_reg(vcpu, &reg);
739 }
740 case KVM_GET_REG_LIST: {
741 struct kvm_reg_list __user *user_list = argp;
742 u64 __user *reg_dest;
743 struct kvm_reg_list reg_list;
744 unsigned n;
745
746 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
747 return -EFAULT;
748 n = reg_list.n;
749 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
750 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
751 return -EFAULT;
752 if (n < reg_list.n)
753 return -E2BIG;
754 reg_dest = user_list->reg;
755 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
756 sizeof(kvm_mips_get_one_regs)))
757 return -EFAULT;
758 return 0;
759 }
497 case KVM_NMI: 760 case KVM_NMI:
498 /* Treat the NMI as a CPU reset */ 761 /* Treat the NMI as a CPU reset */
499 r = kvm_mips_reset_vcpu(vcpu); 762 r = kvm_mips_reset_vcpu(vcpu);
@@ -505,8 +768,6 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
505 if (copy_from_user(&irq, argp, sizeof(irq))) 768 if (copy_from_user(&irq, argp, sizeof(irq)))
506 goto out; 769 goto out;
507 770
508 intr = (int)irq.irq;
509
510 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 771 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
511 irq.irq); 772 irq.irq);
512 773
@@ -514,7 +775,7 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
514 break; 775 break;
515 } 776 }
516 default: 777 default:
517 r = -EINVAL; 778 r = -ENOIOCTLCMD;
518 } 779 }
519 780
520out: 781out:
@@ -565,7 +826,7 @@ long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
565 826
566 switch (ioctl) { 827 switch (ioctl) {
567 default: 828 default:
568 r = -EINVAL; 829 r = -ENOIOCTLCMD;
569 } 830 }
570 831
571 return r; 832 return r;
@@ -593,13 +854,13 @@ void kvm_arch_exit(void)
593int 854int
594kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 855kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
595{ 856{
596 return -ENOTSUPP; 857 return -ENOIOCTLCMD;
597} 858}
598 859
599int 860int
600kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 861kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
601{ 862{
602 return -ENOTSUPP; 863 return -ENOIOCTLCMD;
603} 864}
604 865
605int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 866int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
@@ -609,12 +870,12 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
609 870
610int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 871int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
611{ 872{
612 return -ENOTSUPP; 873 return -ENOIOCTLCMD;
613} 874}
614 875
615int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 876int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
616{ 877{
617 return -ENOTSUPP; 878 return -ENOIOCTLCMD;
618} 879}
619 880
620int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 881int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
@@ -627,6 +888,9 @@ int kvm_dev_ioctl_check_extension(long ext)
627 int r; 888 int r;
628 889
629 switch (ext) { 890 switch (ext) {
891 case KVM_CAP_ONE_REG:
892 r = 1;
893 break;
630 case KVM_CAP_COALESCED_MMIO: 894 case KVM_CAP_COALESCED_MMIO:
631 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 895 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
632 break; 896 break;
@@ -635,7 +899,6 @@ int kvm_dev_ioctl_check_extension(long ext)
635 break; 899 break;
636 } 900 }
637 return r; 901 return r;
638
639} 902}
640 903
641int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 904int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
@@ -677,28 +940,28 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
677{ 940{
678 int i; 941 int i;
679 942
680 for (i = 0; i < 32; i++) 943 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
681 vcpu->arch.gprs[i] = regs->gprs[i]; 944 vcpu->arch.gprs[i] = regs->gpr[i];
682 945 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
683 vcpu->arch.hi = regs->hi; 946 vcpu->arch.hi = regs->hi;
684 vcpu->arch.lo = regs->lo; 947 vcpu->arch.lo = regs->lo;
685 vcpu->arch.pc = regs->pc; 948 vcpu->arch.pc = regs->pc;
686 949
687 return kvm_mips_callbacks->vcpu_ioctl_set_regs(vcpu, regs); 950 return 0;
688} 951}
689 952
690int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 953int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
691{ 954{
692 int i; 955 int i;
693 956
694 for (i = 0; i < 32; i++) 957 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
695 regs->gprs[i] = vcpu->arch.gprs[i]; 958 regs->gpr[i] = vcpu->arch.gprs[i];
696 959
697 regs->hi = vcpu->arch.hi; 960 regs->hi = vcpu->arch.hi;
698 regs->lo = vcpu->arch.lo; 961 regs->lo = vcpu->arch.lo;
699 regs->pc = vcpu->arch.pc; 962 regs->pc = vcpu->arch.pc;
700 963
701 return kvm_mips_callbacks->vcpu_ioctl_get_regs(vcpu, regs); 964 return 0;
702} 965}
703 966
704void kvm_mips_comparecount_func(unsigned long data) 967void kvm_mips_comparecount_func(unsigned long data)
diff --git a/arch/mips/kvm/kvm_trap_emul.c b/arch/mips/kvm/kvm_trap_emul.c
index 466aeef044bd..30d725321db1 100644
--- a/arch/mips/kvm/kvm_trap_emul.c
+++ b/arch/mips/kvm/kvm_trap_emul.c
@@ -345,54 +345,6 @@ static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu)
345 return ret; 345 return ret;
346} 346}
347 347
348static int
349kvm_trap_emul_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
350{
351 struct mips_coproc *cop0 = vcpu->arch.cop0;
352
353 kvm_write_c0_guest_index(cop0, regs->cp0reg[MIPS_CP0_TLB_INDEX][0]);
354 kvm_write_c0_guest_context(cop0, regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0]);
355 kvm_write_c0_guest_badvaddr(cop0, regs->cp0reg[MIPS_CP0_BAD_VADDR][0]);
356 kvm_write_c0_guest_entryhi(cop0, regs->cp0reg[MIPS_CP0_TLB_HI][0]);
357 kvm_write_c0_guest_epc(cop0, regs->cp0reg[MIPS_CP0_EXC_PC][0]);
358
359 kvm_write_c0_guest_status(cop0, regs->cp0reg[MIPS_CP0_STATUS][0]);
360 kvm_write_c0_guest_cause(cop0, regs->cp0reg[MIPS_CP0_CAUSE][0]);
361 kvm_write_c0_guest_pagemask(cop0,
362 regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0]);
363 kvm_write_c0_guest_wired(cop0, regs->cp0reg[MIPS_CP0_TLB_WIRED][0]);
364 kvm_write_c0_guest_errorepc(cop0, regs->cp0reg[MIPS_CP0_ERROR_PC][0]);
365
366 return 0;
367}
368
369static int
370kvm_trap_emul_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
371{
372 struct mips_coproc *cop0 = vcpu->arch.cop0;
373
374 regs->cp0reg[MIPS_CP0_TLB_INDEX][0] = kvm_read_c0_guest_index(cop0);
375 regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0] = kvm_read_c0_guest_context(cop0);
376 regs->cp0reg[MIPS_CP0_BAD_VADDR][0] = kvm_read_c0_guest_badvaddr(cop0);
377 regs->cp0reg[MIPS_CP0_TLB_HI][0] = kvm_read_c0_guest_entryhi(cop0);
378 regs->cp0reg[MIPS_CP0_EXC_PC][0] = kvm_read_c0_guest_epc(cop0);
379
380 regs->cp0reg[MIPS_CP0_STATUS][0] = kvm_read_c0_guest_status(cop0);
381 regs->cp0reg[MIPS_CP0_CAUSE][0] = kvm_read_c0_guest_cause(cop0);
382 regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0] =
383 kvm_read_c0_guest_pagemask(cop0);
384 regs->cp0reg[MIPS_CP0_TLB_WIRED][0] = kvm_read_c0_guest_wired(cop0);
385 regs->cp0reg[MIPS_CP0_ERROR_PC][0] = kvm_read_c0_guest_errorepc(cop0);
386
387 regs->cp0reg[MIPS_CP0_CONFIG][0] = kvm_read_c0_guest_config(cop0);
388 regs->cp0reg[MIPS_CP0_CONFIG][1] = kvm_read_c0_guest_config1(cop0);
389 regs->cp0reg[MIPS_CP0_CONFIG][2] = kvm_read_c0_guest_config2(cop0);
390 regs->cp0reg[MIPS_CP0_CONFIG][3] = kvm_read_c0_guest_config3(cop0);
391 regs->cp0reg[MIPS_CP0_CONFIG][7] = kvm_read_c0_guest_config7(cop0);
392
393 return 0;
394}
395
396static int kvm_trap_emul_vm_init(struct kvm *kvm) 348static int kvm_trap_emul_vm_init(struct kvm *kvm)
397{ 349{
398 return 0; 350 return 0;
@@ -471,8 +423,6 @@ static struct kvm_mips_callbacks kvm_trap_emul_callbacks = {
471 .dequeue_io_int = kvm_mips_dequeue_io_int_cb, 423 .dequeue_io_int = kvm_mips_dequeue_io_int_cb,
472 .irq_deliver = kvm_mips_irq_deliver_cb, 424 .irq_deliver = kvm_mips_irq_deliver_cb,
473 .irq_clear = kvm_mips_irq_clear_cb, 425 .irq_clear = kvm_mips_irq_clear_cb,
474 .vcpu_ioctl_get_regs = kvm_trap_emul_ioctl_get_regs,
475 .vcpu_ioctl_set_regs = kvm_trap_emul_ioctl_set_regs,
476}; 426};
477 427
478int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks) 428int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ce9818eef7d3..afeef93f81a7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -301,10 +301,6 @@ static u32 tlb_handler[128] __cpuinitdata;
301static struct uasm_label labels[128] __cpuinitdata; 301static struct uasm_label labels[128] __cpuinitdata;
302static struct uasm_reloc relocs[128] __cpuinitdata; 302static struct uasm_reloc relocs[128] __cpuinitdata;
303 303
304#ifdef CONFIG_64BIT
305static int check_for_high_segbits __cpuinitdata;
306#endif
307
308static int check_for_high_segbits __cpuinitdata; 304static int check_for_high_segbits __cpuinitdata;
309 305
310static unsigned int kscratch_used_mask __cpuinitdata; 306static unsigned int kscratch_used_mask __cpuinitdata;
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index fb1569580def..6b5f3406f414 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -88,7 +88,7 @@ void __init plat_mem_setup(void)
88 __dt_setup_arch(&__dtb_start); 88 __dt_setup_arch(&__dtb_start);
89 89
90 if (soc_info.mem_size) 90 if (soc_info.mem_size)
91 add_memory_region(soc_info.mem_base, soc_info.mem_size, 91 add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
92 BOOT_MEM_RAM); 92 BOOT_MEM_RAM);
93 else 93 else
94 detect_memory_region(soc_info.mem_base, 94 detect_memory_region(soc_info.mem_base,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 06:30:13 -0500