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authorPaul Gortmaker <paul.gortmaker@windriver.com>2013-06-18 13:01:10 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-07-01 09:10:53 -0400
commit169c3c164f0dd791dfa023ab02c12cb286a72e6e (patch)
treece6c3e9942658c8bd32d7a5c7b1ecc7a0543d64a /arch/mips
parent5a772eee5544f4f84139868f7cd05806b805610d (diff)
MIPS: Delete Wind River ppmc eval board support.
This board has been EOL for many years now; lets not burden people doing build coverage and other tree wide work with working on essentially dead files. [ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Patchwork: http://patchwork.linux-mips.org/patch/5503/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig23
-rw-r--r--arch/mips/configs/wrppmc_defconfig97
-rw-r--r--arch/mips/include/asm/mach-wrppmc/mach-gt64120.h83
-rw-r--r--arch/mips/include/asm/mach-wrppmc/war.h24
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-wrppmc.c37
-rw-r--r--arch/mips/wrppmc/Makefile12
-rw-r--r--arch/mips/wrppmc/Platform7
-rw-r--r--arch/mips/wrppmc/irq.c56
-rw-r--r--arch/mips/wrppmc/pci.c52
-rw-r--r--arch/mips/wrppmc/reset.c41
-rw-r--r--arch/mips/wrppmc/serial.c80
-rw-r--r--arch/mips/wrppmc/setup.c128
-rw-r--r--arch/mips/wrppmc/time.c39
15 files changed, 0 insertions, 681 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 4b597d91a8d5..d9d81c219253 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -30,7 +30,6 @@ platforms += sibyte
30platforms += sni 30platforms += sni
31platforms += txx9 31platforms += txx9
32platforms += vr41xx 32platforms += vr41xx
33platforms += wrppmc
34 33
35# include the platform specific files 34# include the platform specific files
36include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms)) 35include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 26779ccae116..f4cc348034b7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -712,29 +712,6 @@ config MIKROTIK_RB532
712 Support the Mikrotik(tm) RouterBoard 532 series, 712 Support the Mikrotik(tm) RouterBoard 532 series,
713 based on the IDT RC32434 SoC. 713 based on the IDT RC32434 SoC.
714 714
715config WR_PPMC
716 bool "Wind River PPMC board"
717 select CEVT_R4K
718 select CSRC_R4K
719 select IRQ_CPU
720 select BOOT_ELF32
721 select DMA_NONCOHERENT
722 select HW_HAS_PCI
723 select PCI_GT64XXX_PCI0
724 select SWAP_IO_SPACE
725 select SYS_HAS_CPU_MIPS32_R1
726 select SYS_HAS_CPU_MIPS32_R2
727 select SYS_HAS_CPU_MIPS64_R1
728 select SYS_HAS_CPU_NEVADA
729 select SYS_HAS_CPU_RM7000
730 select SYS_SUPPORTS_32BIT_KERNEL
731 select SYS_SUPPORTS_64BIT_KERNEL
732 select SYS_SUPPORTS_BIG_ENDIAN
733 select SYS_SUPPORTS_LITTLE_ENDIAN
734 help
735 This enables support for the Wind River MIPS32 4KC PPMC evaluation
736 board, which is based on GT64120 bridge chip.
737
738config CAVIUM_OCTEON_SOC 715config CAVIUM_OCTEON_SOC
739 bool "Cavium Networks Octeon SoC based boards" 716 bool "Cavium Networks Octeon SoC based boards"
740 select CEVT_R4K 717 select CEVT_R4K
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
deleted file mode 100644
index 44a451be359e..000000000000
--- a/arch/mips/configs/wrppmc_defconfig
+++ /dev/null
@@ -1,97 +0,0 @@
1CONFIG_WR_PPMC=y
2CONFIG_HZ_1000=y
3CONFIG_EXPERIMENTAL=y
4# CONFIG_SWAP is not set
5CONFIG_SYSVIPC=y
6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_BLK_DEV_INITRD=y
9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10CONFIG_EXPERT=y
11CONFIG_KALLSYMS_EXTRA_PASS=y
12# CONFIG_EPOLL is not set
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODVERSIONS=y
17CONFIG_MODULE_SRCVERSION_ALL=y
18CONFIG_PCI=y
19CONFIG_HOTPLUG_PCI=y
20CONFIG_BINFMT_MISC=y
21CONFIG_PM=y
22CONFIG_NET=y
23CONFIG_PACKET=y
24CONFIG_UNIX=y
25CONFIG_XFRM_MIGRATE=y
26CONFIG_INET=y
27CONFIG_IP_MULTICAST=y
28CONFIG_IP_PNP=y
29CONFIG_IP_PNP_DHCP=y
30CONFIG_IP_PNP_BOOTP=y
31CONFIG_IP_PNP_RARP=y
32CONFIG_IP_MROUTE=y
33CONFIG_ARPD=y
34CONFIG_INET_XFRM_MODE_TRANSPORT=m
35CONFIG_INET_XFRM_MODE_TUNNEL=m
36CONFIG_INET_XFRM_MODE_BEET=m
37CONFIG_TCP_MD5SIG=y
38# CONFIG_IPV6 is not set
39CONFIG_NETWORK_SECMARK=y
40CONFIG_FW_LOADER=m
41CONFIG_BLK_DEV_RAM=y
42CONFIG_SGI_IOC4=m
43CONFIG_NETDEVICES=y
44CONFIG_PHYLIB=y
45CONFIG_VITESSE_PHY=m
46CONFIG_SMSC_PHY=m
47CONFIG_NET_ETHERNET=y
48CONFIG_NET_PCI=y
49CONFIG_E100=y
50CONFIG_QLA3XXX=m
51CONFIG_CHELSIO_T3=m
52CONFIG_NETXEN_NIC=m
53# CONFIG_INPUT is not set
54# CONFIG_SERIO is not set
55# CONFIG_VT is not set
56CONFIG_SERIAL_8250=y
57CONFIG_SERIAL_8250_CONSOLE=y
58CONFIG_SERIAL_8250_NR_UARTS=1
59CONFIG_SERIAL_8250_RUNTIME_UARTS=1
60# CONFIG_HW_RANDOM is not set
61CONFIG_PROC_KCORE=y
62CONFIG_TMPFS=y
63CONFIG_TMPFS_POSIX_ACL=y
64CONFIG_NFS_FS=y
65CONFIG_NFS_V3=y
66CONFIG_ROOT_NFS=y
67CONFIG_DLM=m
68CONFIG_CMDLINE_BOOL=y
69CONFIG_CMDLINE="console=ttyS0,115200n8"
70CONFIG_CRYPTO_NULL=m
71CONFIG_CRYPTO_CBC=m
72CONFIG_CRYPTO_ECB=m
73CONFIG_CRYPTO_LRW=m
74CONFIG_CRYPTO_PCBC=m
75CONFIG_CRYPTO_XCBC=m
76CONFIG_CRYPTO_MD4=m
77CONFIG_CRYPTO_MICHAEL_MIC=m
78CONFIG_CRYPTO_SHA256=m
79CONFIG_CRYPTO_SHA512=m
80CONFIG_CRYPTO_TGR192=m
81CONFIG_CRYPTO_WP512=m
82CONFIG_CRYPTO_ANUBIS=m
83CONFIG_CRYPTO_ARC4=m
84CONFIG_CRYPTO_BLOWFISH=m
85CONFIG_CRYPTO_CAMELLIA=m
86CONFIG_CRYPTO_CAST5=m
87CONFIG_CRYPTO_CAST6=m
88CONFIG_CRYPTO_DES=m
89CONFIG_CRYPTO_FCRYPT=m
90CONFIG_CRYPTO_KHAZAD=m
91CONFIG_CRYPTO_SERPENT=m
92CONFIG_CRYPTO_TEA=m
93CONFIG_CRYPTO_TWOFISH=m
94CONFIG_CRYPTO_DEFLATE=m
95CONFIG_CRC_CCITT=y
96CONFIG_CRC16=y
97CONFIG_LIBCRC32C=y
diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
deleted file mode 100644
index 00fa3684ac98..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef __ASM_MIPS_GT64120_H
9#define __ASM_MIPS_GT64120_H
10
11/*
12 * This is the CPU physical memory map of PPMC Board:
13 *
14 * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
15 * 0x1C000000-0x1C000000 - LED (CS0)
16 * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
17 * 0x1F000000-0x1F000000 - MailBox (CS3)
18 * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
19 */
20
21#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
22#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
23
24#define WRPPMC_UART16550_BASE 0x1C800000
25#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
26
27#define WRPPMC_LED_BASE 0x1C000000
28#define WRPPMC_MBOX_BASE 0x1F000000
29
30#define WRPPMC_BOOTROM_BASE 0x1FC00000
31#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
32
33#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
34#define WRPPMC_UART16550_IRQ 6
35#define WRPPMC_PCI_INTA_IRQ 3
36
37/*
38 * PCI Bus I/O and Memory resources allocation
39 *
40 * NOTE: We only have PCI_0 hose interface
41 */
42#define GT_PCI_MEM_BASE 0x13000000UL
43#define GT_PCI_MEM_SIZE 0x02000000UL
44#define GT_PCI_IO_BASE 0x11000000UL
45#define GT_PCI_IO_SIZE 0x02000000UL
46
47/*
48 * PCI interrupts will come in on either the INTA or INTD interrupt lines,
49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
50 * boards, they all either come in on IntD or they all come in on IntA, they
51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
52 * "requested" interrupt numbers and go through the list whenever we get an
53 * IntA/D.
54 *
55 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
56 * INTD is 11.
57 */
58#define GT_TIMER 4
59#define GT_INTA 2
60#define GT_INTD 5
61
62#ifndef __ASSEMBLY__
63
64/*
65 * GT64120 internal register space base address
66 */
67extern unsigned long gt64120_base;
68
69#define GT64120_BASE (gt64120_base)
70
71/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
72#undef WRPPMC_EARLY_DEBUG
73
74#ifdef WRPPMC_EARLY_DEBUG
75extern void wrppmc_led_on(int mask);
76extern void wrppmc_led_off(int mask);
77extern void wrppmc_early_printk(const char *fmt, ...);
78#else
79#define wrppmc_early_printk(fmt, ...) do {} while (0)
80#endif /* WRPPMC_EARLY_DEBUG */
81
82#endif /* __ASSEMBLY__ */
83#endif /* __ASM_MIPS_GT64120_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
deleted file mode 100644
index e86084c0bd6b..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
9#define __ASM_MIPS_MACH_WRPPMC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 1
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index fa3bcd233138..b56fbc06c60e 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
52obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o 52obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
53obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 53obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 55obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o 56obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
58obj-$(CONFIG_CPU_XLR) += pci-xlr.o 57obj-$(CONFIG_CPU_XLR) += pci-xlr.o
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
deleted file mode 100644
index 29737edd121f..000000000000
--- a/arch/mips/pci/fixup-wrppmc.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * fixup-wrppmc.c: PPMC board specific PCI fixup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
9 */
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <asm/gt64120.h>
13
14/* PCI interrupt pins */
15#define PCI_INTA 1
16#define PCI_INTB 2
17#define PCI_INTC 3
18#define PCI_INTD 4
19
20#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
21
22static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
23 /* 0 INTA INTB INTC INTD */
24 [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
26};
27
28int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
29{
30 return pci_irq_tab[slot][pin];
31}
32
33/* Do platform specific device initialization at pci_enable_device() time */
34int pcibios_plat_dev_init(struct pci_dev *dev)
35{
36 return 0;
37}
diff --git a/arch/mips/wrppmc/Makefile b/arch/mips/wrppmc/Makefile
deleted file mode 100644
index 307cc6920ce6..000000000000
--- a/arch/mips/wrppmc/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License. See the file "COPYING" in the main directory of this archive
4# for more details.
5#
6# Copyright 2006 Wind River System, Inc.
7# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
8#
9# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
10#
11
12obj-y += irq.o pci.o reset.o serial.o setup.o time.o
diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
deleted file mode 100644
index dc78b25b95fe..000000000000
--- a/arch/mips/wrppmc/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Wind River PPMC Board (4KC + GT64120)
3#
4platform-$(CONFIG_WR_PPMC) += wrppmc/
5cflags-$(CONFIG_WR_PPMC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-wrppmc
7load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
diff --git a/arch/mips/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
deleted file mode 100644
index f237bf4d5c3a..000000000000
--- a/arch/mips/wrppmc/irq.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * irq.c: GT64120 Interrupt Controller
3 *
4 * Copyright (C) 2006, Wind River System Inc.
5 * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/hardirq.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15
16#include <asm/gt64120.h>
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
19
20asmlinkage void plat_irq_dispatch(void)
21{
22 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
23
24 if (pending & STATUSF_IP7)
25 do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
26 else if (pending & STATUSF_IP6)
27 do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
28 else if (pending & STATUSF_IP3)
29 do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
30 else
31 spurious_interrupt();
32}
33
34/**
35 * Initialize GT64120 Interrupt Controller
36 */
37void gt64120_init_pic(void)
38{
39 /* clear CPU Interrupt Cause Registers */
40 GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
41 GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
42
43 /* Disable all interrupts from GT64120 bridge chip */
44 GT_WRITE(GT_INTRMASK_OFS, 0x00);
45 GT_WRITE(GT_HINTRMASK_OFS, 0x00);
46 GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
47 GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
48}
49
50void __init arch_init_irq(void)
51{
52 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
53 mips_cpu_irq_init();
54
55 gt64120_init_pic();
56}
diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
deleted file mode 100644
index 8b8a0e1a40ca..000000000000
--- a/arch/mips/wrppmc/pci.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * pci.c: GT64120 PCI support.
3 *
4 * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/ioport.h>
12#include <linux/types.h>
13#include <linux/pci.h>
14
15#include <asm/gt64120.h>
16
17extern struct pci_ops gt64xxx_pci0_ops;
18
19static struct resource pci0_io_resource = {
20 .name = "pci_0 io",
21 .start = GT_PCI_IO_BASE,
22 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
23 .flags = IORESOURCE_IO,
24};
25
26static struct resource pci0_mem_resource = {
27 .name = "pci_0 memory",
28 .start = GT_PCI_MEM_BASE,
29 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
30 .flags = IORESOURCE_MEM,
31};
32
33static struct pci_controller hose_0 = {
34 .pci_ops = &gt64xxx_pci0_ops,
35 .io_resource = &pci0_io_resource,
36 .mem_resource = &pci0_mem_resource,
37};
38
39static int __init gt64120_pci_init(void)
40{
41 (void) GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
42 (void) GT_READ(GT_PCI0_BARE_OFS);
43
44 /* reset the whole PCI I/O space range */
45 ioport_resource.start = GT_PCI_IO_BASE;
46 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
47
48 register_pci_controller(&hose_0);
49 return 0;
50}
51
52arch_initcall(gt64120_pci_init);
diff --git a/arch/mips/wrppmc/reset.c b/arch/mips/wrppmc/reset.c
deleted file mode 100644
index 80beb188ed47..000000000000
--- a/arch/mips/wrppmc/reset.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/irqflags.h>
9#include <linux/kernel.h>
10
11#include <asm/cacheflush.h>
12#include <asm/idle.h>
13#include <asm/mipsregs.h>
14#include <asm/processor.h>
15
16void wrppmc_machine_restart(char *command)
17{
18 /*
19 * Ouch, we're still alive ... This time we take the silver bullet ...
20 * ... and find that we leave the hardware in a state in which the
21 * kernel in the flush locks up somewhen during of after the PCI
22 * detection stuff.
23 */
24 local_irq_disable();
25 set_c0_status(ST0_BEV | ST0_ERL);
26 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
27 flush_cache_all();
28 write_c0_wired(0);
29 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
30}
31
32void wrppmc_machine_halt(void)
33{
34 local_irq_disable();
35
36 printk(KERN_NOTICE "You can safely turn off the power\n");
37 while (1) {
38 if (cpu_wait)
39 cpu_wait();
40 }
41}
diff --git a/arch/mips/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
deleted file mode 100644
index 83f0f7d05187..000000000000
--- a/arch/mips/wrppmc/serial.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Registration of WRPPMC UART platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/gt64120.h>
27
28static struct resource wrppmc_uart_resource[] __initdata = {
29 {
30 .start = WRPPMC_UART16550_BASE,
31 .end = WRPPMC_UART16550_BASE + 7,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = WRPPMC_UART16550_IRQ,
36 .end = WRPPMC_UART16550_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct plat_serial8250_port wrppmc_serial8250_port[] = {
42 {
43 .irq = WRPPMC_UART16550_IRQ,
44 .uartclk = WRPPMC_UART16550_CLOCK,
45 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_SKIP_TEST,
47 .mapbase = WRPPMC_UART16550_BASE,
48 },
49 {},
50};
51
52static __init int wrppmc_uart_add(void)
53{
54 struct platform_device *pdev;
55 int retval;
56
57 pdev = platform_device_alloc("serial8250", -1);
58 if (!pdev)
59 return -ENOMEM;
60
61 pdev->id = PLAT8250_DEV_PLATFORM;
62 pdev->dev.platform_data = wrppmc_serial8250_port;
63
64 retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
65 ARRAY_SIZE(wrppmc_uart_resource));
66 if (retval)
67 goto err_free_device;
68
69 retval = platform_device_add(pdev);
70 if (retval)
71 goto err_free_device;
72
73 return 0;
74
75err_free_device:
76 platform_device_put(pdev);
77
78 return retval;
79}
80device_initcall(wrppmc_uart_add);
diff --git a/arch/mips/wrppmc/setup.c b/arch/mips/wrppmc/setup.c
deleted file mode 100644
index ca65c84031a7..000000000000
--- a/arch/mips/wrppmc/setup.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * setup.c: Setup pointers to hardware dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
10 */
11#include <linux/init.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/pm.h>
15
16#include <asm/io.h>
17#include <asm/bootinfo.h>
18#include <asm/reboot.h>
19#include <asm/time.h>
20#include <asm/gt64120.h>
21
22unsigned long gt64120_base = KSEG1ADDR(0x14000000);
23
24#ifdef WRPPMC_EARLY_DEBUG
25
26static volatile unsigned char * wrppmc_led = \
27 (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
28
29/*
30 * PPMC LED control register:
31 * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
32 * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
33 * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
34 */
35void wrppmc_led_on(int mask)
36{
37 unsigned char value = *wrppmc_led;
38
39 value &= (0xF8 | mask);
40 *wrppmc_led = value;
41}
42
43/* If mask = 0, turn off all LEDs */
44void wrppmc_led_off(int mask)
45{
46 unsigned char value = *wrppmc_led;
47
48 value |= (0x7 & mask);
49 *wrppmc_led = value;
50}
51
52/*
53 * We assume that bootloader has initialized UART16550 correctly
54 */
55void __init wrppmc_early_putc(char ch)
56{
57 static volatile unsigned char *wrppmc_uart = \
58 (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
59 unsigned char value;
60
61 /* Wait until Transmit-Holding-Register is empty */
62 while (1) {
63 value = *(wrppmc_uart + 5);
64 if (value & 0x20)
65 break;
66 }
67
68 *wrppmc_uart = ch;
69}
70
71void __init wrppmc_early_printk(const char *fmt, ...)
72{
73 static char pbuf[256] = {'\0', };
74 char *ch = pbuf;
75 va_list args;
76 unsigned int i;
77
78 memset(pbuf, 0, 256);
79 va_start(args, fmt);
80 i = vsprintf(pbuf, fmt, args);
81 va_end(args);
82
83 /* Print the string */
84 while (*ch != '\0') {
85 wrppmc_early_putc(*ch);
86 /* if print '\n', also print '\r' */
87 if (*ch++ == '\n')
88 wrppmc_early_putc('\r');
89 }
90}
91#endif /* WRPPMC_EARLY_DEBUG */
92
93void __init prom_free_prom_memory(void)
94{
95}
96
97void __init plat_mem_setup(void)
98{
99 extern void wrppmc_machine_restart(char *command);
100 extern void wrppmc_machine_halt(void);
101
102 _machine_restart = wrppmc_machine_restart;
103 _machine_halt = wrppmc_machine_halt;
104 pm_power_off = wrppmc_machine_halt;
105
106 /* This makes the operations of 'in/out[bwl]' to the
107 * physical address ( < KSEG0) can work via KSEG1
108 */
109 set_io_port_base(KSEG1);
110}
111
112const char *get_system_type(void)
113{
114 return "Wind River PPMC (GT64120)";
115}
116
117/*
118 * Initializes basic routines and structures pointers, memory size (as
119 * given by the bios and saves the command line.
120 */
121void __init prom_init(void)
122{
123 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
124 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
125
126 wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
127 WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
128}
diff --git a/arch/mips/wrppmc/time.c b/arch/mips/wrppmc/time.c
deleted file mode 100644
index 668dbd5f12c5..000000000000
--- a/arch/mips/wrppmc/time.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * time.c: MIPS CPU Count/Compare timer hookup
3 *
4 * Author: Mark.Zhan, <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2006, Wind River System Inc.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16
17#include <asm/gt64120.h>
18#include <asm/time.h>
19
20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
21
22/*
23 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
24 *
25 * NOTE: We disable all GT64120 timers, and use MIPS processor internal
26 * timer as the source of kernel clock tick.
27 */
28void __init plat_time_init(void)
29{
30 /* Disable GT64120 timers */
31 GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
32 GT_WRITE(GT_TC0_OFS, 0x00);
33 GT_WRITE(GT_TC1_OFS, 0x00);
34 GT_WRITE(GT_TC2_OFS, 0x00);
35 GT_WRITE(GT_TC3_OFS, 0x00);
36
37 /* Use MIPS compare/count internal timer */
38 mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
39}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 10:12:50 -0500