diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:09:17 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:20 -0400 |
commit | fbaa4e2a19a4b85b38464cf2683e4d275b4d970c (patch) | |
tree | 810aa976c773abbf4f0affdec94d24b067435ee5 /arch/mips/vr41xx | |
parent | d7ae7c7137868fca5a18954f4d70d525f38867c9 (diff) |
MIPS: VR41xx: Convert to new irq_chip functions
And cleanup direct access to irq_desc[].
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2208/
Patchwork: https://patchwork.linux-mips.org/patch/2209/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/vr41xx')
-rw-r--r-- | arch/mips/vr41xx/common/icu.c | 72 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/irq.c | 19 |
2 files changed, 44 insertions, 47 deletions
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 6153b6a05ccf..f53156bb9aa8 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -154,7 +154,7 @@ static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) | |||
154 | 154 | ||
155 | void vr41xx_enable_piuint(uint16_t mask) | 155 | void vr41xx_enable_piuint(uint16_t mask) |
156 | { | 156 | { |
157 | struct irq_desc *desc = irq_desc + PIU_IRQ; | 157 | struct irq_desc *desc = irq_to_desc(PIU_IRQ); |
158 | unsigned long flags; | 158 | unsigned long flags; |
159 | 159 | ||
160 | if (current_cpu_type() == CPU_VR4111 || | 160 | if (current_cpu_type() == CPU_VR4111 || |
@@ -169,7 +169,7 @@ EXPORT_SYMBOL(vr41xx_enable_piuint); | |||
169 | 169 | ||
170 | void vr41xx_disable_piuint(uint16_t mask) | 170 | void vr41xx_disable_piuint(uint16_t mask) |
171 | { | 171 | { |
172 | struct irq_desc *desc = irq_desc + PIU_IRQ; | 172 | struct irq_desc *desc = irq_to_desc(PIU_IRQ); |
173 | unsigned long flags; | 173 | unsigned long flags; |
174 | 174 | ||
175 | if (current_cpu_type() == CPU_VR4111 || | 175 | if (current_cpu_type() == CPU_VR4111 || |
@@ -184,7 +184,7 @@ EXPORT_SYMBOL(vr41xx_disable_piuint); | |||
184 | 184 | ||
185 | void vr41xx_enable_aiuint(uint16_t mask) | 185 | void vr41xx_enable_aiuint(uint16_t mask) |
186 | { | 186 | { |
187 | struct irq_desc *desc = irq_desc + AIU_IRQ; | 187 | struct irq_desc *desc = irq_to_desc(AIU_IRQ); |
188 | unsigned long flags; | 188 | unsigned long flags; |
189 | 189 | ||
190 | if (current_cpu_type() == CPU_VR4111 || | 190 | if (current_cpu_type() == CPU_VR4111 || |
@@ -199,7 +199,7 @@ EXPORT_SYMBOL(vr41xx_enable_aiuint); | |||
199 | 199 | ||
200 | void vr41xx_disable_aiuint(uint16_t mask) | 200 | void vr41xx_disable_aiuint(uint16_t mask) |
201 | { | 201 | { |
202 | struct irq_desc *desc = irq_desc + AIU_IRQ; | 202 | struct irq_desc *desc = irq_to_desc(AIU_IRQ); |
203 | unsigned long flags; | 203 | unsigned long flags; |
204 | 204 | ||
205 | if (current_cpu_type() == CPU_VR4111 || | 205 | if (current_cpu_type() == CPU_VR4111 || |
@@ -214,7 +214,7 @@ EXPORT_SYMBOL(vr41xx_disable_aiuint); | |||
214 | 214 | ||
215 | void vr41xx_enable_kiuint(uint16_t mask) | 215 | void vr41xx_enable_kiuint(uint16_t mask) |
216 | { | 216 | { |
217 | struct irq_desc *desc = irq_desc + KIU_IRQ; | 217 | struct irq_desc *desc = irq_to_desc(KIU_IRQ); |
218 | unsigned long flags; | 218 | unsigned long flags; |
219 | 219 | ||
220 | if (current_cpu_type() == CPU_VR4111 || | 220 | if (current_cpu_type() == CPU_VR4111 || |
@@ -229,7 +229,7 @@ EXPORT_SYMBOL(vr41xx_enable_kiuint); | |||
229 | 229 | ||
230 | void vr41xx_disable_kiuint(uint16_t mask) | 230 | void vr41xx_disable_kiuint(uint16_t mask) |
231 | { | 231 | { |
232 | struct irq_desc *desc = irq_desc + KIU_IRQ; | 232 | struct irq_desc *desc = irq_to_desc(KIU_IRQ); |
233 | unsigned long flags; | 233 | unsigned long flags; |
234 | 234 | ||
235 | if (current_cpu_type() == CPU_VR4111 || | 235 | if (current_cpu_type() == CPU_VR4111 || |
@@ -244,7 +244,7 @@ EXPORT_SYMBOL(vr41xx_disable_kiuint); | |||
244 | 244 | ||
245 | void vr41xx_enable_macint(uint16_t mask) | 245 | void vr41xx_enable_macint(uint16_t mask) |
246 | { | 246 | { |
247 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; | 247 | struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); |
248 | unsigned long flags; | 248 | unsigned long flags; |
249 | 249 | ||
250 | raw_spin_lock_irqsave(&desc->lock, flags); | 250 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -256,7 +256,7 @@ EXPORT_SYMBOL(vr41xx_enable_macint); | |||
256 | 256 | ||
257 | void vr41xx_disable_macint(uint16_t mask) | 257 | void vr41xx_disable_macint(uint16_t mask) |
258 | { | 258 | { |
259 | struct irq_desc *desc = irq_desc + ETHERNET_IRQ; | 259 | struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); |
260 | unsigned long flags; | 260 | unsigned long flags; |
261 | 261 | ||
262 | raw_spin_lock_irqsave(&desc->lock, flags); | 262 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -268,7 +268,7 @@ EXPORT_SYMBOL(vr41xx_disable_macint); | |||
268 | 268 | ||
269 | void vr41xx_enable_dsiuint(uint16_t mask) | 269 | void vr41xx_enable_dsiuint(uint16_t mask) |
270 | { | 270 | { |
271 | struct irq_desc *desc = irq_desc + DSIU_IRQ; | 271 | struct irq_desc *desc = irq_to_desc(DSIU_IRQ); |
272 | unsigned long flags; | 272 | unsigned long flags; |
273 | 273 | ||
274 | raw_spin_lock_irqsave(&desc->lock, flags); | 274 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -280,7 +280,7 @@ EXPORT_SYMBOL(vr41xx_enable_dsiuint); | |||
280 | 280 | ||
281 | void vr41xx_disable_dsiuint(uint16_t mask) | 281 | void vr41xx_disable_dsiuint(uint16_t mask) |
282 | { | 282 | { |
283 | struct irq_desc *desc = irq_desc + DSIU_IRQ; | 283 | struct irq_desc *desc = irq_to_desc(DSIU_IRQ); |
284 | unsigned long flags; | 284 | unsigned long flags; |
285 | 285 | ||
286 | raw_spin_lock_irqsave(&desc->lock, flags); | 286 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -292,7 +292,7 @@ EXPORT_SYMBOL(vr41xx_disable_dsiuint); | |||
292 | 292 | ||
293 | void vr41xx_enable_firint(uint16_t mask) | 293 | void vr41xx_enable_firint(uint16_t mask) |
294 | { | 294 | { |
295 | struct irq_desc *desc = irq_desc + FIR_IRQ; | 295 | struct irq_desc *desc = irq_to_desc(FIR_IRQ); |
296 | unsigned long flags; | 296 | unsigned long flags; |
297 | 297 | ||
298 | raw_spin_lock_irqsave(&desc->lock, flags); | 298 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -304,7 +304,7 @@ EXPORT_SYMBOL(vr41xx_enable_firint); | |||
304 | 304 | ||
305 | void vr41xx_disable_firint(uint16_t mask) | 305 | void vr41xx_disable_firint(uint16_t mask) |
306 | { | 306 | { |
307 | struct irq_desc *desc = irq_desc + FIR_IRQ; | 307 | struct irq_desc *desc = irq_to_desc(FIR_IRQ); |
308 | unsigned long flags; | 308 | unsigned long flags; |
309 | 309 | ||
310 | raw_spin_lock_irqsave(&desc->lock, flags); | 310 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -316,7 +316,7 @@ EXPORT_SYMBOL(vr41xx_disable_firint); | |||
316 | 316 | ||
317 | void vr41xx_enable_pciint(void) | 317 | void vr41xx_enable_pciint(void) |
318 | { | 318 | { |
319 | struct irq_desc *desc = irq_desc + PCI_IRQ; | 319 | struct irq_desc *desc = irq_to_desc(PCI_IRQ); |
320 | unsigned long flags; | 320 | unsigned long flags; |
321 | 321 | ||
322 | if (current_cpu_type() == CPU_VR4122 || | 322 | if (current_cpu_type() == CPU_VR4122 || |
@@ -332,7 +332,7 @@ EXPORT_SYMBOL(vr41xx_enable_pciint); | |||
332 | 332 | ||
333 | void vr41xx_disable_pciint(void) | 333 | void vr41xx_disable_pciint(void) |
334 | { | 334 | { |
335 | struct irq_desc *desc = irq_desc + PCI_IRQ; | 335 | struct irq_desc *desc = irq_to_desc(PCI_IRQ); |
336 | unsigned long flags; | 336 | unsigned long flags; |
337 | 337 | ||
338 | if (current_cpu_type() == CPU_VR4122 || | 338 | if (current_cpu_type() == CPU_VR4122 || |
@@ -348,7 +348,7 @@ EXPORT_SYMBOL(vr41xx_disable_pciint); | |||
348 | 348 | ||
349 | void vr41xx_enable_scuint(void) | 349 | void vr41xx_enable_scuint(void) |
350 | { | 350 | { |
351 | struct irq_desc *desc = irq_desc + SCU_IRQ; | 351 | struct irq_desc *desc = irq_to_desc(SCU_IRQ); |
352 | unsigned long flags; | 352 | unsigned long flags; |
353 | 353 | ||
354 | if (current_cpu_type() == CPU_VR4122 || | 354 | if (current_cpu_type() == CPU_VR4122 || |
@@ -364,7 +364,7 @@ EXPORT_SYMBOL(vr41xx_enable_scuint); | |||
364 | 364 | ||
365 | void vr41xx_disable_scuint(void) | 365 | void vr41xx_disable_scuint(void) |
366 | { | 366 | { |
367 | struct irq_desc *desc = irq_desc + SCU_IRQ; | 367 | struct irq_desc *desc = irq_to_desc(SCU_IRQ); |
368 | unsigned long flags; | 368 | unsigned long flags; |
369 | 369 | ||
370 | if (current_cpu_type() == CPU_VR4122 || | 370 | if (current_cpu_type() == CPU_VR4122 || |
@@ -380,7 +380,7 @@ EXPORT_SYMBOL(vr41xx_disable_scuint); | |||
380 | 380 | ||
381 | void vr41xx_enable_csiint(uint16_t mask) | 381 | void vr41xx_enable_csiint(uint16_t mask) |
382 | { | 382 | { |
383 | struct irq_desc *desc = irq_desc + CSI_IRQ; | 383 | struct irq_desc *desc = irq_to_desc(CSI_IRQ); |
384 | unsigned long flags; | 384 | unsigned long flags; |
385 | 385 | ||
386 | if (current_cpu_type() == CPU_VR4122 || | 386 | if (current_cpu_type() == CPU_VR4122 || |
@@ -396,7 +396,7 @@ EXPORT_SYMBOL(vr41xx_enable_csiint); | |||
396 | 396 | ||
397 | void vr41xx_disable_csiint(uint16_t mask) | 397 | void vr41xx_disable_csiint(uint16_t mask) |
398 | { | 398 | { |
399 | struct irq_desc *desc = irq_desc + CSI_IRQ; | 399 | struct irq_desc *desc = irq_to_desc(CSI_IRQ); |
400 | unsigned long flags; | 400 | unsigned long flags; |
401 | 401 | ||
402 | if (current_cpu_type() == CPU_VR4122 || | 402 | if (current_cpu_type() == CPU_VR4122 || |
@@ -412,7 +412,7 @@ EXPORT_SYMBOL(vr41xx_disable_csiint); | |||
412 | 412 | ||
413 | void vr41xx_enable_bcuint(void) | 413 | void vr41xx_enable_bcuint(void) |
414 | { | 414 | { |
415 | struct irq_desc *desc = irq_desc + BCU_IRQ; | 415 | struct irq_desc *desc = irq_to_desc(BCU_IRQ); |
416 | unsigned long flags; | 416 | unsigned long flags; |
417 | 417 | ||
418 | if (current_cpu_type() == CPU_VR4122 || | 418 | if (current_cpu_type() == CPU_VR4122 || |
@@ -428,7 +428,7 @@ EXPORT_SYMBOL(vr41xx_enable_bcuint); | |||
428 | 428 | ||
429 | void vr41xx_disable_bcuint(void) | 429 | void vr41xx_disable_bcuint(void) |
430 | { | 430 | { |
431 | struct irq_desc *desc = irq_desc + BCU_IRQ; | 431 | struct irq_desc *desc = irq_to_desc(BCU_IRQ); |
432 | unsigned long flags; | 432 | unsigned long flags; |
433 | 433 | ||
434 | if (current_cpu_type() == CPU_VR4122 || | 434 | if (current_cpu_type() == CPU_VR4122 || |
@@ -442,45 +442,41 @@ void vr41xx_disable_bcuint(void) | |||
442 | 442 | ||
443 | EXPORT_SYMBOL(vr41xx_disable_bcuint); | 443 | EXPORT_SYMBOL(vr41xx_disable_bcuint); |
444 | 444 | ||
445 | static void disable_sysint1_irq(unsigned int irq) | 445 | static void disable_sysint1_irq(struct irq_data *d) |
446 | { | 446 | { |
447 | icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); | 447 | icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); |
448 | } | 448 | } |
449 | 449 | ||
450 | static void enable_sysint1_irq(unsigned int irq) | 450 | static void enable_sysint1_irq(struct irq_data *d) |
451 | { | 451 | { |
452 | icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); | 452 | icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); |
453 | } | 453 | } |
454 | 454 | ||
455 | static struct irq_chip sysint1_irq_type = { | 455 | static struct irq_chip sysint1_irq_type = { |
456 | .name = "SYSINT1", | 456 | .name = "SYSINT1", |
457 | .ack = disable_sysint1_irq, | 457 | .irq_mask = disable_sysint1_irq, |
458 | .mask = disable_sysint1_irq, | 458 | .irq_unmask = enable_sysint1_irq, |
459 | .mask_ack = disable_sysint1_irq, | ||
460 | .unmask = enable_sysint1_irq, | ||
461 | }; | 459 | }; |
462 | 460 | ||
463 | static void disable_sysint2_irq(unsigned int irq) | 461 | static void disable_sysint2_irq(struct irq_data *d) |
464 | { | 462 | { |
465 | icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); | 463 | icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); |
466 | } | 464 | } |
467 | 465 | ||
468 | static void enable_sysint2_irq(unsigned int irq) | 466 | static void enable_sysint2_irq(struct irq_data *d) |
469 | { | 467 | { |
470 | icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); | 468 | icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); |
471 | } | 469 | } |
472 | 470 | ||
473 | static struct irq_chip sysint2_irq_type = { | 471 | static struct irq_chip sysint2_irq_type = { |
474 | .name = "SYSINT2", | 472 | .name = "SYSINT2", |
475 | .ack = disable_sysint2_irq, | 473 | .irq_mask = disable_sysint2_irq, |
476 | .mask = disable_sysint2_irq, | 474 | .irq_unmask = enable_sysint2_irq, |
477 | .mask_ack = disable_sysint2_irq, | ||
478 | .unmask = enable_sysint2_irq, | ||
479 | }; | 475 | }; |
480 | 476 | ||
481 | static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) | 477 | static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) |
482 | { | 478 | { |
483 | struct irq_desc *desc = irq_desc + irq; | 479 | struct irq_desc *desc = irq_to_desc(irq); |
484 | uint16_t intassign0, intassign1; | 480 | uint16_t intassign0, intassign1; |
485 | unsigned int pin; | 481 | unsigned int pin; |
486 | 482 | ||
@@ -540,7 +536,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) | |||
540 | 536 | ||
541 | static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) | 537 | static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) |
542 | { | 538 | { |
543 | struct irq_desc *desc = irq_desc + irq; | 539 | struct irq_desc *desc = irq_to_desc(irq); |
544 | uint16_t intassign2, intassign3; | 540 | uint16_t intassign2, intassign3; |
545 | unsigned int pin; | 541 | unsigned int pin; |
546 | 542 | ||
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 0975eb72d385..9ff7f397c0e1 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c | |||
@@ -62,7 +62,6 @@ EXPORT_SYMBOL_GPL(cascade_irq); | |||
62 | static void irq_dispatch(unsigned int irq) | 62 | static void irq_dispatch(unsigned int irq) |
63 | { | 63 | { |
64 | irq_cascade_t *cascade; | 64 | irq_cascade_t *cascade; |
65 | struct irq_desc *desc; | ||
66 | 65 | ||
67 | if (irq >= NR_IRQS) { | 66 | if (irq >= NR_IRQS) { |
68 | atomic_inc(&irq_err_count); | 67 | atomic_inc(&irq_err_count); |
@@ -71,14 +70,16 @@ static void irq_dispatch(unsigned int irq) | |||
71 | 70 | ||
72 | cascade = irq_cascade + irq; | 71 | cascade = irq_cascade + irq; |
73 | if (cascade->get_irq != NULL) { | 72 | if (cascade->get_irq != NULL) { |
74 | unsigned int source_irq = irq; | 73 | struct irq_desc *desc = irq_to_desc(irq); |
74 | struct irq_data *idata = irq_desc_get_irq_data(desc); | ||
75 | struct irq_chip *chip = irq_desc_get_chip(desc); | ||
75 | int ret; | 76 | int ret; |
76 | desc = irq_desc + source_irq; | 77 | |
77 | if (desc->chip->mask_ack) | 78 | if (chip->irq_mask_ack) |
78 | desc->chip->mask_ack(source_irq); | 79 | chip->irq_mask_ack(idata); |
79 | else { | 80 | else { |
80 | desc->chip->mask(source_irq); | 81 | chip->irq_mask(idata); |
81 | desc->chip->ack(source_irq); | 82 | chip->irq_ack(idata); |
82 | } | 83 | } |
83 | ret = cascade->get_irq(irq); | 84 | ret = cascade->get_irq(irq); |
84 | irq = ret; | 85 | irq = ret; |
@@ -86,8 +87,8 @@ static void irq_dispatch(unsigned int irq) | |||
86 | atomic_inc(&irq_err_count); | 87 | atomic_inc(&irq_err_count); |
87 | else | 88 | else |
88 | irq_dispatch(irq); | 89 | irq_dispatch(irq); |
89 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | 90 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) |
90 | desc->chip->unmask(source_irq); | 91 | chip->irq_unmask(idata); |
91 | } else | 92 | } else |
92 | do_IRQ(irq); | 93 | do_IRQ(irq); |
93 | } | 94 | } |