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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:33:08 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit89d63fe179520b11f54de1f26755b7444c79e73a (patch)
treefede06c5648335652c864fc35c951d991cbab183 /arch/mips/txx9/rbtx4927
parent22b1d707ffc99faebd86257ad19d5bb9fc624734 (diff)
[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/rbtx4927')
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c20
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c499
2 files changed, 122 insertions, 397 deletions
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 936e50e91d95..bef1447aeed2 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
111#include <linux/types.h> 111#include <linux/types.h>
112#include <linux/interrupt.h> 112#include <linux/interrupt.h>
113#include <asm/io.h> 113#include <asm/io.h>
114#ifdef CONFIG_TOSHIBA_FPCIB0
115#include <asm/i8259.h>
116#endif
117#include <asm/txx9/rbtx4927.h> 114#include <asm/txx9/rbtx4927.h>
118 115
119#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 116#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
@@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
125#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC 122#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
126#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) 123#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
127 124
128extern int tx4927_using_backplane;
129
130static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 125static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
131static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 126static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
132 127
@@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
146 u8 level3; 141 u8 level3;
147 142
148 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 143 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
149 if (level3) { 144 if (level3)
150 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; 145 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
151#ifdef CONFIG_TOSHIBA_FPCIB0
152 if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
153 tx4927_using_backplane) {
154 int irq = i8259_irq();
155 if (irq >= 0)
156 sw_irq = irq;
157 }
158#endif
159 }
160 return (sw_irq); 146 return (sw_irq);
161} 147}
162 148
@@ -205,10 +191,6 @@ void __init arch_init_irq(void)
205 191
206 tx4927_irq_init(); 192 tx4927_irq_init();
207 toshiba_rbtx4927_irq_ioc_init(); 193 toshiba_rbtx4927_irq_ioc_init();
208#ifdef CONFIG_TOSHIBA_FPCIB0
209 if (tx4927_using_backplane)
210 init_i8259_irqs();
211#endif
212 /* Onboard 10M Ether: High Active */ 194 /* Onboard 10M Ether: High Active */
213 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 195 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
214} 196}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index df1b6e99b666..86b870abc319 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -47,10 +47,10 @@
47#include <linux/types.h> 47#include <linux/types.h>
48#include <linux/ioport.h> 48#include <linux/ioport.h>
49#include <linux/interrupt.h> 49#include <linux/interrupt.h>
50#include <linux/pci.h>
51#include <linux/pm.h> 50#include <linux/pm.h>
52#include <linux/platform_device.h> 51#include <linux/platform_device.h>
53#include <linux/clk.h> 52#include <linux/clk.h>
53#include <linux/delay.h>
54 54
55#include <asm/bootinfo.h> 55#include <asm/bootinfo.h>
56#include <asm/io.h> 56#include <asm/io.h>
@@ -58,10 +58,10 @@
58#include <asm/reboot.h> 58#include <asm/reboot.h>
59#include <asm/time.h> 59#include <asm/time.h>
60#include <asm/txx9tmr.h> 60#include <asm/txx9tmr.h>
61#ifdef CONFIG_TOSHIBA_FPCIB0 61#include <asm/txx9/generic.h>
62#include <asm/txx9/smsc_fdc37m81x.h> 62#include <asm/txx9/pci.h>
63#endif
64#include <asm/txx9/rbtx4927.h> 63#include <asm/txx9/rbtx4927.h>
64#include <asm/txx9/tx4938.h> /* for TX4937 */
65#ifdef CONFIG_SERIAL_TXX9 65#ifdef CONFIG_SERIAL_TXX9
66#include <linux/serial_core.h> 66#include <linux/serial_core.h>
67#endif 67#endif
@@ -70,356 +70,116 @@
70extern void toshiba_rbtx4927_restart(char *command); 70extern void toshiba_rbtx4927_restart(char *command);
71extern void toshiba_rbtx4927_halt(void); 71extern void toshiba_rbtx4927_halt(void);
72extern void toshiba_rbtx4927_power_off(void); 72extern void toshiba_rbtx4927_power_off(void);
73
74int tx4927_using_backplane = 0;
75
76extern void toshiba_rbtx4927_irq_setup(void); 73extern void toshiba_rbtx4927_irq_setup(void);
77 74
78char *prom_getcmdline(void); 75char *prom_getcmdline(void);
79 76
80#ifdef CONFIG_PCI
81#undef TX4927_SUPPORT_COMMAND_IO
82#undef TX4927_SUPPORT_PCI_66
83int tx4927_cpu_clock = 100000000; /* 100MHz */
84unsigned long mips_pci_io_base;
85unsigned long mips_pci_io_size;
86unsigned long mips_pci_mem_base;
87unsigned long mips_pci_mem_size;
88/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
89unsigned long mips_pci_io_pciaddr = 0;
90unsigned long mips_memory_upper;
91static int tx4927_ccfg_toeon = 1; 77static int tx4927_ccfg_toeon = 1;
92static int tx4927_pcic_trdyto = 0; /* default: disabled */
93unsigned long tx4927_ce_base[8];
94int tx4927_pci66 = 0; /* 0:auto */
95#endif
96 78
97char *toshiba_name = ""; 79char *toshiba_name = "";
98 80
99#ifdef CONFIG_PCI 81#ifdef CONFIG_PCI
100extern struct pci_controller tx4927_controller; 82static void __init tx4927_pci_setup(void)
101
102static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
103 int top_bus, int busnr, int devfn)
104{ 83{
105 static struct pci_dev dev; 84 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
106 static struct pci_bus bus; 85 struct pci_controller *c = &txx9_primary_pcic;
107 86
108 dev.sysdata = (void *)hose; 87 register_pci_controller(c);
109 dev.devfn = devfn; 88
110 bus.number = busnr; 89 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
111 bus.ops = hose->pci_ops; 90 txx9_pci_option =
112 bus.parent = NULL; 91 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
113 dev.bus = &bus; 92 TXX9_PCI_OPT_CLK_66; /* already configured */
114 93
115 return &dev; 94 /* Reset PCI Bus */
116} 95 writeb(1, rbtx4927_pcireset_addr);
117 96 /* Reset PCIC */
118#define EARLY_PCI_OP(rw, size, type) \ 97 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
119static int early_##rw##_config_##size(struct pci_controller *hose, \ 98 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
120 int top_bus, int bus, int devfn, int offset, type value) \ 99 TXX9_PCI_OPT_CLK_66)
121{ \ 100 tx4927_pciclk66_setup();
122 return pci_##rw##_config_##size( \ 101 mdelay(10);
123 fake_pci_dev(hose, top_bus, bus, devfn), \ 102 /* clear PCIC reset */
124 offset, value); \ 103 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
104 writeb(0, rbtx4927_pcireset_addr);
105 iob();
106
107 tx4927_report_pciclk();
108 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
109 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
110 TXX9_PCI_OPT_CLK_AUTO &&
111 txx9_pci66_check(c, 0, 0)) {
112 /* Reset PCI Bus */
113 writeb(1, rbtx4927_pcireset_addr);
114 /* Reset PCIC */
115 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
116 tx4927_pciclk66_setup();
117 mdelay(10);
118 /* clear PCIC reset */
119 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
120 writeb(0, rbtx4927_pcireset_addr);
121 iob();
122 /* Reinitialize PCIC */
123 tx4927_report_pciclk();
124 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
125 }
125} 126}
126 127
127EARLY_PCI_OP(read, byte, u8 *) 128static void __init tx4937_pci_setup(void)
128EARLY_PCI_OP(read, dword, u32 *)
129EARLY_PCI_OP(write, byte, u8)
130EARLY_PCI_OP(write, dword, u32)
131
132static int __init tx4927_pcibios_init(void)
133{ 129{
134 unsigned int id; 130 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
135 u32 pci_devfn; 131 struct pci_controller *c = &txx9_primary_pcic;
136 int devfn_start = 0; 132
137 int devfn_stop = 0xff; 133 register_pci_controller(c);
138 int busno = 0; /* One bus on the Toshiba */ 134
139 struct pci_controller *hose = &tx4927_controller; 135 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
140 136 txx9_pci_option =
141 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { 137 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
142 early_read_config_dword(hose, busno, busno, pci_devfn, 138 TXX9_PCI_OPT_CLK_66; /* already configured */
143 PCI_VENDOR_ID, &id); 139
144 140 /* Reset PCI Bus */
145 if (id == 0xffffffff) { 141 writeb(1, rbtx4927_pcireset_addr);
146 continue; 142 /* Reset PCIC */
147 } 143 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
148 144 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
149 if (id == 0x94601055) { 145 TXX9_PCI_OPT_CLK_66)
150 u8 v08_64; 146 tx4938_pciclk66_setup();
151 u32 v32_b0; 147 mdelay(10);
152 u8 v08_e1; 148 /* clear PCIC reset */
153 149 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
154 early_read_config_byte(hose, busno, busno, 150 writeb(0, rbtx4927_pcireset_addr);
155 pci_devfn, 0x64, &v08_64); 151 iob();
156 early_read_config_dword(hose, busno, busno, 152
157 pci_devfn, 0xb0, &v32_b0); 153 tx4938_report_pciclk();
158 early_read_config_byte(hose, busno, busno, 154 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
159 pci_devfn, 0xe1, &v08_e1); 155 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
160 156 TXX9_PCI_OPT_CLK_AUTO &&
161 /* serial irq control */ 157 txx9_pci66_check(c, 0, 0)) {
162 v08_64 = 0xd0; 158 /* Reset PCI Bus */
163 159 writeb(1, rbtx4927_pcireset_addr);
164 /* serial irq pin */ 160 /* Reset PCIC */
165 v32_b0 |= 0x00010000; 161 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
166 162 tx4938_pciclk66_setup();
167 /* ide irq on isa14 */ 163 mdelay(10);
168 v08_e1 &= 0xf0; 164 /* clear PCIC reset */
169 v08_e1 |= 0x0d; 165 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
170 166 writeb(0, rbtx4927_pcireset_addr);
171 early_write_config_byte(hose, busno, busno, 167 iob();
172 pci_devfn, 0x64, v08_64); 168 /* Reinitialize PCIC */
173 early_write_config_dword(hose, busno, busno, 169 tx4938_report_pciclk();
174 pci_devfn, 0xb0, v32_b0); 170 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
175 early_write_config_byte(hose, busno, busno,
176 pci_devfn, 0xe1, v08_e1);
177 }
178
179 if (id == 0x91301055) {
180 u8 v08_04;
181 u8 v08_09;
182 u8 v08_41;
183 u8 v08_43;
184 u8 v08_5c;
185
186 early_read_config_byte(hose, busno, busno,
187 pci_devfn, 0x04, &v08_04);
188 early_read_config_byte(hose, busno, busno,
189 pci_devfn, 0x09, &v08_09);
190 early_read_config_byte(hose, busno, busno,
191 pci_devfn, 0x41, &v08_41);
192 early_read_config_byte(hose, busno, busno,
193 pci_devfn, 0x43, &v08_43);
194 early_read_config_byte(hose, busno, busno,
195 pci_devfn, 0x5c, &v08_5c);
196
197 /* enable ide master/io */
198 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
199
200 /* enable ide native mode */
201 v08_09 |= 0x05;
202
203 /* enable primary ide */
204 v08_41 |= 0x80;
205
206 /* enable secondary ide */
207 v08_43 |= 0x80;
208
209 /*
210 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
211 *
212 * This line of code is intended to provide the user with a work
213 * around solution to the anomalies cited in SMSC's anomaly sheet
214 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
215 *
216 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
217 */
218 v08_5c |= 0x01;
219
220 early_write_config_byte(hose, busno, busno,
221 pci_devfn, 0x5c, v08_5c);
222 early_write_config_byte(hose, busno, busno,
223 pci_devfn, 0x04, v08_04);
224 early_write_config_byte(hose, busno, busno,
225 pci_devfn, 0x09, v08_09);
226 early_write_config_byte(hose, busno, busno,
227 pci_devfn, 0x41, v08_41);
228 early_write_config_byte(hose, busno, busno,
229 pci_devfn, 0x43, v08_43);
230 }
231
232 } 171 }
233
234 register_pci_controller(&tx4927_controller);
235 return 0;
236} 172}
237 173
238arch_initcall(tx4927_pcibios_init); 174static int __init rbtx4927_arch_init(void)
239
240extern struct resource pci_io_resource;
241extern struct resource pci_mem_resource;
242
243void __init tx4927_pci_setup(void)
244{ 175{
245 static int called = 0; 176 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
246 extern unsigned int tx4927_get_mem_size(void); 177 tx4937_pci_setup();
247 178 else
248 mips_memory_upper = tx4927_get_mem_size() << 20; 179 tx4927_pci_setup();
249 mips_memory_upper += KSEG0; 180 return 0;
250 mips_pci_io_base = TX4927_PCIIO;
251 mips_pci_io_size = TX4927_PCIIO_SIZE;
252 mips_pci_mem_base = TX4927_PCIMEM;
253 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
254
255 if (!called) {
256 printk
257 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
258 toshiba_name,
259 (unsigned short) (tx4927_pcicptr->pciid >> 16),
260 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
261 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
262 (!(tx4927_ccfgptr->
263 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
264 "Internal");
265 called = 1;
266 }
267 printk("%s PCIC --%s PCICLK:", toshiba_name,
268 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
269 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
270 int pciclk = 0;
271 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
272 switch ((unsigned long) tx4927_ccfgptr->
273 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
274 case TX4937_CCFG_PCIDIVMODE_4:
275 pciclk = tx4927_cpu_clock / 4;
276 break;
277 case TX4937_CCFG_PCIDIVMODE_4_5:
278 pciclk = tx4927_cpu_clock * 2 / 9;
279 break;
280 case TX4937_CCFG_PCIDIVMODE_5:
281 pciclk = tx4927_cpu_clock / 5;
282 break;
283 case TX4937_CCFG_PCIDIVMODE_5_5:
284 pciclk = tx4927_cpu_clock * 2 / 11;
285 break;
286 case TX4937_CCFG_PCIDIVMODE_8:
287 pciclk = tx4927_cpu_clock / 8;
288 break;
289 case TX4937_CCFG_PCIDIVMODE_9:
290 pciclk = tx4927_cpu_clock / 9;
291 break;
292 case TX4937_CCFG_PCIDIVMODE_10:
293 pciclk = tx4927_cpu_clock / 10;
294 break;
295 case TX4937_CCFG_PCIDIVMODE_11:
296 pciclk = tx4927_cpu_clock / 11;
297 break;
298 }
299
300 else
301 switch ((unsigned long) tx4927_ccfgptr->
302 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
303 case TX4927_CCFG_PCIDIVMODE_2_5:
304 pciclk = tx4927_cpu_clock * 2 / 5;
305 break;
306 case TX4927_CCFG_PCIDIVMODE_3:
307 pciclk = tx4927_cpu_clock / 3;
308 break;
309 case TX4927_CCFG_PCIDIVMODE_5:
310 pciclk = tx4927_cpu_clock / 5;
311 break;
312 case TX4927_CCFG_PCIDIVMODE_6:
313 pciclk = tx4927_cpu_clock / 6;
314 break;
315 }
316
317 printk("Internal(%dMHz)", pciclk / 1000000);
318 } else
319 printk("External");
320 printk("\n");
321
322 /* GB->PCI mappings */
323 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
324 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
325#ifdef __BIG_ENDIAN
326 TX4927_PCIC_G2PIOGBASE_ECHG
327#else
328 TX4927_PCIC_G2PIOGBASE_BSDIS
329#endif
330 ;
331
332 tx4927_pcicptr->g2piopbase = 0;
333
334 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
335 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
336#ifdef __BIG_ENDIAN
337 TX4927_PCIC_G2PMnGBASE_ECHG
338#else
339 TX4927_PCIC_G2PMnGBASE_BSDIS
340#endif
341 ;
342 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
343
344 tx4927_pcicptr->g2pmmask[1] = 0;
345 tx4927_pcicptr->g2pmgbase[1] = 0;
346 tx4927_pcicptr->g2pmpbase[1] = 0;
347 tx4927_pcicptr->g2pmmask[2] = 0;
348 tx4927_pcicptr->g2pmgbase[2] = 0;
349 tx4927_pcicptr->g2pmpbase[2] = 0;
350
351
352 /* PCI->GB mappings (I/O 256B) */
353 tx4927_pcicptr->p2giopbase = 0; /* 256B */
354
355 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
356 tx4927_pcicptr->p2gm0plbase = 0;
357 tx4927_pcicptr->p2gm0pubase = 0;
358 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
359#ifdef __BIG_ENDIAN
360 TX4927_PCIC_P2GMnGBASE_TECHG
361#else
362 TX4927_PCIC_P2GMnGBASE_TBSDIS
363#endif
364 ;
365
366 /* PCI->GB mappings (MEM 16MB) -not used */
367 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
368 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
369 tx4927_pcicptr->p2gmgbase[1] = 0;
370
371 /* PCI->GB mappings (MEM 1MB) -not used */
372 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
373 tx4927_pcicptr->p2gmgbase[2] = 0;
374
375
376 /* Enable Initiator Memory 0 Space, I/O Space, Config */
377 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
378 tx4927_pcicptr->pciccfg |=
379 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
380 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
381
382
383 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
384 tx4927_pcicptr->pcicfg1 = 0;
385
386 if (tx4927_pcic_trdyto >= 0) {
387 tx4927_pcicptr->g2ptocnt &= ~0xff;
388 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
389 }
390
391 /* Clear All Local Bus Status */
392 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
393 /* Enable All Local Bus Interrupts */
394 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
395 /* Clear All Initiator Status */
396 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
397 /* Enable All Initiator Interrupts */
398 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
399 /* Clear All PCI Status Error */
400 tx4927_pcicptr->pcistatus =
401 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
402 (TX4927_PCIC_PCISTATUS_ALL << 16);
403 /* Enable All PCI Status Error Interrupts */
404 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
405
406 /* PCIC Int => IRC IRQ16 */
407 tx4927_pcicptr->pcicfg2 =
408 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
409
410 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
411 /* XXX */
412 } else {
413 /* Reset Bus Arbiter */
414 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
415 /* Enable Bus Arbiter */
416 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
417 }
418
419 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
420 PCI_COMMAND_MEMORY |
421 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
422} 181}
182arch_initcall(rbtx4927_arch_init);
423#endif /* CONFIG_PCI */ 183#endif /* CONFIG_PCI */
424 184
425static void __noreturn wait_forever(void) 185static void __noreturn wait_forever(void)
@@ -479,8 +239,6 @@ void __init plat_mem_setup(void)
479 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 239 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
480 write_c0_config(cp0_config); 240 write_c0_config(cp0_config);
481 241
482 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
483
484 ioport_resource.end = 0xffffffff; 242 ioport_resource.end = 0xffffffff;
485 iomem_resource.end = 0xffffffff; 243 iomem_resource.end = 0xffffffff;
486 244
@@ -492,8 +250,13 @@ void __init plat_mem_setup(void)
492 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); 250 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
493 251
494#ifdef CONFIG_PCI 252#ifdef CONFIG_PCI
253 txx9_alloc_pci_controller(&txx9_primary_pcic,
254 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
255 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
256#else
257 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
258#endif
495 259
496 /* PCIC */
497 /* 260 /*
498 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 261 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
499 * 262 *
@@ -517,58 +280,38 @@ void __init plat_mem_setup(void)
517 * 280 *
518 */ 281 */
519 if (mips_machtype == MACH_TOSHIBA_RBTX4937) 282 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
520 switch ((unsigned long)tx4927_ccfgptr-> 283 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
521 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { 284 TX4938_CCFG_PCIDIVMODE_MASK) {
522 case TX4937_CCFG_PCIDIVMODE_8: 285 case TX4938_CCFG_PCIDIVMODE_8:
523 case TX4937_CCFG_PCIDIVMODE_4: 286 case TX4938_CCFG_PCIDIVMODE_4:
524 tx4927_cpu_clock = 266666666; /* 266MHz */ 287 txx9_cpu_clock = 266666666; /* 266MHz */
525 break; 288 break;
526 case TX4937_CCFG_PCIDIVMODE_9: 289 case TX4938_CCFG_PCIDIVMODE_9:
527 case TX4937_CCFG_PCIDIVMODE_4_5: 290 case TX4938_CCFG_PCIDIVMODE_4_5:
528 tx4927_cpu_clock = 300000000; /* 300MHz */ 291 txx9_cpu_clock = 300000000; /* 300MHz */
529 break; 292 break;
530 default: 293 default:
531 tx4927_cpu_clock = 333333333; /* 333MHz */ 294 txx9_cpu_clock = 333333333; /* 333MHz */
532 } 295 }
533 else 296 else
534 switch ((unsigned long)tx4927_ccfgptr-> 297 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
535 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { 298 TX4927_CCFG_PCIDIVMODE_MASK) {
536 case TX4927_CCFG_PCIDIVMODE_2_5: 299 case TX4927_CCFG_PCIDIVMODE_2_5:
537 case TX4927_CCFG_PCIDIVMODE_5: 300 case TX4927_CCFG_PCIDIVMODE_5:
538 tx4927_cpu_clock = 166666666; /* 166MHz */ 301 txx9_cpu_clock = 166666666; /* 166MHz */
539 break; 302 break;
540 default: 303 default:
541 tx4927_cpu_clock = 200000000; /* 200MHz */ 304 txx9_cpu_clock = 200000000; /* 200MHz */
542 } 305 }
306 /* change default value to udelay/mdelay take reasonable time */
307 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
543 308
544 /* CCFG */ 309 /* CCFG */
545 /* do reset on watchdog */ 310 /* do reset on watchdog */
546 tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; 311 tx4927_ccfg_set(TX4927_CCFG_WR);
547 /* enable Timeout BusError */ 312 /* enable Timeout BusError */
548 if (tx4927_ccfg_toeon) 313 if (tx4927_ccfg_toeon)
549 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; 314 tx4927_ccfg_set(TX4927_CCFG_TOE);
550
551 tx4927_pci_setup();
552 if (tx4927_using_backplane == 1)
553 printk("backplane board IS installed\n");
554 else
555 printk("No Backplane \n");
556
557 /* this is on ISA bus behind PCI bus, so need PCI up first */
558#ifdef CONFIG_TOSHIBA_FPCIB0
559 if (tx4927_using_backplane) {
560 smsc_fdc37m81x_init(0x3f0);
561 smsc_fdc37m81x_config_beg();
562 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
563 SMSC_FDC37M81X_KBD);
564 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
565 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
566 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
567 1);
568 smsc_fdc37m81x_config_end();
569 }
570#endif
571#endif /* CONFIG_PCI */
572 315
573#ifdef CONFIG_SERIAL_TXX9 316#ifdef CONFIG_SERIAL_TXX9
574 { 317 {
@@ -611,8 +354,8 @@ void __init plat_mem_setup(void)
611 354
612void __init plat_time_init(void) 355void __init plat_time_init(void)
613{ 356{
614 mips_hpt_frequency = tx4927_cpu_clock / 2; 357 mips_hpt_frequency = txx9_cpu_clock / 2;
615 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) 358 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
616 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, 359 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
617 TXX9_IRQ_BASE + 17, 360 TXX9_IRQ_BASE + 17,
618 50000000); 361 50000000);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 06:21:44 -0400