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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-09-01 09:22:37 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:47 -0400
commit21e77df215e58523a755b5dd006cb17610616f20 (patch)
tree94895b0fdc98e5f6ac44ba667feb96a9433a7065 /arch/mips/txx9/rbtx4927
parentf6d9831bb11eb465f95fb1736b866d405d9c7cbf (diff)
MIPS: TXx9: Microoptimize interrupt handlers
The IOC interrupt status register on RBTX49XX only have 8 bits. Use 8-bit version of __fls() to optimize interrupt handlers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/rbtx4927')
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 22076e3f03a8..9c14ebb26cb4 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -133,9 +133,9 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
133 u8 level3; 133 u8 level3;
134 134
135 level3 = readb(rbtx4927_imstat_addr) & 0x1f; 135 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
136 if (level3) 136 if (unlikely(!level3))
137 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 137 return -1;
138 return sw_irq; 138 return RBTX4927_IRQ_IOC + __fls8(level3);
139} 139}
140 140
141static void __init toshiba_rbtx4927_irq_ioc_init(void) 141static void __init toshiba_rbtx4927_irq_ioc_init(void)