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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2006-12-28 12:22:32 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-02-18 16:31:37 -0500
commitc066a32a890c50ce59e91f8cea8eb5fd8d5821b9 (patch)
treed129af235d11d44c649f0743bc38535c3a229e41 /arch/mips/sni/setup.c
parent5759906ca9e5201c3fd40d61c861ec1e441d3a24 (diff)
[MIPS] Support for several more SNI RM models.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sni/setup.c')
-rw-r--r--arch/mips/sni/setup.c242
1 files changed, 27 insertions, 215 deletions
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index afeb7f13e5b5..68d7cf609b4f 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -6,16 +6,10 @@
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
9 */ 10 */
10#include <linux/eisa.h> 11#include <linux/eisa.h>
11#include <linux/hdreg.h>
12#include <linux/ioport.h>
13#include <linux/sched.h>
14#include <linux/init.h> 12#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/mc146818rtc.h>
17#include <linux/pm.h>
18#include <linux/pci.h>
19#include <linux/console.h> 13#include <linux/console.h>
20#include <linux/fb.h> 14#include <linux/fb.h>
21#include <linux/screen_info.h> 15#include <linux/screen_info.h>
@@ -25,52 +19,16 @@
25#include <asm/sgialib.h> 19#include <asm/sgialib.h>
26#endif 20#endif
27 21
28#include <asm/bcache.h>
29#include <asm/bootinfo.h>
30#include <asm/io.h> 22#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mc146818-time.h>
33#include <asm/processor.h>
34#include <asm/reboot.h> 23#include <asm/reboot.h>
35#include <asm/sni.h> 24#include <asm/sni.h>
36#include <asm/time.h> 25
37#include <asm/traps.h> 26unsigned int sni_brd_type;
38 27
39extern void sni_machine_restart(char *command); 28extern void sni_machine_restart(char *command);
40extern void sni_machine_halt(void); 29extern void sni_machine_halt(void);
41extern void sni_machine_power_off(void); 30extern void sni_machine_power_off(void);
42 31
43void __init plat_timer_setup(struct irqaction *irq)
44{
45 /* set the clock to 100 Hz */
46 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
47 outb_p(LATCH & 0xff , 0x40); /* LSB */
48 outb(LATCH >> 8 , 0x40); /* MSB */
49 setup_irq(0, irq);
50}
51
52/*
53 * A bit more gossip about the iron we're running on ...
54 */
55static inline void sni_pcimt_detect(void)
56{
57 char boardtype[80];
58 unsigned char csmsr;
59 char *p = boardtype;
60 unsigned int asic;
61
62 csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
63
64 p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
65 if ((csmsr & 0x80) == 0)
66 p += sprintf(p, ", board revision %s",
67 (csmsr & 0x20) ? "D" : "C");
68 asic = csmsr & 0x80;
69 asic = (csmsr & 0x08) ? asic : !asic;
70 p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
71 printk("%s.\n", boardtype);
72}
73
74static void __init sni_display_setup(void) 32static void __init sni_display_setup(void)
75{ 33{
76#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC) 34#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
@@ -90,175 +48,11 @@ static void __init sni_display_setup(void)
90#endif 48#endif
91} 49}
92 50
93static struct resource sni_io_resource = {
94 .start = 0x00001000UL,
95 .end = 0x03bfffffUL,
96 .name = "PCIMT IO MEM",
97 .flags = IORESOURCE_IO,
98};
99
100static struct resource pcimt_io_resources[] = {
101 {
102 .start = 0x00,
103 .end = 0x1f,
104 .name = "dma1",
105 .flags = IORESOURCE_BUSY
106 }, {
107 .start = 0x40,
108 .end = 0x5f,
109 .name = "timer",
110 .flags = IORESOURCE_BUSY
111 }, {
112 .start = 0x60,
113 .end = 0x6f,
114 .name = "keyboard",
115 .flags = IORESOURCE_BUSY
116 }, {
117 .start = 0x80,
118 .end = 0x8f,
119 .name = "dma page reg",
120 .flags = IORESOURCE_BUSY
121 }, {
122 .start = 0xc0,
123 .end = 0xdf,
124 .name = "dma2",
125 .flags = IORESOURCE_BUSY
126 }, {
127 .start = 0xcfc,
128 .end = 0xcff,
129 .name = "PCI config data",
130 .flags = IORESOURCE_BUSY
131 }
132};
133
134static struct resource sni_mem_resource = {
135 .start = 0x10000000UL,
136 .end = 0xffffffffUL,
137 .name = "PCIMT PCI MEM",
138 .flags = IORESOURCE_MEM
139};
140
141/*
142 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
143 * for other purposes. Be paranoid and allocate all of the before the PCI
144 * code gets a chance to to map anything else there ...
145 *
146 * This leaves the following areas available:
147 *
148 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
149 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
150 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
151 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
152 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
153 */
154static struct resource pcimt_mem_resources[] = {
155 {
156 .start = 0x100a0000,
157 .end = 0x100bffff,
158 .name = "Video RAM area",
159 .flags = IORESOURCE_BUSY
160 }, {
161 .start = 0x100c0000,
162 .end = 0x100fffff,
163 .name = "ISA Reserved",
164 .flags = IORESOURCE_BUSY
165 }, {
166 .start = 0x14000000,
167 .end = 0x17bfffff,
168 .name = "PCI IO",
169 .flags = IORESOURCE_BUSY
170 }, {
171 .start = 0x17c00000,
172 .end = 0x17ffffff,
173 .name = "Cache Replacement Area",
174 .flags = IORESOURCE_BUSY
175 }, {
176 .start = 0x1a000000,
177 .end = 0x1a000003,
178 .name = "PCI INT Acknowledge",
179 .flags = IORESOURCE_BUSY
180 }, {
181 .start = 0x1fc00000,
182 .end = 0x1fc7ffff,
183 .name = "Boot PROM",
184 .flags = IORESOURCE_BUSY
185 }, {
186 .start = 0x1fc80000,
187 .end = 0x1fcfffff,
188 .name = "Diag PROM",
189 .flags = IORESOURCE_BUSY
190 }, {
191 .start = 0x1fd00000,
192 .end = 0x1fdfffff,
193 .name = "X-Bus",
194 .flags = IORESOURCE_BUSY
195 }, {
196 .start = 0x1fe00000,
197 .end = 0x1fefffff,
198 .name = "BIOS map",
199 .flags = IORESOURCE_BUSY
200 }, {
201 .start = 0x1ff00000,
202 .end = 0x1ff7ffff,
203 .name = "NVRAM / EEPROM",
204 .flags = IORESOURCE_BUSY
205 }, {
206 .start = 0x1fff0000,
207 .end = 0x1fffefff,
208 .name = "ASIC PCI",
209 .flags = IORESOURCE_BUSY
210 }, {
211 .start = 0x1ffff000,
212 .end = 0x1fffffff,
213 .name = "MP Agent",
214 .flags = IORESOURCE_BUSY
215 }, {
216 .start = 0x20000000,
217 .end = 0x9fffffff,
218 .name = "Main Memory",
219 .flags = IORESOURCE_BUSY
220 }
221};
222
223static void __init sni_resource_init(void)
224{
225 int i;
226
227 /* request I/O space for devices used on all i[345]86 PCs */
228 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
229 request_resource(&ioport_resource, pcimt_io_resources + i);
230
231 /* request mem space for pcimt-specific devices */
232 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
233 request_resource(&sni_mem_resource, pcimt_mem_resources + i);
234
235 ioport_resource.end = sni_io_resource.end;
236}
237
238extern struct pci_ops sni_pci_ops;
239
240static struct pci_controller sni_controller = {
241 .pci_ops = &sni_pci_ops,
242 .mem_resource = &sni_mem_resource,
243 .mem_offset = 0x10000000UL,
244 .io_resource = &sni_io_resource,
245 .io_offset = 0x00000000UL
246};
247
248static inline void sni_pcimt_time_init(void)
249{
250 rtc_mips_get_time = mc146818_get_cmos_time;
251 rtc_mips_set_time = mc146818_set_rtc_mmss;
252}
253 51
254void __init plat_mem_setup(void) 52void __init plat_mem_setup(void)
255{ 53{
256 sni_pcimt_detect();
257 sni_pcimt_sc_init();
258 sni_pcimt_time_init();
259
260 set_io_port_base(SNI_PORT_BASE); 54 set_io_port_base(SNI_PORT_BASE);
261 ioport_resource.end = sni_io_resource.end; 55// ioport_resource.end = sni_io_resource.end;
262 56
263 /* 57 /*
264 * Setup (E)ISA I/O memory access stuff 58 * Setup (E)ISA I/O memory access stuff
@@ -268,15 +62,33 @@ void __init plat_mem_setup(void)
268 EISA_bus = 1; 62 EISA_bus = 1;
269#endif 63#endif
270 64
271 sni_resource_init(); 65 switch (sni_brd_type) {
66 case SNI_BRD_10:
67 case SNI_BRD_10NEW:
68 case SNI_BRD_TOWER_OASIC:
69 case SNI_BRD_MINITOWER:
70 sni_a20r_init();
71 break;
72
73 case SNI_BRD_PCI_TOWER:
74 case SNI_BRD_PCI_TOWER_CPLUS:
75 sni_pcit_init();
76 break;
77
78 case SNI_BRD_RM200:
79 sni_rm200_init();
80 break;
81
82 case SNI_BRD_PCI_MTOWER:
83 case SNI_BRD_PCI_DESKTOP:
84 case SNI_BRD_PCI_MTOWER_CPLUS:
85 sni_pcimt_init();
86 break;
87 }
272 88
273 _machine_restart = sni_machine_restart; 89 _machine_restart = sni_machine_restart;
274 _machine_halt = sni_machine_halt; 90 _machine_halt = sni_machine_halt;
275 pm_power_off = sni_machine_power_off; 91 pm_power_off = sni_machine_power_off;
276 92
277 sni_display_setup(); 93 sni_display_setup();
278
279#ifdef CONFIG_PCI
280 register_pci_controller(&sni_controller);
281#endif
282} 94}