MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8 files changed, 76 insertions, 76 deletions

diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 4a6057b35b9d..a0a79222ce0b 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -2,7 +2,7 @@
  * Basic EISA bus support for the SGI Indigo-2.
  *
  * (C) 2002 Pascal Dameme <netinet@freesurf.fr>
- *      and Marc Zyngier <mzyngier@freesurf.fr>
+ *      and Marc Zyngier <mzyngier@freesurf.fr>
  *
  * This code is released under both the GPL version 2 and BSD
  * licenses.  Either license may be used.
@@ -40,13 +40,13 @@
 
 /* I2 has four EISA slots. */
 #define IP22_EISA_MAX_SLOTS       4
-#define EISA_MAX_IRQ             16
+#define EISA_MAX_IRQ             16
 
-#define EIU_MODE_REG     0x0001ffc0
-#define EIU_STAT_REG     0x0001ffc4
-#define EIU_PREMPT_REG   0x0001ffc8
-#define EIU_QUIET_REG    0x0001ffcc
-#define EIU_INTRPT_ACK   0x00010004
+#define EIU_MODE_REG     0x0001ffc0
+#define EIU_STAT_REG     0x0001ffc4
+#define EIU_PREMPT_REG   0x0001ffc8
+#define EIU_QUIET_REG    0x0001ffcc
+#define EIU_INTRPT_ACK   0x00010004
 
 static char __init *decode_eisa_sig(unsigned long addr)
 {
diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c
index f5ebc092aed5..ab0e379dc7e0 100644
--- a/arch/mips/sgi-ip22/ip22-gio.c
+++ b/arch/mips/sgi-ip22/ip22-gio.c
@@ -15,7 +15,7 @@ static struct bus_type gio_bus_type;
 
 static struct {
         const char *name;
-        __u8       id;
+        __u8       id;
 } gio_name_table[] = {
         { .name = "SGI Impact", .id = 0x10 },
         { .name = "Phobos G160", .id = 0x35 },
@@ -376,15 +376,15 @@ static void ip22_check_gio(int slotno, unsigned long addr)
 }
 
 static struct bus_type gio_bus_type = {
-        .name      = "gio",
+        .name      = "gio",
         .dev_attrs = gio_dev_attrs,
-        .match     = gio_bus_match,
-        .probe     = gio_device_probe,
-        .remove    = gio_device_remove,
+        .match     = gio_bus_match,
+        .probe     = gio_device_probe,
+        .remove    = gio_device_remove,
         .suspend   = gio_device_suspend,
-        .resume    = gio_device_resume,
+        .resume    = gio_device_resume,
         .shutdown  = gio_device_shutdown,
-        .uevent    = gio_device_uevent,
+        .uevent    = gio_device_uevent,
 };
 
 static struct resource gio_bus_resource = {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 3f2b7633f946..3db64d51798d 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -1,12 +1,12 @@
 /*
  * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
- *             found on INDY and Indigo2 workstations.
+ *             found on INDY and Indigo2 workstations.
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
- *                    - Indigo2 changes
- *                    - Interrupt handling fixes
+ *                    - Indigo2 changes
+ *                    - Interrupt handling fixes
  * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
  */
 #include <linux/types.h>
@@ -195,24 +195,24 @@ extern void indy_8254timer_irq(void);
  * at all) like:
  *
  *      MIPS IRQ        Source
- *      --------        ------
- *             0        Software (ignored)
- *             1        Software (ignored)
- *             2        Local IRQ level zero
- *             3        Local IRQ level one
- *             4        8254 Timer zero
- *             5        8254 Timer one
- *             6        Bus Error
- *             7        R4k timer (what we use)
+ *      --------        ------
+ *             0        Software (ignored)
+ *             1        Software (ignored)
+ *             2        Local IRQ level zero
+ *             3        Local IRQ level one
+ *             4        8254 Timer zero
+ *             5        8254 Timer one
+ *             6        Bus Error
+ *             7        R4k timer (what we use)
  *
  * We handle the IRQ according to _our_ priority which is:
  *
- * Highest ----     R4k Timer
- *                  Local IRQ zero
- *                  Local IRQ one
- *                  Bus Error
- *                  8254 Timer zero
- * Lowest  ----     8254 Timer one
+ * Highest ----     R4k Timer
+ *                  Local IRQ zero
+ *                  Local IRQ one
+ *                  Bus Error
+ *                  8254 Timer zero
+ * Lowest  ----     8254 Timer one
  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index 75ada8a9713b..7cec0a4e527d 100644
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -121,22 +121,22 @@ void __init sgimc_init(void)
          */
 
         /* Step 0: Make sure we turn off the watchdog in case it's
-         *         still running (which might be the case after a
-         *         soft reboot).
+         *         still running (which might be the case after a
+         *         soft reboot).
          */
         tmp = sgimc->cpuctrl0;
         tmp &= ~SGIMC_CCTRL0_WDOG;
         sgimc->cpuctrl0 = tmp;
 
         /* Step 1: The CPU/GIO error status registers will not latch
-         *         up a new error status until the register has been
-         *         cleared by the cpu.  These status registers are
-         *         cleared by writing any value to them.
+         *         up a new error status until the register has been
+         *         cleared by the cpu.  These status registers are
+         *         cleared by writing any value to them.
          */
         sgimc->cstat = sgimc->gstat = 0;
 
         /* Step 2: Enable all parity checking in cpu control register
-         *         zero.
+         *         zero.
          */
         /* don't touch parity settings for IP28 */
         tmp = sgimc->cpuctrl0;
@@ -147,7 +147,7 @@ void __init sgimc_init(void)
         sgimc->cpuctrl0 = tmp;
 
         /* Step 3: Setup the MC write buffer depth, this is controlled
-         *         in cpu control register 1 in the lower 4 bits.
+         *         in cpu control register 1 in the lower 4 bits.
          */
         tmp = sgimc->cpuctrl1;
         tmp &= ~0xf;
@@ -155,26 +155,26 @@ void __init sgimc_init(void)
         sgimc->cpuctrl1 = tmp;
 
         /* Step 4: Initialize the RPSS divider register to run as fast
-         *         as it can correctly operate.  The register is laid
-         *         out as follows:
+         *         as it can correctly operate.  The register is laid
+         *         out as follows:
          *
-         *         ----------------------------------------
-         *         |  RESERVED  |   INCREMENT   | DIVIDER |
-         *         ----------------------------------------
-         *          31        16 15            8 7       0
+         *         ----------------------------------------
+         *         |  RESERVED  |   INCREMENT   | DIVIDER |
+         *         ----------------------------------------
+         *          31        16 15            8 7       0
          *
-         *         DIVIDER determines how often a 'tick' happens,
-         *         INCREMENT determines by how the RPSS increment
-         *         registers value increases at each 'tick'. Thus,
-         *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
+         *         DIVIDER determines how often a 'tick' happens,
+         *         INCREMENT determines by how the RPSS increment
+         *         registers value increases at each 'tick'. Thus,
+         *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
          */
         sgimc->divider = 0x101;
 
         /* Step 5: Initialize GIO64 arbitrator configuration register.
          *
          * NOTE: HPC init code in sgihpc_init() must run before us because
-         *       we need to know Guiness vs. FullHouse and the board
-         *       revision on this machine. You have been warned.
+         *       we need to know Guiness vs. FullHouse and the board
+         *       revision on this machine. You have been warned.
          */
 
         /* First the basic invariants across all GIO64 implementations. */
@@ -187,18 +187,18 @@ void __init sgimc_init(void)
                 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC at 64bits */
                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */
-                        tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
+                        tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
                         tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
                 } else {
                         tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC 64bits */
                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
                         tmp |= SGIMC_GIOPAR_PLINEEXP1;
-                        tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
+                        tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
                 }
         } else {
                 /* Guiness specific settings. */
                 tmp |= SGIMC_GIOPAR_EISA64;     /* MC talks to EISA at 64bits */
-                tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
+                tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
         }
         sgimc->giopar = tmp;    /* poof */
 
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
index 0177566475d4..e077036a676a 100644
--- a/arch/mips/sgi-ip22/ip22-nvram.c
+++ b/arch/mips/sgi-ip22/ip22-nvram.c
@@ -14,11 +14,11 @@
 #define EEPROM_WRITE    0xa000  /* serial memory write */
 #define EEPROM_WRALL    0x8800  /* write all registers */
 #define EEPROM_WDS      0x8000  /* disable all programming */
-#define EEPROM_PRREAD   0xc000  /* read protect register */
-#define EEPROM_PREN     0x9800  /* enable protect register mode */
-#define EEPROM_PRCLEAR  0xffff  /* clear protect register */
-#define EEPROM_PRWRITE  0xa000  /* write protect register */
-#define EEPROM_PRDS     0x8000  /* disable protect register, forever */
+#define EEPROM_PRREAD   0xc000  /* read protect register */
+#define EEPROM_PREN     0x9800  /* enable protect register mode */
+#define EEPROM_PRCLEAR  0xffff  /* clear protect register */
+#define EEPROM_PRWRITE  0xa000  /* write protect register */
+#define EEPROM_PRDS     0x8000  /* disable protect register, forever */
 
 #define EEPROM_EPROT    0x01    /* Protect register enable */
 #define EEPROM_CSEL     0x02    /* Chip select */
@@ -27,7 +27,7 @@
 #define EEPROM_DATI     0x10    /* Data in */
 
 /* We need to use these functions early... */
-#define delay() ({                                              \
+#define delay() ({                                              \
         int x;                                                  \
         for (x=0; x<100000; x++) __asm__ __volatile__(""); })
 
@@ -35,7 +35,7 @@
         __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr);     \
         __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr);     \
         __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr);    \
-        delay();                                                \
+        delay();                                                \
         __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr);      \
         __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 
@@ -46,7 +46,7 @@
         __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr);     \
         __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 
-#define BITS_IN_COMMAND 11
+#define BITS_IN_COMMAND 11
 /*
  * clock in the nvram command and the register number. For the
  * national semiconductor nv ram chip the op code is 3 bits and
diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index 698904daf901..a14fd32b76bd 100644
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -137,7 +137,7 @@ static int __init sgiseeq_devinit(void)
 
         eth0_pd.hpc = hpc3c0;
         eth0_pd.irq = SGI_ENET_IRQ;
-#define EADDR_NVOFS     250
+#define EADDR_NVOFS     250
         for (i = 0; i < 3; i++) {
                 unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i);
 
@@ -155,17 +155,17 @@ static int __init sgiseeq_devinit(void)
                 return 0;
 
         sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 |
-                         SGIMC_GIOPAR_HPC264;
+                         SGIMC_GIOPAR_HPC264;
         hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
         /* interrupt/config register on Challenge S Mezz board */
         hpc3c1->pbus_extregs[0][0] = 0x30;
 
         eth1_pd.hpc = hpc3c1;
         eth1_pd.irq = SGI_GIO_0_IRQ;
-#define EADDR_NVOFS     250
+#define EADDR_NVOFS     250
         for (i = 0; i < 3; i++) {
                 unsigned short tmp = ip22_eeprom_read(&hpc3c1->eeprom,
-                                                      EADDR_NVOFS / 2 + i);
+                                                      EADDR_NVOFS / 2 + i);
 
                 eth1_pd.mac[2 * i]     = tmp >> 8;
                 eth1_pd.mac[2 * i + 1] = tmp & 0xff;
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index 20363d29cb58..063c2dd31e72 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -101,7 +101,7 @@ static void debounce(unsigned long data)
         del_timer(&debounce_timer);
         if (sgint->istat1 & SGINT_ISTAT1_PWR) {
                 /* Interrupt still being sent. */
-                debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s  */
+                debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s  */
                 add_timer(&debounce_timer);
 
                 sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR |
@@ -166,7 +166,7 @@ static irqreturn_t panel_int(int irq, void *dev_id)
 }
 
 static int panic_event(struct notifier_block *this, unsigned long event,
-                      void *ptr)
+                      void *ptr)
 {
         if (machine_state & MACHINE_PANICED)
                 return NOTIFY_DONE;
diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c
index 0626555fd1a3..3f47346608d7 100644
--- a/arch/mips/sgi-ip22/ip28-berr.c
+++ b/arch/mips/sgi-ip22/ip28-berr.c
@@ -136,14 +136,14 @@ static void save_and_clear_buserr(void)
         hpc3.scsi[1].cbp   = hpc3c0->scsi_chan1.cbptr;
         hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
 
-        hpc3.ethrx.addr  = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
-        hpc3.ethrx.ctrl  = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
-        hpc3.ethrx.cbp   = hpc3c0->ethregs.rx_cbptr;
+        hpc3.ethrx.addr  = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
+        hpc3.ethrx.ctrl  = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
+        hpc3.ethrx.cbp   = hpc3c0->ethregs.rx_cbptr;
         hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
 
-        hpc3.ethtx.addr  = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
-        hpc3.ethtx.ctrl  = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
-        hpc3.ethtx.cbp   = hpc3c0->ethregs.tx_cbptr;
+        hpc3.ethtx.addr  = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
+        hpc3.ethtx.ctrl  = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
+        hpc3.ethtx.cbp   = hpc3c0->ethregs.tx_cbptr;
         hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
 
         for (i = 0; i < 8; ++i) {
@@ -196,11 +196,11 @@ static void print_cache_tags(void)
                         scb | (1 << 12)*i);
         }
         i = read_c0_config();
-        scb = i & (1 << 13) ? 7:6;      /* scblksize = 2^[7..6] */
+        scb = i & (1 << 13) ? 7:6;      /* scblksize = 2^[7..6] */
         scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
 
         i = ((1 << scw) - 1) & ~((1 << scb) - 1);
-        printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x  (PA[%u:%u] %05x)\n",
+        printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x  (PA[%u:%u] %05x)\n",
                 cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
                 cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
                 scw-1, scb, i & (unsigned)cache_tags.err_addr);