MIPS: ath79: replace ath724x to ar724x

Replace the 'ath724x' to 'ar724x' in function, variable and structure names to reflect the name of the real SoC. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: René Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3490/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
author: Gabor Juhos <juhosg@openwrt.org> 2012-03-14 05:29:26 -0400
committer: Ralf Baechle <ralf@linux-mips.org> 2012-05-15 11:49:02 -0400
commit: d624bd3cf7835612b25b9ec8db4002624c2dbb32 (patch)
tree: 64615a0cf44f613cd99e399257cb873c7c9c7eb1 /arch/mips/pci
parent: 692183ef12c4ba9dcdc9a54065ca92072cd79493 (diff)
1 files changed, 31 insertions, 31 deletions
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index ebefc165fae6..772d12c5fc9e 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -14,13 +14,13 @@
 #define reg_read(_phys)         (*(unsigned int *) KSEG1ADDR(_phys))
 #define reg_write(_phys, _val)  ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-#define ATH724X_PCI_DEV_BASE    0x14000000
+#define AR724X_PCI_DEV_BASE     0x14000000
-#define ATH724X_PCI_MEM_BASE    0x10000000
+#define AR724X_PCI_MEM_BASE     0x10000000
-#define ATH724X_PCI_MEM_SIZE    0x08000000
+#define AR724X_PCI_MEM_SIZE     0x08000000
-static DEFINE_SPINLOCK(ath724x_pci_lock);
+static DEFINE_SPINLOCK(ar724x_pci_lock);
-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                            int size, uint32_t *value)
 {
        unsigned long flags, addr, tval, mask;
@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
        if (where & (size - 1))
                return PCIBIOS_BAD_REGISTER_NUMBER;
-        spin_lock_irqsave(&ath724x_pci_lock, flags);
+        spin_lock_irqsave(&ar724x_pci_lock, flags);
        switch (size) {
        case 1:
                addr = where & ~3;
                mask = 0xff000000 >> ((where % 4) * 8);
-                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = reg_read(AR724X_PCI_DEV_BASE + addr);
                tval = tval & ~mask;
                *value = (tval >> ((4 - (where % 4))*8));
                break;
        case 2:
                addr = where & ~3;
                mask = 0xffff0000 >> ((where % 4)*8);
-                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = reg_read(AR724X_PCI_DEV_BASE + addr);
                tval = tval & ~mask;
                *value = (tval >> ((4 - (where % 4))*8));
                break;
        case 4:
-                *value = reg_read(ATH724X_PCI_DEV_BASE + where);
+                *value = reg_read(AR724X_PCI_DEV_BASE + where);
                break;
        default:
-                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+                spin_unlock_irqrestore(&ar724x_pci_lock, flags);
                return PCIBIOS_BAD_REGISTER_NUMBER;
        }
-        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+        spin_unlock_irqrestore(&ar724x_pci_lock, flags);
        return PCIBIOS_SUCCESSFUL;
 }
-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                             int size, uint32_t value)
 {
        unsigned long flags, tval, addr, mask;
@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
        if (where & (size - 1))
                return PCIBIOS_BAD_REGISTER_NUMBER;
-        spin_lock_irqsave(&ath724x_pci_lock, flags);
+        spin_lock_irqsave(&ar724x_pci_lock, flags);
        switch (size) {
        case 1:
-                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                addr = (AR724X_PCI_DEV_BASE + where) & ~3;
                mask = 0xff000000 >> ((where % 4)*8);
                tval = reg_read(addr);
                tval = tval & ~mask;
@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                reg_write(addr, tval);
                break;
        case 2:
-                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                addr = (AR724X_PCI_DEV_BASE + where) & ~3;
                mask = 0xffff0000 >> ((where % 4)*8);
                tval = reg_read(addr);
                tval = tval & ~mask;
@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                reg_write(addr, tval);
                break;
        case 4:
-                reg_write((ATH724X_PCI_DEV_BASE + where), value);
+                reg_write((AR724X_PCI_DEV_BASE + where), value);
                break;
        default:
-                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+                spin_unlock_irqrestore(&ar724x_pci_lock, flags);
                return PCIBIOS_BAD_REGISTER_NUMBER;
        }
-        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+        spin_unlock_irqrestore(&ar724x_pci_lock, flags);
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops ath724x_pci_ops = {
+static struct pci_ops ar724x_pci_ops = {
-        .read   = ath724x_pci_read,
+        .read   = ar724x_pci_read,
-        .write  = ath724x_pci_write,
+        .write  = ar724x_pci_write,
 };
-static struct resource ath724x_io_resource = {
+static struct resource ar724x_io_resource = {
        .name   = "PCI IO space",
        .start  = 0,
        .end    = 0,
        .flags  = IORESOURCE_IO,
 };
-static struct resource ath724x_mem_resource = {
+static struct resource ar724x_mem_resource = {
        .name   = "PCI memory space",
-        .start  = ATH724X_PCI_MEM_BASE,
+        .start  = AR724X_PCI_MEM_BASE,
-        .end    = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
+        .end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
        .flags  = IORESOURCE_MEM,
 };
-static struct pci_controller ath724x_pci_controller = {
+static struct pci_controller ar724x_pci_controller = {
-        .pci_ops        = &ath724x_pci_ops,
+        .pci_ops        = &ar724x_pci_ops,
-        .io_resource    = &ath724x_io_resource,
+        .io_resource    = &ar724x_io_resource,
-        .mem_resource   = &ath724x_mem_resource,
+        .mem_resource   = &ar724x_mem_resource,
 };
-int __init ath724x_pcibios_init(void)
+int __init ar724x_pcibios_init(void)
 {
-        register_pci_controller(&ath724x_pci_controller);
+        register_pci_controller(&ar724x_pci_controller);
        return PCIBIOS_SUCCESSFUL;
 }
author	Gabor Juhos <juhosg@openwrt.org>	2012-03-14 05:29:26 -0400
committer	Ralf Baechle <ralf@linux-mips.org>	2012-05-15 11:49:02 -0400
commit	d624bd3cf7835612b25b9ec8db4002624c2dbb32 (patch)
tree	64615a0cf44f613cd99e399257cb873c7c9c7eb1 /arch/mips/pci
parent	692183ef12c4ba9dcdc9a54065ca92072cd79493 (diff)

diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index ebefc165fae6..772d12c5fc9e 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c
@@ -14,13 +14,13 @@
14	#define reg_read(_phys) ((unsigned int ) KSEG1ADDR(_phys))	14	#define reg_read(_phys) ((unsigned int ) KSEG1ADDR(_phys))
15	#define reg_write(_phys, _val) (((unsigned int ) KSEG1ADDR(_phys)) = (_val))	15	#define reg_write(_phys, _val) (((unsigned int ) KSEG1ADDR(_phys)) = (_val))
16		16
17	#define ATH724X_PCI_DEV_BASE 0x14000000	17	#define AR724X_PCI_DEV_BASE 0x14000000
18	#define ATH724X_PCI_MEM_BASE 0x10000000	18	#define AR724X_PCI_MEM_BASE 0x10000000
19	#define ATH724X_PCI_MEM_SIZE 0x08000000	19	#define AR724X_PCI_MEM_SIZE 0x08000000
20		20
21	static DEFINE_SPINLOCK(ath724x_pci_lock);	21	static DEFINE_SPINLOCK(ar724x_pci_lock);
22		22
23	static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,	23	static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
24	int size, uint32_t *value)	24	int size, uint32_t *value)
25	{	25	{
26	unsigned long flags, addr, tval, mask;	26	unsigned long flags, addr, tval, mask;
@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
31	if (where & (size - 1))	31	if (where & (size - 1))
32	return PCIBIOS_BAD_REGISTER_NUMBER;	32	return PCIBIOS_BAD_REGISTER_NUMBER;
33		33
34	spin_lock_irqsave(&ath724x_pci_lock, flags);	34	spin_lock_irqsave(&ar724x_pci_lock, flags);
35		35
36	switch (size) {	36	switch (size) {
37	case 1:	37	case 1:
38	addr = where & ~3;	38	addr = where & ~3;
39	mask = 0xff000000 >> ((where % 4) * 8);	39	mask = 0xff000000 >> ((where % 4) * 8);
40	tval = reg_read(ATH724X_PCI_DEV_BASE + addr);	40	tval = reg_read(AR724X_PCI_DEV_BASE + addr);
41	tval = tval & ~mask;	41	tval = tval & ~mask;
42	value = (tval >> ((4 - (where % 4))8));	42	value = (tval >> ((4 - (where % 4))8));
43	break;	43	break;
44	case 2:	44	case 2:
45	addr = where & ~3;	45	addr = where & ~3;
46	mask = 0xffff0000 >> ((where % 4)*8);	46	mask = 0xffff0000 >> ((where % 4)*8);
47	tval = reg_read(ATH724X_PCI_DEV_BASE + addr);	47	tval = reg_read(AR724X_PCI_DEV_BASE + addr);
48	tval = tval & ~mask;	48	tval = tval & ~mask;
49	value = (tval >> ((4 - (where % 4))8));	49	value = (tval >> ((4 - (where % 4))8));
50	break;	50	break;
51	case 4:	51	case 4:
52	*value = reg_read(ATH724X_PCI_DEV_BASE + where);	52	*value = reg_read(AR724X_PCI_DEV_BASE + where);
53	break;	53	break;
54	default:	54	default:
55	spin_unlock_irqrestore(&ath724x_pci_lock, flags);	55	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
56		56
57	return PCIBIOS_BAD_REGISTER_NUMBER;	57	return PCIBIOS_BAD_REGISTER_NUMBER;
58	}	58	}
59		59
60	spin_unlock_irqrestore(&ath724x_pci_lock, flags);	60	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
61		61
62	return PCIBIOS_SUCCESSFUL;	62	return PCIBIOS_SUCCESSFUL;
63	}	63	}
64		64
65	static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,	65	static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
66	int size, uint32_t value)	66	int size, uint32_t value)
67	{	67	{
68	unsigned long flags, tval, addr, mask;	68	unsigned long flags, tval, addr, mask;
@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
73	if (where & (size - 1))	73	if (where & (size - 1))
74	return PCIBIOS_BAD_REGISTER_NUMBER;	74	return PCIBIOS_BAD_REGISTER_NUMBER;
75		75
76	spin_lock_irqsave(&ath724x_pci_lock, flags);	76	spin_lock_irqsave(&ar724x_pci_lock, flags);
77		77
78	switch (size) {	78	switch (size) {
79	case 1:	79	case 1:
80	addr = (ATH724X_PCI_DEV_BASE + where) & ~3;	80	addr = (AR724X_PCI_DEV_BASE + where) & ~3;
81	mask = 0xff000000 >> ((where % 4)*8);	81	mask = 0xff000000 >> ((where % 4)*8);
82	tval = reg_read(addr);	82	tval = reg_read(addr);
83	tval = tval & ~mask;	83	tval = tval & ~mask;
@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
85	reg_write(addr, tval);	85	reg_write(addr, tval);
86	break;	86	break;
87	case 2:	87	case 2:
88	addr = (ATH724X_PCI_DEV_BASE + where) & ~3;	88	addr = (AR724X_PCI_DEV_BASE + where) & ~3;
89	mask = 0xffff0000 >> ((where % 4)*8);	89	mask = 0xffff0000 >> ((where % 4)*8);
90	tval = reg_read(addr);	90	tval = reg_read(addr);
91	tval = tval & ~mask;	91	tval = tval & ~mask;
@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
93	reg_write(addr, tval);	93	reg_write(addr, tval);
94	break;	94	break;
95	case 4:	95	case 4:
96	reg_write((ATH724X_PCI_DEV_BASE + where), value);	96	reg_write((AR724X_PCI_DEV_BASE + where), value);
97	break;	97	break;
98	default:	98	default:
99	spin_unlock_irqrestore(&ath724x_pci_lock, flags);	99	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
100		100
101	return PCIBIOS_BAD_REGISTER_NUMBER;	101	return PCIBIOS_BAD_REGISTER_NUMBER;
102	}	102	}
103		103
104	spin_unlock_irqrestore(&ath724x_pci_lock, flags);	104	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
105		105
106	return PCIBIOS_SUCCESSFUL;	106	return PCIBIOS_SUCCESSFUL;
107	}	107	}
108		108
109	static struct pci_ops ath724x_pci_ops = {	109	static struct pci_ops ar724x_pci_ops = {
110	.read = ath724x_pci_read,	110	.read = ar724x_pci_read,
111	.write = ath724x_pci_write,	111	.write = ar724x_pci_write,
112	};	112	};
113		113
114	static struct resource ath724x_io_resource = {	114	static struct resource ar724x_io_resource = {
115	.name = "PCI IO space",	115	.name = "PCI IO space",
116	.start = 0,	116	.start = 0,
117	.end = 0,	117	.end = 0,
118	.flags = IORESOURCE_IO,	118	.flags = IORESOURCE_IO,
119	};	119	};
120		120
121	static struct resource ath724x_mem_resource = {	121	static struct resource ar724x_mem_resource = {
122	.name = "PCI memory space",	122	.name = "PCI memory space",
123	.start = ATH724X_PCI_MEM_BASE,	123	.start = AR724X_PCI_MEM_BASE,
124	.end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,	124	.end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
125	.flags = IORESOURCE_MEM,	125	.flags = IORESOURCE_MEM,
126	};	126	};
127		127
128	static struct pci_controller ath724x_pci_controller = {	128	static struct pci_controller ar724x_pci_controller = {
129	.pci_ops = &ath724x_pci_ops,	129	.pci_ops = &ar724x_pci_ops,
130	.io_resource = &ath724x_io_resource,	130	.io_resource = &ar724x_io_resource,
131	.mem_resource = &ath724x_mem_resource,	131	.mem_resource = &ar724x_mem_resource,
132	};	132	};
133		133
134	int __init ath724x_pcibios_init(void)	134	int __init ar724x_pcibios_init(void)
135	{	135	{
136	register_pci_controller(&ath724x_pci_controller);	136	register_pci_controller(&ar724x_pci_controller);
137		137
138	return PCIBIOS_SUCCESSFUL;	138	return PCIBIOS_SUCCESSFUL;
139	}	139	}