MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 15 insertions, 15 deletions

diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 5b5ed76c6f47..95c2ea815cac 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -30,8 +30,8 @@
  * addresses. Use PCI endian swapping 1 so no address swapping is
  * necessary. The Linux io routines will endian swap the data.
  */
-#define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
-#define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
+#define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
+#define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
 
 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
@@ -68,10 +68,10 @@ enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux
- *               enumerates through all the bridges and figures out the
- *               slot on Bus 0 where this device eventually hooks to.
+ *               enumerates through all the bridges and figures out the
+ *               slot on Bus 0 where this device eventually hooks to.
  * @pin:    The PCI interrupt pin read from the device, then swizzled
- *               as it goes through each bridge.
+ *               as it goes through each bridge.
  * Returns Interrupt number for the device
  */
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -120,8 +120,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         /* Enable the PCIe normal error reporting */
         config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
         config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
-        config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
-        config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
+        config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+        config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
 
         /* Find the Advanced Error Reporting capability */
@@ -226,10 +226,10 @@ const char *octeon_get_pci_interrupts(void)
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux
- *               enumerates through all the bridges and figures out the
- *               slot on Bus 0 where this device eventually hooks to.
+ *               enumerates through all the bridges and figures out the
+ *               slot on Bus 0 where this device eventually hooks to.
  * @pin:    The PCI interrupt pin read from the device, then swizzled
- *               as it goes through each bridge.
+ *               as it goes through each bridge.
  * Returns Interrupt number for the device
  */
 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
@@ -404,8 +404,8 @@ static void octeon_pci_initialize(void)
                 ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
                 ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
                 ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
-                ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
-                ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
+                ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
+                ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
         }
 
         octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
@@ -446,7 +446,7 @@ static void octeon_pci_initialize(void)
                  * count. [1..31] and 0=32.  NOTE: If the user
                  * programs these bits beyond the Designed Maximum
                  * outstanding count, then the designed maximum table
-                 * depth will be used instead.  No additional
+                 * depth will be used instead.  No additional
                  * Deferred/Split transactions will be accepted if
                  * this outstanding maximum count is
                  * reached. Furthermore, no additional deferred/split
@@ -456,7 +456,7 @@ static void octeon_pci_initialize(void)
                 cfg19.s.tdomc = 4;
                 /*
                  * Master Deferred Read Request Outstanding Max Count
-                 * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
+                 * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
                  * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
                  * 5 2 110 6 3 111 7 3 For example, if these bits are
                  * programmed to 100, the core can support 2 DAC
@@ -550,7 +550,7 @@ static void octeon_pci_initialize(void)
 
         /*
          * Affects PCI performance when OCTEON services reads to its
-         * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
+         * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
          * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
          * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
          * these values need to be changed so they won't possibly prefetch off